arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 serial2 = &uart2;
  23                 serial3 = &uart3;
  24                 serial4 = &uart4;
  25                 serial5 = &uart5;
  26         };
  27
  28
  29         cpus {
  30                 enable-method = "allwinner,sun6i-a31";
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a7";
  36                         device_type = "cpu";
  37                         reg = <0>;
  38                 };
  39
  40                 cpu@1 {
  41                         compatible = "arm,cortex-a7";
  42                         device_type = "cpu";
  43                         reg = <1>;
  44                 };
  45
  46                 cpu@2 {
  47                         compatible = "arm,cortex-a7";
  48                         device_type = "cpu";
  49                         reg = <2>;
  50                 };
  51
  52                 cpu@3 {
  53                         compatible = "arm,cortex-a7";
  54                         device_type = "cpu";
  55                         reg = <3>;
  56                 };
  57         };
  58
  59         memory {
  60                 reg = <0x40000000 0x80000000>;
  61         };
  62
  63         pmu {
  64                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
  65                 interrupts = <0 120 4>,
  66                              <0 121 4>,
  67                              <0 122 4>,
  68                              <0 123 4>;
  69         };
  70
  71         clocks {
  72                 #address-cells = <1>;
  73                 #size-cells = <1>;
  74                 ranges;
  75
  76                 osc24M: osc24M {
  77                         #clock-cells = <0>;
  78                         compatible = "fixed-clock";
  79                         clock-frequency = <24000000>;
  80                 };
  81
  82                 osc32k: clk@0 {
  83                         #clock-cells = <0>;
  84                         compatible = "fixed-clock";
  85                         clock-frequency = <32768>;
  86                         clock-output-names = "osc32k";
  87                 };
  88
  89                 pll1: clk@01c20000 {
  90                         #clock-cells = <0>;
  91                         compatible = "allwinner,sun6i-a31-pll1-clk";
  92                         reg = <0x01c20000 0x4>;
  93                         clocks = <&osc24M>;
  94                         clock-output-names = "pll1";
  95                 };
  96
  97                 pll6: clk@01c20028 {
  98                         #clock-cells = <0>;
  99                         compatible = "allwinner,sun6i-a31-pll6-clk";
 100                         reg = <0x01c20028 0x4>;
 101                         clocks = <&osc24M>;
 102                         clock-output-names = "pll6";
 103                 };
 104
 105                 cpu: cpu@01c20050 {
 106                         #clock-cells = <0>;
 107                         compatible = "allwinner,sun4i-a10-cpu-clk";
 108                         reg = <0x01c20050 0x4>;
 109
 110                         /*
 111                          * PLL1 is listed twice here.
 112                          * While it looks suspicious, it's actually documented
 113                          * that way both in the datasheet and in the code from
 114                          * Allwinner.
 115                          */
 116                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 117                         clock-output-names = "cpu";
 118                 };
 119
 120                 axi: axi@01c20050 {
 121                         #clock-cells = <0>;
 122                         compatible = "allwinner,sun4i-a10-axi-clk";
 123                         reg = <0x01c20050 0x4>;
 124                         clocks = <&cpu>;
 125                         clock-output-names = "axi";
 126                 };
 127
 128                 ahb1_mux: ahb1_mux@01c20054 {
 129                         #clock-cells = <0>;
 130                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 131                         reg = <0x01c20054 0x4>;
 132                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 133                         clock-output-names = "ahb1_mux";
 134                 };
 135
 136                 ahb1: ahb1@01c20054 {
 137                         #clock-cells = <0>;
 138                         compatible = "allwinner,sun4i-a10-ahb-clk";
 139                         reg = <0x01c20054 0x4>;
 140                         clocks = <&ahb1_mux>;
 141                         clock-output-names = "ahb1";
 142                 };
 143
 144                 ahb1_gates: clk@01c20060 {
 145                         #clock-cells = <1>;
 146                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 147                         reg = <0x01c20060 0x8>;
 148                         clocks = <&ahb1>;
 149                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 150                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 151                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 152                                         "ahb1_nand0", "ahb1_sdram",
 153                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 154                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 155                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 156                                         "ahb1_ehci1", "ahb1_ohci0",
 157                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 158                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 159                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 160                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 161                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 162                                         "ahb1_drc0", "ahb1_drc1";
 163                 };
 164
 165                 apb1: apb1@01c20054 {
 166                         #clock-cells = <0>;
 167                         compatible = "allwinner,sun4i-a10-apb0-clk";
 168                         reg = <0x01c20054 0x4>;
 169                         clocks = <&ahb1>;
 170                         clock-output-names = "apb1";
 171                 };
 172
 173                 apb1_gates: clk@01c20068 {
 174                         #clock-cells = <1>;
 175                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 176                         reg = <0x01c20068 0x4>;
 177                         clocks = <&apb1>;
 178                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 179                                         "apb1_pio", "apb1_daudio0",
 180                                         "apb1_daudio1";
 181                 };
 182
 183                 apb2_mux: apb2_mux@01c20058 {
 184                         #clock-cells = <0>;
 185                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 186                         reg = <0x01c20058 0x4>;
 187                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 188                         clock-output-names = "apb2_mux";
 189                 };
 190
 191                 apb2: apb2@01c20058 {
 192                         #clock-cells = <0>;
 193                         compatible = "allwinner,sun6i-a31-apb2-div-clk";
 194                         reg = <0x01c20058 0x4>;
 195                         clocks = <&apb2_mux>;
 196                         clock-output-names = "apb2";
 197                 };
 198
 199                 apb2_gates: clk@01c2006c {
 200                         #clock-cells = <1>;
 201                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 202                         reg = <0x01c2006c 0x4>;
 203                         clocks = <&apb2>;
 204                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 205                                         "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
 206                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
 207                                         "apb2_uart4", "apb2_uart5";
 208                 };
 209
 210                 mmc0_clk: clk@01c20088 {
 211                         #clock-cells = <0>;
 212                         compatible = "allwinner,sun4i-a10-mod0-clk";
 213                         reg = <0x01c20088 0x4>;
 214                         clocks = <&osc24M>, <&pll6>;
 215                         clock-output-names = "mmc0";
 216                 };
 217
 218                 mmc1_clk: clk@01c2008c {
 219                         #clock-cells = <0>;
 220                         compatible = "allwinner,sun4i-a10-mod0-clk";
 221                         reg = <0x01c2008c 0x4>;
 222                         clocks = <&osc24M>, <&pll6>;
 223                         clock-output-names = "mmc1";
 224                 };
 225
 226                 mmc2_clk: clk@01c20090 {
 227                         #clock-cells = <0>;
 228                         compatible = "allwinner,sun4i-a10-mod0-clk";
 229                         reg = <0x01c20090 0x4>;
 230                         clocks = <&osc24M>, <&pll6>;
 231                         clock-output-names = "mmc2";
 232                 };
 233
 234                 mmc3_clk: clk@01c20094 {
 235                         #clock-cells = <0>;
 236                         compatible = "allwinner,sun4i-a10-mod0-clk";
 237                         reg = <0x01c20094 0x4>;
 238                         clocks = <&osc24M>, <&pll6>;
 239                         clock-output-names = "mmc3";
 240                 };
 241
 242                 spi0_clk: clk@01c200a0 {
 243                         #clock-cells = <0>;
 244                         compatible = "allwinner,sun4i-a10-mod0-clk";
 245                         reg = <0x01c200a0 0x4>;
 246                         clocks = <&osc24M>, <&pll6>;
 247                         clock-output-names = "spi0";
 248                 };
 249
 250                 spi1_clk: clk@01c200a4 {
 251                         #clock-cells = <0>;
 252                         compatible = "allwinner,sun4i-a10-mod0-clk";
 253                         reg = <0x01c200a4 0x4>;
 254                         clocks = <&osc24M>, <&pll6>;
 255                         clock-output-names = "spi1";
 256                 };
 257
 258                 spi2_clk: clk@01c200a8 {
 259                         #clock-cells = <0>;
 260                         compatible = "allwinner,sun4i-a10-mod0-clk";
 261                         reg = <0x01c200a8 0x4>;
 262                         clocks = <&osc24M>, <&pll6>;
 263                         clock-output-names = "spi2";
 264                 };
 265
 266                 spi3_clk: clk@01c200ac {
 267                         #clock-cells = <0>;
 268                         compatible = "allwinner,sun4i-a10-mod0-clk";
 269                         reg = <0x01c200ac 0x4>;
 270                         clocks = <&osc24M>, <&pll6>;
 271                         clock-output-names = "spi3";
 272                 };
 273
 274                 usb_clk: clk@01c200cc {
 275                         #clock-cells = <1>;
 276                         #reset-cells = <1>;
 277                         compatible = "allwinner,sun6i-a31-usb-clk";
 278                         reg = <0x01c200cc 0x4>;
 279                         clocks = <&osc24M>;
 280                         clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
 281                                              "usb_ohci0", "usb_ohci1",
 282                                              "usb_ohci2";
 283                 };
 284         };
 285
 286         soc@01c00000 {
 287                 compatible = "simple-bus";
 288                 #address-cells = <1>;
 289                 #size-cells = <1>;
 290                 ranges;
 291
 292                 dma: dma-controller@01c02000 {
 293                         compatible = "allwinner,sun6i-a31-dma";
 294                         reg = <0x01c02000 0x1000>;
 295                         interrupts = <0 50 4>;
 296                         clocks = <&ahb1_gates 6>;
 297                         resets = <&ahb1_rst 6>;
 298                         #dma-cells = <1>;
 299                 };
 300
 301                 mmc0: mmc@01c0f000 {
 302                         compatible = "allwinner,sun5i-a13-mmc";
 303                         reg = <0x01c0f000 0x1000>;
 304                         clocks = <&ahb1_gates 8>, <&mmc0_clk>;
 305                         clock-names = "ahb", "mmc";
 306                         resets = <&ahb1_rst 8>;
 307                         reset-names = "ahb";
 308                         interrupts = <0 60 4>;
 309                         status = "disabled";
 310                 };
 311
 312                 mmc1: mmc@01c10000 {
 313                         compatible = "allwinner,sun5i-a13-mmc";
 314                         reg = <0x01c10000 0x1000>;
 315                         clocks = <&ahb1_gates 9>, <&mmc1_clk>;
 316                         clock-names = "ahb", "mmc";
 317                         resets = <&ahb1_rst 9>;
 318                         reset-names = "ahb";
 319                         interrupts = <0 61 4>;
 320                         status = "disabled";
 321                 };
 322
 323                 mmc2: mmc@01c11000 {
 324                         compatible = "allwinner,sun5i-a13-mmc";
 325                         reg = <0x01c11000 0x1000>;
 326                         clocks = <&ahb1_gates 10>, <&mmc2_clk>;
 327                         clock-names = "ahb", "mmc";
 328                         resets = <&ahb1_rst 10>;
 329                         reset-names = "ahb";
 330                         interrupts = <0 62 4>;
 331                         status = "disabled";
 332                 };
 333
 334                 mmc3: mmc@01c12000 {
 335                         compatible = "allwinner,sun5i-a13-mmc";
 336                         reg = <0x01c12000 0x1000>;
 337                         clocks = <&ahb1_gates 11>, <&mmc3_clk>;
 338                         clock-names = "ahb", "mmc";
 339                         resets = <&ahb1_rst 11>;
 340                         reset-names = "ahb";
 341                         interrupts = <0 63 4>;
 342                         status = "disabled";
 343                 };
 344
 345                 usbphy: phy@01c19400 {
 346                         compatible = "allwinner,sun6i-a31-usb-phy";
 347                         reg = <0x01c19400 0x10>,
 348                               <0x01c1a800 0x4>,
 349                               <0x01c1b800 0x4>;
 350                         reg-names = "phy_ctrl",
 351                                     "pmu1",
 352                                     "pmu2";
 353                         clocks = <&usb_clk 8>,
 354                                  <&usb_clk 9>,
 355                                  <&usb_clk 10>;
 356                         clock-names = "usb0_phy",
 357                                       "usb1_phy",
 358                                       "usb2_phy";
 359                         resets = <&usb_clk 0>,
 360                                  <&usb_clk 1>,
 361                                  <&usb_clk 2>;
 362                         reset-names = "usb0_reset",
 363                                       "usb1_reset",
 364                                       "usb2_reset";
 365                         status = "disabled";
 366                         #phy-cells = <1>;
 367                 };
 368
 369                 ehci0: usb@01c1a000 {
 370                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 371                         reg = <0x01c1a000 0x100>;
 372                         interrupts = <0 72 4>;
 373                         clocks = <&ahb1_gates 26>;
 374                         resets = <&ahb1_rst 26>;
 375                         phys = <&usbphy 1>;
 376                         phy-names = "usb";
 377                         status = "disabled";
 378                 };
 379
 380                 ohci0: usb@01c1a400 {
 381                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 382                         reg = <0x01c1a400 0x100>;
 383                         interrupts = <0 73 4>;
 384                         clocks = <&ahb1_gates 29>, <&usb_clk 16>;
 385                         resets = <&ahb1_rst 29>;
 386                         phys = <&usbphy 1>;
 387                         phy-names = "usb";
 388                         status = "disabled";
 389                 };
 390
 391                 ehci1: usb@01c1b000 {
 392                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 393                         reg = <0x01c1b000 0x100>;
 394                         interrupts = <0 74 4>;
 395                         clocks = <&ahb1_gates 27>;
 396                         resets = <&ahb1_rst 27>;
 397                         phys = <&usbphy 2>;
 398                         phy-names = "usb";
 399                         status = "disabled";
 400                 };
 401
 402                 ohci1: usb@01c1b400 {
 403                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 404                         reg = <0x01c1b400 0x100>;
 405                         interrupts = <0 75 4>;
 406                         clocks = <&ahb1_gates 30>, <&usb_clk 17>;
 407                         resets = <&ahb1_rst 30>;
 408                         phys = <&usbphy 2>;
 409                         phy-names = "usb";
 410                         status = "disabled";
 411                 };
 412
 413                 ohci2: usb@01c1c400 {
 414                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 415                         reg = <0x01c1c400 0x100>;
 416                         interrupts = <0 77 4>;
 417                         clocks = <&ahb1_gates 31>, <&usb_clk 18>;
 418                         resets = <&ahb1_rst 31>;
 419                         status = "disabled";
 420                 };
 421
 422                 pio: pinctrl@01c20800 {
 423                         compatible = "allwinner,sun6i-a31-pinctrl";
 424                         reg = <0x01c20800 0x400>;
 425                         interrupts = <0 11 4>,
 426                                      <0 15 4>,
 427                                      <0 16 4>,
 428                                      <0 17 4>;
 429                         clocks = <&apb1_gates 5>;
 430                         gpio-controller;
 431                         interrupt-controller;
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         #gpio-cells = <3>;
 435
 436                         uart0_pins_a: uart0@0 {
 437                                 allwinner,pins = "PH20", "PH21";
 438                                 allwinner,function = "uart0";
 439                                 allwinner,drive = <0>;
 440                                 allwinner,pull = <0>;
 441                         };
 442
 443                         i2c0_pins_a: i2c0@0 {
 444                                 allwinner,pins = "PH14", "PH15";
 445                                 allwinner,function = "i2c0";
 446                                 allwinner,drive = <0>;
 447                                 allwinner,pull = <0>;
 448                         };
 449
 450                         i2c1_pins_a: i2c1@0 {
 451                                 allwinner,pins = "PH16", "PH17";
 452                                 allwinner,function = "i2c1";
 453                                 allwinner,drive = <0>;
 454                                 allwinner,pull = <0>;
 455                         };
 456
 457                         i2c2_pins_a: i2c2@0 {
 458                                 allwinner,pins = "PH18", "PH19";
 459                                 allwinner,function = "i2c2";
 460                                 allwinner,drive = <0>;
 461                                 allwinner,pull = <0>;
 462                         };
 463
 464                         mmc0_pins_a: mmc0@0 {
 465                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 466                                 allwinner,function = "mmc0";
 467                                 allwinner,drive = <2>;
 468                                 allwinner,pull = <0>;
 469                         };
 470                 };
 471
 472                 ahb1_rst: reset@01c202c0 {
 473                         #reset-cells = <1>;
 474                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 475                         reg = <0x01c202c0 0xc>;
 476                 };
 477
 478                 apb1_rst: reset@01c202d0 {
 479                         #reset-cells = <1>;
 480                         compatible = "allwinner,sun6i-a31-clock-reset";
 481                         reg = <0x01c202d0 0x4>;
 482                 };
 483
 484                 apb2_rst: reset@01c202d8 {
 485                         #reset-cells = <1>;
 486                         compatible = "allwinner,sun6i-a31-clock-reset";
 487                         reg = <0x01c202d8 0x4>;
 488                 };
 489
 490                 timer@01c20c00 {
 491                         compatible = "allwinner,sun4i-a10-timer";
 492                         reg = <0x01c20c00 0xa0>;
 493                         interrupts = <0 18 4>,
 494                                      <0 19 4>,
 495                                      <0 20 4>,
 496                                      <0 21 4>,
 497                                      <0 22 4>;
 498                         clocks = <&osc24M>;
 499                 };
 500
 501                 wdt1: watchdog@01c20ca0 {
 502                         compatible = "allwinner,sun6i-a31-wdt";
 503                         reg = <0x01c20ca0 0x20>;
 504                 };
 505
 506                 uart0: serial@01c28000 {
 507                         compatible = "snps,dw-apb-uart";
 508                         reg = <0x01c28000 0x400>;
 509                         interrupts = <0 0 4>;
 510                         reg-shift = <2>;
 511                         reg-io-width = <4>;
 512                         clocks = <&apb2_gates 16>;
 513                         resets = <&apb2_rst 16>;
 514                         dmas = <&dma 6>, <&dma 6>;
 515                         dma-names = "rx", "tx";
 516                         status = "disabled";
 517                 };
 518
 519                 uart1: serial@01c28400 {
 520                         compatible = "snps,dw-apb-uart";
 521                         reg = <0x01c28400 0x400>;
 522                         interrupts = <0 1 4>;
 523                         reg-shift = <2>;
 524                         reg-io-width = <4>;
 525                         clocks = <&apb2_gates 17>;
 526                         resets = <&apb2_rst 17>;
 527                         dmas = <&dma 7>, <&dma 7>;
 528                         dma-names = "rx", "tx";
 529                         status = "disabled";
 530                 };
 531
 532                 uart2: serial@01c28800 {
 533                         compatible = "snps,dw-apb-uart";
 534                         reg = <0x01c28800 0x400>;
 535                         interrupts = <0 2 4>;
 536                         reg-shift = <2>;
 537                         reg-io-width = <4>;
 538                         clocks = <&apb2_gates 18>;
 539                         resets = <&apb2_rst 18>;
 540                         dmas = <&dma 8>, <&dma 8>;
 541                         dma-names = "rx", "tx";
 542                         status = "disabled";
 543                 };
 544
 545                 uart3: serial@01c28c00 {
 546                         compatible = "snps,dw-apb-uart";
 547                         reg = <0x01c28c00 0x400>;
 548                         interrupts = <0 3 4>;
 549                         reg-shift = <2>;
 550                         reg-io-width = <4>;
 551                         clocks = <&apb2_gates 19>;
 552                         resets = <&apb2_rst 19>;
 553                         dmas = <&dma 9>, <&dma 9>;
 554                         dma-names = "rx", "tx";
 555                         status = "disabled";
 556                 };
 557
 558                 uart4: serial@01c29000 {
 559                         compatible = "snps,dw-apb-uart";
 560                         reg = <0x01c29000 0x400>;
 561                         interrupts = <0 4 4>;
 562                         reg-shift = <2>;
 563                         reg-io-width = <4>;
 564                         clocks = <&apb2_gates 20>;
 565                         resets = <&apb2_rst 20>;
 566                         dmas = <&dma 10>, <&dma 10>;
 567                         dma-names = "rx", "tx";
 568                         status = "disabled";
 569                 };
 570
 571                 uart5: serial@01c29400 {
 572                         compatible = "snps,dw-apb-uart";
 573                         reg = <0x01c29400 0x400>;
 574                         interrupts = <0 5 4>;
 575                         reg-shift = <2>;
 576                         reg-io-width = <4>;
 577                         clocks = <&apb2_gates 21>;
 578                         resets = <&apb2_rst 21>;
 579                         dmas = <&dma 22>, <&dma 22>;
 580                         dma-names = "rx", "tx";
 581                         status = "disabled";
 582                 };
 583
 584                 i2c0: i2c@01c2ac00 {
 585                         compatible = "allwinner,sun6i-a31-i2c";
 586                         reg = <0x01c2ac00 0x400>;
 587                         interrupts = <0 6 4>;
 588                         clocks = <&apb2_gates 0>;
 589                         clock-frequency = <100000>;
 590                         resets = <&apb2_rst 0>;
 591                         status = "disabled";
 592                 };
 593
 594                 i2c1: i2c@01c2b000 {
 595                         compatible = "allwinner,sun6i-a31-i2c";
 596                         reg = <0x01c2b000 0x400>;
 597                         interrupts = <0 7 4>;
 598                         clocks = <&apb2_gates 1>;
 599                         clock-frequency = <100000>;
 600                         resets = <&apb2_rst 1>;
 601                         status = "disabled";
 602                 };
 603
 604                 i2c2: i2c@01c2b400 {
 605                         compatible = "allwinner,sun6i-a31-i2c";
 606                         reg = <0x01c2b400 0x400>;
 607                         interrupts = <0 8 4>;
 608                         clocks = <&apb2_gates 2>;
 609                         clock-frequency = <100000>;
 610                         resets = <&apb2_rst 2>;
 611                         status = "disabled";
 612                 };
 613
 614                 i2c3: i2c@01c2b800 {
 615                         compatible = "allwinner,sun6i-a31-i2c";
 616                         reg = <0x01c2b800 0x400>;
 617                         interrupts = <0 9 4>;
 618                         clocks = <&apb2_gates 3>;
 619                         clock-frequency = <100000>;
 620                         resets = <&apb2_rst 3>;
 621                         status = "disabled";
 622                 };
 623
 624                 timer@01c60000 {
 625                         compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
 626                         reg = <0x01c60000 0x1000>;
 627                         interrupts = <0 51 4>,
 628                                      <0 52 4>,
 629                                      <0 53 4>,
 630                                      <0 54 4>;
 631                         clocks = <&ahb1_gates 19>;
 632                         resets = <&ahb1_rst 19>;
 633                 };
 634
 635                 spi0: spi@01c68000 {
 636                         compatible = "allwinner,sun6i-a31-spi";
 637                         reg = <0x01c68000 0x1000>;
 638                         interrupts = <0 65 4>;
 639                         clocks = <&ahb1_gates 20>, <&spi0_clk>;
 640                         clock-names = "ahb", "mod";
 641                         dmas = <&dma 23>, <&dma 23>;
 642                         dma-names = "rx", "tx";
 643                         resets = <&ahb1_rst 20>;
 644                         status = "disabled";
 645                 };
 646
 647                 spi1: spi@01c69000 {
 648                         compatible = "allwinner,sun6i-a31-spi";
 649                         reg = <0x01c69000 0x1000>;
 650                         interrupts = <0 66 4>;
 651                         clocks = <&ahb1_gates 21>, <&spi1_clk>;
 652                         clock-names = "ahb", "mod";
 653                         dmas = <&dma 24>, <&dma 24>;
 654                         dma-names = "rx", "tx";
 655                         resets = <&ahb1_rst 21>;
 656                         status = "disabled";
 657                 };
 658
 659                 spi2: spi@01c6a000 {
 660                         compatible = "allwinner,sun6i-a31-spi";
 661                         reg = <0x01c6a000 0x1000>;
 662                         interrupts = <0 67 4>;
 663                         clocks = <&ahb1_gates 22>, <&spi2_clk>;
 664                         clock-names = "ahb", "mod";
 665                         dmas = <&dma 25>, <&dma 25>;
 666                         dma-names = "rx", "tx";
 667                         resets = <&ahb1_rst 22>;
 668                         status = "disabled";
 669                 };
 670
 671                 spi3: spi@01c6b000 {
 672                         compatible = "allwinner,sun6i-a31-spi";
 673                         reg = <0x01c6b000 0x1000>;
 674                         interrupts = <0 68 4>;
 675                         clocks = <&ahb1_gates 23>, <&spi3_clk>;
 676                         clock-names = "ahb", "mod";
 677                         dmas = <&dma 26>, <&dma 26>;
 678                         dma-names = "rx", "tx";
 679                         resets = <&ahb1_rst 23>;
 680                         status = "disabled";
 681                 };
 682
 683                 gic: interrupt-controller@01c81000 {
 684                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 685                         reg = <0x01c81000 0x1000>,
 686                               <0x01c82000 0x1000>,
 687                               <0x01c84000 0x2000>,
 688                               <0x01c86000 0x2000>;
 689                         interrupt-controller;
 690                         #interrupt-cells = <3>;
 691                         interrupts = <1 9 0xf04>;
 692                 };
 693
 694                 nmi_intc: interrupt-controller@01f00c0c {
 695                         compatible = "allwinner,sun6i-a31-sc-nmi";
 696                         interrupt-controller;
 697                         #interrupt-cells = <2>;
 698                         reg = <0x01f00c0c 0x38>;
 699                         interrupts = <0 32 4>;
 700                 };
 701
 702                 prcm@01f01400 {
 703                         compatible = "allwinner,sun6i-a31-prcm";
 704                         reg = <0x01f01400 0x200>;
 705
 706                         ar100: ar100_clk {
 707                                 compatible = "allwinner,sun6i-a31-ar100-clk";
 708                                 #clock-cells = <0>;
 709                                 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 710                                 clock-output-names = "ar100";
 711                         };
 712
 713                         ahb0: ahb0_clk {
 714                                 compatible = "fixed-factor-clock";
 715                                 #clock-cells = <0>;
 716                                 clock-div = <1>;
 717                                 clock-mult = <1>;
 718                                 clocks = <&ar100>;
 719                                 clock-output-names = "ahb0";
 720                         };
 721
 722                         apb0: apb0_clk {
 723                                 compatible = "allwinner,sun6i-a31-apb0-clk";
 724                                 #clock-cells = <0>;
 725                                 clocks = <&ahb0>;
 726                                 clock-output-names = "apb0";
 727                         };
 728
 729                         apb0_gates: apb0_gates_clk {
 730                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
 731                                 #clock-cells = <1>;
 732                                 clocks = <&apb0>;
 733                                 clock-output-names = "apb0_pio", "apb0_ir",
 734                                                 "apb0_timer", "apb0_p2wi",
 735                                                 "apb0_uart", "apb0_1wire",
 736                                                 "apb0_i2c";
 737                         };
 738
 739                         apb0_rst: apb0_rst {
 740                                 compatible = "allwinner,sun6i-a31-clock-reset";
 741                                 #reset-cells = <1>;
 742                         };
 743                 };
 744
 745                 cpucfg@01f01c00 {
 746                         compatible = "allwinner,sun6i-a31-cpuconfig";
 747                         reg = <0x01f01c00 0x300>;
 748                 };
 749
 750                 r_pio: pinctrl@01f02c00 {
 751                         compatible = "allwinner,sun6i-a31-r-pinctrl";
 752                         reg = <0x01f02c00 0x400>;
 753                         interrupts = <0 45 4>,
 754                                      <0 46 4>;
 755                         clocks = <&apb0_gates 0>;
 756                         resets = <&apb0_rst 0>;
 757                         gpio-controller;
 758                         interrupt-controller;
 759                         #address-cells = <1>;
 760                         #size-cells = <0>;
 761                         #gpio-cells = <3>;
 762                 };
 763         };
 764 };