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Merge tag 'topic/designware-baytrail-2017-03-02' of git://anongit.freedesktop.org...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sun6i-a31.dtsi
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include "skeleton.dtsi"
46
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53
54 / {
55 interrupt-parent = <&gic>;
56
57 aliases {
58 ethernet0 = &gmac;
59 };
60
61 chosen {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65
66 simplefb_hdmi: framebuffer@0 {
67 compatible = "allwinner,simple-framebuffer",
68 "simple-framebuffer";
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
71 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
72 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
73 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
74 status = "disabled";
75 };
76
77 simplefb_lcd: framebuffer@1 {
78 compatible = "allwinner,simple-framebuffer",
79 "simple-framebuffer";
80 allwinner,pipeline = "de_be0-lcd0";
81 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
82 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
83 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
84 status = "disabled";
85 };
86 };
87
88 timer {
89 compatible = "arm,armv7-timer";
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
94 clock-frequency = <24000000>;
95 arm,cpu-registers-not-fw-configured;
96 };
97
98 cpus {
99 enable-method = "allwinner,sun6i-a31";
100 #address-cells = <1>;
101 #size-cells = <0>;
102
103 cpu0: cpu@0 {
104 compatible = "arm,cortex-a7";
105 device_type = "cpu";
106 reg = <0>;
107 clocks = <&ccu CLK_CPU>;
108 clock-latency = <244144>; /* 8 32k periods */
109 operating-points = <
110 /* kHz uV */
111 1008000 1200000
112 864000 1200000
113 720000 1100000
114 480000 1000000
115 >;
116 #cooling-cells = <2>;
117 cooling-min-level = <0>;
118 cooling-max-level = <3>;
119 };
120
121 cpu@1 {
122 compatible = "arm,cortex-a7";
123 device_type = "cpu";
124 reg = <1>;
125 };
126
127 cpu@2 {
128 compatible = "arm,cortex-a7";
129 device_type = "cpu";
130 reg = <2>;
131 };
132
133 cpu@3 {
134 compatible = "arm,cortex-a7";
135 device_type = "cpu";
136 reg = <3>;
137 };
138 };
139
140 thermal-zones {
141 cpu_thermal {
142 /* milliseconds */
143 polling-delay-passive = <250>;
144 polling-delay = <1000>;
145 thermal-sensors = <&rtp>;
146
147 cooling-maps {
148 map0 {
149 trip = <&cpu_alert0>;
150 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
151 };
152 };
153
154 trips {
155 cpu_alert0: cpu_alert0 {
156 /* milliCelsius */
157 temperature = <70000>;
158 hysteresis = <2000>;
159 type = "passive";
160 };
161
162 cpu_crit: cpu_crit {
163 /* milliCelsius */
164 temperature = <100000>;
165 hysteresis = <2000>;
166 type = "critical";
167 };
168 };
169 };
170 };
171
172 memory {
173 reg = <0x40000000 0x80000000>;
174 };
175
176 pmu {
177 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
178 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
182 };
183
184 clocks {
185 #address-cells = <1>;
186 #size-cells = <1>;
187 ranges;
188
189 osc24M: osc24M {
190 #clock-cells = <0>;
191 compatible = "fixed-clock";
192 clock-frequency = <24000000>;
193 };
194
195 osc32k: clk@0 {
196 #clock-cells = <0>;
197 compatible = "fixed-clock";
198 clock-frequency = <32768>;
199 clock-output-names = "osc32k";
200 };
201
202 /*
203 * The following two are dummy clocks, placeholders
204 * used in the gmac_tx clock. The gmac driver will
205 * choose one parent depending on the PHY interface
206 * mode, using clk_set_rate auto-reparenting.
207 *
208 * The actual TX clock rate is not controlled by the
209 * gmac_tx clock.
210 */
211 mii_phy_tx_clk: clk@1 {
212 #clock-cells = <0>;
213 compatible = "fixed-clock";
214 clock-frequency = <25000000>;
215 clock-output-names = "mii_phy_tx";
216 };
217
218 gmac_int_tx_clk: clk@2 {
219 #clock-cells = <0>;
220 compatible = "fixed-clock";
221 clock-frequency = <125000000>;
222 clock-output-names = "gmac_int_tx";
223 };
224
225 gmac_tx_clk: clk@01c200d0 {
226 #clock-cells = <0>;
227 compatible = "allwinner,sun7i-a20-gmac-clk";
228 reg = <0x01c200d0 0x4>;
229 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
230 clock-output-names = "gmac_tx";
231 };
232 };
233
234 de: display-engine {
235 compatible = "allwinner,sun6i-a31-display-engine";
236 allwinner,pipelines = <&fe0>;
237 status = "disabled";
238 };
239
240 soc@01c00000 {
241 compatible = "simple-bus";
242 #address-cells = <1>;
243 #size-cells = <1>;
244 ranges;
245
246 dma: dma-controller@01c02000 {
247 compatible = "allwinner,sun6i-a31-dma";
248 reg = <0x01c02000 0x1000>;
249 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&ccu CLK_AHB1_DMA>;
251 resets = <&ccu RST_AHB1_DMA>;
252 #dma-cells = <1>;
253 };
254
255 tcon0: lcd-controller@01c0c000 {
256 compatible = "allwinner,sun6i-a31-tcon";
257 reg = <0x01c0c000 0x1000>;
258 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
259 resets = <&ccu RST_AHB1_LCD0>;
260 reset-names = "lcd";
261 clocks = <&ccu CLK_AHB1_LCD0>,
262 <&ccu CLK_LCD0_CH0>,
263 <&ccu CLK_LCD0_CH1>;
264 clock-names = "ahb",
265 "tcon-ch0",
266 "tcon-ch1";
267 clock-output-names = "tcon0-pixel-clock";
268 status = "disabled";
269
270 ports {
271 #address-cells = <1>;
272 #size-cells = <0>;
273
274 tcon0_in: port@0 {
275 #address-cells = <1>;
276 #size-cells = <0>;
277 reg = <0>;
278
279 tcon0_in_drc0: endpoint@0 {
280 reg = <0>;
281 remote-endpoint = <&drc0_out_tcon0>;
282 };
283 };
284
285 tcon0_out: port@1 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 reg = <1>;
289 };
290 };
291 };
292
293 mmc0: mmc@01c0f000 {
294 compatible = "allwinner,sun7i-a20-mmc";
295 reg = <0x01c0f000 0x1000>;
296 clocks = <&ccu CLK_AHB1_MMC0>,
297 <&ccu CLK_MMC0>,
298 <&ccu CLK_MMC0_OUTPUT>,
299 <&ccu CLK_MMC0_SAMPLE>;
300 clock-names = "ahb",
301 "mmc",
302 "output",
303 "sample";
304 resets = <&ccu RST_AHB1_MMC0>;
305 reset-names = "ahb";
306 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
307 status = "disabled";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 };
311
312 mmc1: mmc@01c10000 {
313 compatible = "allwinner,sun7i-a20-mmc";
314 reg = <0x01c10000 0x1000>;
315 clocks = <&ccu CLK_AHB1_MMC1>,
316 <&ccu CLK_MMC1>,
317 <&ccu CLK_MMC1_OUTPUT>,
318 <&ccu CLK_MMC1_SAMPLE>;
319 clock-names = "ahb",
320 "mmc",
321 "output",
322 "sample";
323 resets = <&ccu RST_AHB1_MMC1>;
324 reset-names = "ahb";
325 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
326 status = "disabled";
327 #address-cells = <1>;
328 #size-cells = <0>;
329 };
330
331 mmc2: mmc@01c11000 {
332 compatible = "allwinner,sun7i-a20-mmc";
333 reg = <0x01c11000 0x1000>;
334 clocks = <&ccu CLK_AHB1_MMC2>,
335 <&ccu CLK_MMC2>,
336 <&ccu CLK_MMC2_OUTPUT>,
337 <&ccu CLK_MMC2_SAMPLE>;
338 clock-names = "ahb",
339 "mmc",
340 "output",
341 "sample";
342 resets = <&ccu RST_AHB1_MMC2>;
343 reset-names = "ahb";
344 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
345 status = "disabled";
346 #address-cells = <1>;
347 #size-cells = <0>;
348 };
349
350 mmc3: mmc@01c12000 {
351 compatible = "allwinner,sun7i-a20-mmc";
352 reg = <0x01c12000 0x1000>;
353 clocks = <&ccu CLK_AHB1_MMC3>,
354 <&ccu CLK_MMC3>,
355 <&ccu CLK_MMC3_OUTPUT>,
356 <&ccu CLK_MMC3_SAMPLE>;
357 clock-names = "ahb",
358 "mmc",
359 "output",
360 "sample";
361 resets = <&ccu RST_AHB1_MMC3>;
362 reset-names = "ahb";
363 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
364 status = "disabled";
365 #address-cells = <1>;
366 #size-cells = <0>;
367 };
368
369 usb_otg: usb@01c19000 {
370 compatible = "allwinner,sun6i-a31-musb";
371 reg = <0x01c19000 0x0400>;
372 clocks = <&ccu CLK_AHB1_OTG>;
373 resets = <&ccu RST_AHB1_OTG>;
374 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-names = "mc";
376 phys = <&usbphy 0>;
377 phy-names = "usb";
378 extcon = <&usbphy 0>;
379 status = "disabled";
380 };
381
382 usbphy: phy@01c19400 {
383 compatible = "allwinner,sun6i-a31-usb-phy";
384 reg = <0x01c19400 0x10>,
385 <0x01c1a800 0x4>,
386 <0x01c1b800 0x4>;
387 reg-names = "phy_ctrl",
388 "pmu1",
389 "pmu2";
390 clocks = <&ccu CLK_USB_PHY0>,
391 <&ccu CLK_USB_PHY1>,
392 <&ccu CLK_USB_PHY2>;
393 clock-names = "usb0_phy",
394 "usb1_phy",
395 "usb2_phy";
396 resets = <&ccu RST_USB_PHY0>,
397 <&ccu RST_USB_PHY1>,
398 <&ccu RST_USB_PHY2>;
399 reset-names = "usb0_reset",
400 "usb1_reset",
401 "usb2_reset";
402 status = "disabled";
403 #phy-cells = <1>;
404 };
405
406 ehci0: usb@01c1a000 {
407 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
408 reg = <0x01c1a000 0x100>;
409 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&ccu CLK_AHB1_EHCI0>;
411 resets = <&ccu RST_AHB1_EHCI0>;
412 phys = <&usbphy 1>;
413 phy-names = "usb";
414 status = "disabled";
415 };
416
417 ohci0: usb@01c1a400 {
418 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
419 reg = <0x01c1a400 0x100>;
420 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
422 resets = <&ccu RST_AHB1_OHCI0>;
423 phys = <&usbphy 1>;
424 phy-names = "usb";
425 status = "disabled";
426 };
427
428 ehci1: usb@01c1b000 {
429 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
430 reg = <0x01c1b000 0x100>;
431 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_AHB1_EHCI1>;
433 resets = <&ccu RST_AHB1_EHCI1>;
434 phys = <&usbphy 2>;
435 phy-names = "usb";
436 status = "disabled";
437 };
438
439 ohci1: usb@01c1b400 {
440 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
441 reg = <0x01c1b400 0x100>;
442 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
444 resets = <&ccu RST_AHB1_OHCI1>;
445 phys = <&usbphy 2>;
446 phy-names = "usb";
447 status = "disabled";
448 };
449
450 ohci2: usb@01c1c400 {
451 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
452 reg = <0x01c1c400 0x100>;
453 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
455 resets = <&ccu RST_AHB1_OHCI2>;
456 status = "disabled";
457 };
458
459 ccu: clock@01c20000 {
460 compatible = "allwinner,sun6i-a31-ccu";
461 reg = <0x01c20000 0x400>;
462 clocks = <&osc24M>, <&osc32k>;
463 clock-names = "hosc", "losc";
464 #clock-cells = <1>;
465 #reset-cells = <1>;
466 };
467
468 pio: pinctrl@01c20800 {
469 compatible = "allwinner,sun6i-a31-pinctrl";
470 reg = <0x01c20800 0x400>;
471 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
476 clock-names = "apb", "hosc", "losc";
477 gpio-controller;
478 interrupt-controller;
479 #interrupt-cells = <3>;
480 #gpio-cells = <3>;
481
482 gmac_pins_gmii_a: gmac_gmii@0 {
483 pins = "PA0", "PA1", "PA2", "PA3",
484 "PA4", "PA5", "PA6", "PA7",
485 "PA8", "PA9", "PA10", "PA11",
486 "PA12", "PA13", "PA14", "PA15",
487 "PA16", "PA17", "PA18", "PA19",
488 "PA20", "PA21", "PA22", "PA23",
489 "PA24", "PA25", "PA26", "PA27";
490 function = "gmac";
491 /*
492 * data lines in GMII mode run at 125MHz and
493 * might need a higher signal drive strength
494 */
495 drive-strength = <30>;
496 };
497
498 gmac_pins_mii_a: gmac_mii@0 {
499 pins = "PA0", "PA1", "PA2", "PA3",
500 "PA8", "PA9", "PA11",
501 "PA12", "PA13", "PA14", "PA19",
502 "PA20", "PA21", "PA22", "PA23",
503 "PA24", "PA26", "PA27";
504 function = "gmac";
505 };
506
507 gmac_pins_rgmii_a: gmac_rgmii@0 {
508 pins = "PA0", "PA1", "PA2", "PA3",
509 "PA9", "PA10", "PA11",
510 "PA12", "PA13", "PA14", "PA19",
511 "PA20", "PA25", "PA26", "PA27";
512 function = "gmac";
513 /*
514 * data lines in RGMII mode use DDR mode
515 * and need a higher signal drive strength
516 */
517 drive-strength = <40>;
518 };
519
520 i2c0_pins_a: i2c0@0 {
521 pins = "PH14", "PH15";
522 function = "i2c0";
523 };
524
525 i2c1_pins_a: i2c1@0 {
526 pins = "PH16", "PH17";
527 function = "i2c1";
528 };
529
530 i2c2_pins_a: i2c2@0 {
531 pins = "PH18", "PH19";
532 function = "i2c2";
533 };
534
535 lcd0_rgb888_pins: lcd0_rgb888 {
536 pins = "PD0", "PD1", "PD2", "PD3",
537 "PD4", "PD5", "PD6", "PD7",
538 "PD8", "PD9", "PD10", "PD11",
539 "PD12", "PD13", "PD14", "PD15",
540 "PD16", "PD17", "PD18", "PD19",
541 "PD20", "PD21", "PD22", "PD23",
542 "PD24", "PD25", "PD26", "PD27";
543 function = "lcd0";
544 };
545
546 mmc0_pins_a: mmc0@0 {
547 pins = "PF0", "PF1", "PF2",
548 "PF3", "PF4", "PF5";
549 function = "mmc0";
550 drive-strength = <30>;
551 bias-pull-up;
552 };
553
554 mmc1_pins_a: mmc1@0 {
555 pins = "PG0", "PG1", "PG2", "PG3",
556 "PG4", "PG5";
557 function = "mmc1";
558 drive-strength = <30>;
559 bias-pull-up;
560 };
561
562 mmc2_pins_a: mmc2@0 {
563 pins = "PC6", "PC7", "PC8", "PC9",
564 "PC10", "PC11";
565 function = "mmc2";
566 drive-strength = <30>;
567 bias-pull-up;
568 };
569
570 mmc2_8bit_emmc_pins: mmc2@1 {
571 pins = "PC6", "PC7", "PC8", "PC9",
572 "PC10", "PC11", "PC12",
573 "PC13", "PC14", "PC15",
574 "PC24";
575 function = "mmc2";
576 drive-strength = <30>;
577 bias-pull-up;
578 };
579
580 mmc3_8bit_emmc_pins: mmc3@1 {
581 pins = "PC6", "PC7", "PC8", "PC9",
582 "PC10", "PC11", "PC12",
583 "PC13", "PC14", "PC15",
584 "PC24";
585 function = "mmc3";
586 drive-strength = <40>;
587 bias-pull-up;
588 };
589
590 spdif_pins_a: spdif@0 {
591 pins = "PH28";
592 function = "spdif";
593 };
594
595 uart0_pins_a: uart0@0 {
596 pins = "PH20", "PH21";
597 function = "uart0";
598 };
599 };
600
601 timer@01c20c00 {
602 compatible = "allwinner,sun4i-a10-timer";
603 reg = <0x01c20c00 0xa0>;
604 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&osc24M>;
610 };
611
612 wdt1: watchdog@01c20ca0 {
613 compatible = "allwinner,sun6i-a31-wdt";
614 reg = <0x01c20ca0 0x20>;
615 };
616
617 spdif: spdif@01c21000 {
618 #sound-dai-cells = <0>;
619 compatible = "allwinner,sun6i-a31-spdif";
620 reg = <0x01c21000 0x400>;
621 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
623 resets = <&ccu RST_APB1_SPDIF>;
624 clock-names = "apb", "spdif";
625 dmas = <&dma 2>, <&dma 2>;
626 dma-names = "rx", "tx";
627 status = "disabled";
628 };
629
630 lradc: lradc@01c22800 {
631 compatible = "allwinner,sun4i-a10-lradc-keys";
632 reg = <0x01c22800 0x100>;
633 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
634 status = "disabled";
635 };
636
637 rtp: rtp@01c25000 {
638 compatible = "allwinner,sun6i-a31-ts";
639 reg = <0x01c25000 0x100>;
640 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
641 #thermal-sensor-cells = <0>;
642 };
643
644 uart0: serial@01c28000 {
645 compatible = "snps,dw-apb-uart";
646 reg = <0x01c28000 0x400>;
647 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
648 reg-shift = <2>;
649 reg-io-width = <4>;
650 clocks = <&ccu CLK_APB2_UART0>;
651 resets = <&ccu RST_APB2_UART0>;
652 dmas = <&dma 6>, <&dma 6>;
653 dma-names = "rx", "tx";
654 status = "disabled";
655 };
656
657 uart1: serial@01c28400 {
658 compatible = "snps,dw-apb-uart";
659 reg = <0x01c28400 0x400>;
660 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
661 reg-shift = <2>;
662 reg-io-width = <4>;
663 clocks = <&ccu CLK_APB2_UART1>;
664 resets = <&ccu RST_APB2_UART1>;
665 dmas = <&dma 7>, <&dma 7>;
666 dma-names = "rx", "tx";
667 status = "disabled";
668 };
669
670 uart2: serial@01c28800 {
671 compatible = "snps,dw-apb-uart";
672 reg = <0x01c28800 0x400>;
673 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
674 reg-shift = <2>;
675 reg-io-width = <4>;
676 clocks = <&ccu CLK_APB2_UART2>;
677 resets = <&ccu RST_APB2_UART2>;
678 dmas = <&dma 8>, <&dma 8>;
679 dma-names = "rx", "tx";
680 status = "disabled";
681 };
682
683 uart3: serial@01c28c00 {
684 compatible = "snps,dw-apb-uart";
685 reg = <0x01c28c00 0x400>;
686 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
687 reg-shift = <2>;
688 reg-io-width = <4>;
689 clocks = <&ccu CLK_APB2_UART3>;
690 resets = <&ccu RST_APB2_UART3>;
691 dmas = <&dma 9>, <&dma 9>;
692 dma-names = "rx", "tx";
693 status = "disabled";
694 };
695
696 uart4: serial@01c29000 {
697 compatible = "snps,dw-apb-uart";
698 reg = <0x01c29000 0x400>;
699 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
700 reg-shift = <2>;
701 reg-io-width = <4>;
702 clocks = <&ccu CLK_APB2_UART4>;
703 resets = <&ccu RST_APB2_UART4>;
704 dmas = <&dma 10>, <&dma 10>;
705 dma-names = "rx", "tx";
706 status = "disabled";
707 };
708
709 uart5: serial@01c29400 {
710 compatible = "snps,dw-apb-uart";
711 reg = <0x01c29400 0x400>;
712 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
713 reg-shift = <2>;
714 reg-io-width = <4>;
715 clocks = <&ccu CLK_APB2_UART5>;
716 resets = <&ccu RST_APB2_UART5>;
717 dmas = <&dma 22>, <&dma 22>;
718 dma-names = "rx", "tx";
719 status = "disabled";
720 };
721
722 i2c0: i2c@01c2ac00 {
723 compatible = "allwinner,sun6i-a31-i2c";
724 reg = <0x01c2ac00 0x400>;
725 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&ccu CLK_APB2_I2C0>;
727 resets = <&ccu RST_APB2_I2C0>;
728 status = "disabled";
729 #address-cells = <1>;
730 #size-cells = <0>;
731 };
732
733 i2c1: i2c@01c2b000 {
734 compatible = "allwinner,sun6i-a31-i2c";
735 reg = <0x01c2b000 0x400>;
736 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&ccu CLK_APB2_I2C1>;
738 resets = <&ccu RST_APB2_I2C1>;
739 status = "disabled";
740 #address-cells = <1>;
741 #size-cells = <0>;
742 };
743
744 i2c2: i2c@01c2b400 {
745 compatible = "allwinner,sun6i-a31-i2c";
746 reg = <0x01c2b400 0x400>;
747 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&ccu CLK_APB2_I2C2>;
749 resets = <&ccu RST_APB2_I2C2>;
750 status = "disabled";
751 #address-cells = <1>;
752 #size-cells = <0>;
753 };
754
755 i2c3: i2c@01c2b800 {
756 compatible = "allwinner,sun6i-a31-i2c";
757 reg = <0x01c2b800 0x400>;
758 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&ccu CLK_APB2_I2C3>;
760 resets = <&ccu RST_APB2_I2C3>;
761 status = "disabled";
762 #address-cells = <1>;
763 #size-cells = <0>;
764 };
765
766 gmac: ethernet@01c30000 {
767 compatible = "allwinner,sun7i-a20-gmac";
768 reg = <0x01c30000 0x1054>;
769 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
770 interrupt-names = "macirq";
771 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
772 clock-names = "stmmaceth", "allwinner_gmac_tx";
773 resets = <&ccu RST_AHB1_EMAC>;
774 reset-names = "stmmaceth";
775 snps,pbl = <2>;
776 snps,fixed-burst;
777 snps,force_sf_dma_mode;
778 status = "disabled";
779 #address-cells = <1>;
780 #size-cells = <0>;
781 };
782
783 crypto: crypto-engine@01c15000 {
784 compatible = "allwinner,sun4i-a10-crypto";
785 reg = <0x01c15000 0x1000>;
786 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
788 clock-names = "ahb", "mod";
789 resets = <&ccu RST_AHB1_SS>;
790 reset-names = "ahb";
791 };
792
793 codec: codec@01c22c00 {
794 #sound-dai-cells = <0>;
795 compatible = "allwinner,sun6i-a31-codec";
796 reg = <0x01c22c00 0x400>;
797 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
799 clock-names = "apb", "codec";
800 resets = <&ccu RST_APB1_CODEC>;
801 dmas = <&dma 15>, <&dma 15>;
802 dma-names = "rx", "tx";
803 status = "disabled";
804 };
805
806 timer@01c60000 {
807 compatible = "allwinner,sun6i-a31-hstimer",
808 "allwinner,sun7i-a20-hstimer";
809 reg = <0x01c60000 0x1000>;
810 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&ccu CLK_AHB1_HSTIMER>;
815 resets = <&ccu RST_AHB1_HSTIMER>;
816 };
817
818 spi0: spi@01c68000 {
819 compatible = "allwinner,sun6i-a31-spi";
820 reg = <0x01c68000 0x1000>;
821 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
823 clock-names = "ahb", "mod";
824 dmas = <&dma 23>, <&dma 23>;
825 dma-names = "rx", "tx";
826 resets = <&ccu RST_AHB1_SPI0>;
827 status = "disabled";
828 };
829
830 spi1: spi@01c69000 {
831 compatible = "allwinner,sun6i-a31-spi";
832 reg = <0x01c69000 0x1000>;
833 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
835 clock-names = "ahb", "mod";
836 dmas = <&dma 24>, <&dma 24>;
837 dma-names = "rx", "tx";
838 resets = <&ccu RST_AHB1_SPI1>;
839 status = "disabled";
840 };
841
842 spi2: spi@01c6a000 {
843 compatible = "allwinner,sun6i-a31-spi";
844 reg = <0x01c6a000 0x1000>;
845 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
847 clock-names = "ahb", "mod";
848 dmas = <&dma 25>, <&dma 25>;
849 dma-names = "rx", "tx";
850 resets = <&ccu RST_AHB1_SPI2>;
851 status = "disabled";
852 };
853
854 spi3: spi@01c6b000 {
855 compatible = "allwinner,sun6i-a31-spi";
856 reg = <0x01c6b000 0x1000>;
857 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
859 clock-names = "ahb", "mod";
860 dmas = <&dma 26>, <&dma 26>;
861 dma-names = "rx", "tx";
862 resets = <&ccu RST_AHB1_SPI3>;
863 status = "disabled";
864 };
865
866 gic: interrupt-controller@01c81000 {
867 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
868 reg = <0x01c81000 0x1000>,
869 <0x01c82000 0x2000>,
870 <0x01c84000 0x2000>,
871 <0x01c86000 0x2000>;
872 interrupt-controller;
873 #interrupt-cells = <3>;
874 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
875 };
876
877 fe0: display-frontend@01e00000 {
878 compatible = "allwinner,sun6i-a31-display-frontend";
879 reg = <0x01e00000 0x20000>;
880 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
882 <&ccu CLK_DRAM_FE0>;
883 clock-names = "ahb", "mod",
884 "ram";
885 resets = <&ccu RST_AHB1_FE0>;
886
887 ports {
888 #address-cells = <1>;
889 #size-cells = <0>;
890
891 fe0_out: port@1 {
892 #address-cells = <1>;
893 #size-cells = <0>;
894 reg = <1>;
895
896 fe0_out_be0: endpoint@0 {
897 reg = <0>;
898 remote-endpoint = <&be0_in_fe0>;
899 };
900 };
901 };
902 };
903
904 be0: display-backend@01e60000 {
905 compatible = "allwinner,sun6i-a31-display-backend";
906 reg = <0x01e60000 0x10000>;
907 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
909 <&ccu CLK_DRAM_BE0>;
910 clock-names = "ahb", "mod",
911 "ram";
912 resets = <&ccu RST_AHB1_BE0>;
913
914 assigned-clocks = <&ccu CLK_BE0>;
915 assigned-clock-rates = <300000000>;
916
917 ports {
918 #address-cells = <1>;
919 #size-cells = <0>;
920
921 be0_in: port@0 {
922 #address-cells = <1>;
923 #size-cells = <0>;
924 reg = <0>;
925
926 be0_in_fe0: endpoint@0 {
927 reg = <0>;
928 remote-endpoint = <&fe0_out_be0>;
929 };
930 };
931
932 be0_out: port@1 {
933 #address-cells = <1>;
934 #size-cells = <0>;
935 reg = <1>;
936
937 be0_out_drc0: endpoint@0 {
938 reg = <0>;
939 remote-endpoint = <&drc0_in_be0>;
940 };
941 };
942 };
943 };
944
945 drc0: drc@01e70000 {
946 compatible = "allwinner,sun6i-a31-drc";
947 reg = <0x01e70000 0x10000>;
948 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
950 <&ccu CLK_DRAM_DRC0>;
951 clock-names = "ahb", "mod",
952 "ram";
953 resets = <&ccu RST_AHB1_DRC0>;
954
955 assigned-clocks = <&ccu CLK_IEP_DRC0>;
956 assigned-clock-rates = <300000000>;
957
958 ports {
959 #address-cells = <1>;
960 #size-cells = <0>;
961
962 drc0_in: port@0 {
963 #address-cells = <1>;
964 #size-cells = <0>;
965 reg = <0>;
966
967 drc0_in_be0: endpoint@0 {
968 reg = <0>;
969 remote-endpoint = <&be0_out_drc0>;
970 };
971 };
972
973 drc0_out: port@1 {
974 #address-cells = <1>;
975 #size-cells = <0>;
976 reg = <1>;
977
978 drc0_out_tcon0: endpoint@0 {
979 reg = <0>;
980 remote-endpoint = <&tcon0_in_drc0>;
981 };
982 };
983 };
984 };
985
986 rtc: rtc@01f00000 {
987 compatible = "allwinner,sun6i-a31-rtc";
988 reg = <0x01f00000 0x54>;
989 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
991 };
992
993 nmi_intc: interrupt-controller@01f00c0c {
994 compatible = "allwinner,sun6i-a31-sc-nmi";
995 interrupt-controller;
996 #interrupt-cells = <2>;
997 reg = <0x01f00c0c 0x38>;
998 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
999 };
1000
1001 prcm@01f01400 {
1002 compatible = "allwinner,sun6i-a31-prcm";
1003 reg = <0x01f01400 0x200>;
1004
1005 ar100: ar100_clk {
1006 compatible = "allwinner,sun6i-a31-ar100-clk";
1007 #clock-cells = <0>;
1008 clocks = <&osc32k>, <&osc24M>,
1009 <&ccu CLK_PLL_PERIPH>,
1010 <&ccu CLK_PLL_PERIPH>;
1011 clock-output-names = "ar100";
1012 };
1013
1014 ahb0: ahb0_clk {
1015 compatible = "fixed-factor-clock";
1016 #clock-cells = <0>;
1017 clock-div = <1>;
1018 clock-mult = <1>;
1019 clocks = <&ar100>;
1020 clock-output-names = "ahb0";
1021 };
1022
1023 apb0: apb0_clk {
1024 compatible = "allwinner,sun6i-a31-apb0-clk";
1025 #clock-cells = <0>;
1026 clocks = <&ahb0>;
1027 clock-output-names = "apb0";
1028 };
1029
1030 apb0_gates: apb0_gates_clk {
1031 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1032 #clock-cells = <1>;
1033 clocks = <&apb0>;
1034 clock-output-names = "apb0_pio", "apb0_ir",
1035 "apb0_timer", "apb0_p2wi",
1036 "apb0_uart", "apb0_1wire",
1037 "apb0_i2c";
1038 };
1039
1040 ir_clk: ir_clk {
1041 #clock-cells = <0>;
1042 compatible = "allwinner,sun4i-a10-mod0-clk";
1043 clocks = <&osc32k>, <&osc24M>;
1044 clock-output-names = "ir";
1045 };
1046
1047 apb0_rst: apb0_rst {
1048 compatible = "allwinner,sun6i-a31-clock-reset";
1049 #reset-cells = <1>;
1050 };
1051 };
1052
1053 cpucfg@01f01c00 {
1054 compatible = "allwinner,sun6i-a31-cpuconfig";
1055 reg = <0x01f01c00 0x300>;
1056 };
1057
1058 ir: ir@01f02000 {
1059 compatible = "allwinner,sun5i-a13-ir";
1060 clocks = <&apb0_gates 1>, <&ir_clk>;
1061 clock-names = "apb", "ir";
1062 resets = <&apb0_rst 1>;
1063 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1064 reg = <0x01f02000 0x40>;
1065 status = "disabled";
1066 };
1067
1068 r_pio: pinctrl@01f02c00 {
1069 compatible = "allwinner,sun6i-a31-r-pinctrl";
1070 reg = <0x01f02c00 0x400>;
1071 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1074 clock-names = "apb", "hosc", "losc";
1075 resets = <&apb0_rst 0>;
1076 gpio-controller;
1077 interrupt-controller;
1078 #interrupt-cells = <3>;
1079 #size-cells = <0>;
1080 #gpio-cells = <3>;
1081
1082 ir_pins_a: ir@0 {
1083 pins = "PL4";
1084 function = "s_ir";
1085 };
1086
1087 p2wi_pins: p2wi {
1088 pins = "PL0", "PL1";
1089 function = "s_p2wi";
1090 };
1091 };
1092
1093 p2wi: i2c@01f03400 {
1094 compatible = "allwinner,sun6i-a31-p2wi";
1095 reg = <0x01f03400 0x400>;
1096 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&apb0_gates 3>;
1098 clock-frequency = <100000>;
1099 resets = <&apb0_rst 3>;
1100 pinctrl-names = "default";
1101 pinctrl-0 = <&p2wi_pins>;
1102 status = "disabled";
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105 };
1106 };
1107 };
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