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Merge remote-tracking branch 'spi/topic/core' into spi-next
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sun6i-a31.dtsi
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50 /include/ "skeleton.dtsi"
51
52 / {
53 interrupt-parent = <&gic>;
54
55 aliases {
56 ethernet0 = &gmac;
57 };
58
59 chosen {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 ranges;
63
64 framebuffer@0 {
65 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&pll6 0>;
68 status = "disabled";
69 };
70 };
71
72 cpus {
73 enable-method = "allwinner,sun6i-a31";
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 cpu@0 {
78 compatible = "arm,cortex-a7";
79 device_type = "cpu";
80 reg = <0>;
81 };
82
83 cpu@1 {
84 compatible = "arm,cortex-a7";
85 device_type = "cpu";
86 reg = <1>;
87 };
88
89 cpu@2 {
90 compatible = "arm,cortex-a7";
91 device_type = "cpu";
92 reg = <2>;
93 };
94
95 cpu@3 {
96 compatible = "arm,cortex-a7";
97 device_type = "cpu";
98 reg = <3>;
99 };
100 };
101
102 memory {
103 reg = <0x40000000 0x80000000>;
104 };
105
106 pmu {
107 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
108 interrupts = <0 120 4>,
109 <0 121 4>,
110 <0 122 4>,
111 <0 123 4>;
112 };
113
114 clocks {
115 #address-cells = <1>;
116 #size-cells = <1>;
117 ranges;
118
119 osc24M: osc24M {
120 #clock-cells = <0>;
121 compatible = "fixed-clock";
122 clock-frequency = <24000000>;
123 };
124
125 osc32k: clk@0 {
126 #clock-cells = <0>;
127 compatible = "fixed-clock";
128 clock-frequency = <32768>;
129 clock-output-names = "osc32k";
130 };
131
132 pll1: clk@01c20000 {
133 #clock-cells = <0>;
134 compatible = "allwinner,sun6i-a31-pll1-clk";
135 reg = <0x01c20000 0x4>;
136 clocks = <&osc24M>;
137 clock-output-names = "pll1";
138 };
139
140 pll6: clk@01c20028 {
141 #clock-cells = <1>;
142 compatible = "allwinner,sun6i-a31-pll6-clk";
143 reg = <0x01c20028 0x4>;
144 clocks = <&osc24M>;
145 clock-output-names = "pll6", "pll6x2";
146 };
147
148 cpu: cpu@01c20050 {
149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-a10-cpu-clk";
151 reg = <0x01c20050 0x4>;
152
153 /*
154 * PLL1 is listed twice here.
155 * While it looks suspicious, it's actually documented
156 * that way both in the datasheet and in the code from
157 * Allwinner.
158 */
159 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
160 clock-output-names = "cpu";
161 };
162
163 axi: axi@01c20050 {
164 #clock-cells = <0>;
165 compatible = "allwinner,sun4i-a10-axi-clk";
166 reg = <0x01c20050 0x4>;
167 clocks = <&cpu>;
168 clock-output-names = "axi";
169 };
170
171 ahb1_mux: ahb1_mux@01c20054 {
172 #clock-cells = <0>;
173 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
174 reg = <0x01c20054 0x4>;
175 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
176 clock-output-names = "ahb1_mux";
177 };
178
179 ahb1: ahb1@01c20054 {
180 #clock-cells = <0>;
181 compatible = "allwinner,sun4i-a10-ahb-clk";
182 reg = <0x01c20054 0x4>;
183 clocks = <&ahb1_mux>;
184 clock-output-names = "ahb1";
185 };
186
187 ahb1_gates: clk@01c20060 {
188 #clock-cells = <1>;
189 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
190 reg = <0x01c20060 0x8>;
191 clocks = <&ahb1>;
192 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
193 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
194 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
195 "ahb1_nand0", "ahb1_sdram",
196 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
197 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
198 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
199 "ahb1_ehci1", "ahb1_ohci0",
200 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
201 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
202 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
203 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
204 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
205 "ahb1_drc0", "ahb1_drc1";
206 };
207
208 apb1: apb1@01c20054 {
209 #clock-cells = <0>;
210 compatible = "allwinner,sun4i-a10-apb0-clk";
211 reg = <0x01c20054 0x4>;
212 clocks = <&ahb1>;
213 clock-output-names = "apb1";
214 };
215
216 apb1_gates: clk@01c20068 {
217 #clock-cells = <1>;
218 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
219 reg = <0x01c20068 0x4>;
220 clocks = <&apb1>;
221 clock-output-names = "apb1_codec", "apb1_digital_mic",
222 "apb1_pio", "apb1_daudio0",
223 "apb1_daudio1";
224 };
225
226 apb2: clk@01c20058 {
227 #clock-cells = <0>;
228 compatible = "allwinner,sun4i-a10-apb1-clk";
229 reg = <0x01c20058 0x4>;
230 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
231 clock-output-names = "apb2";
232 };
233
234 apb2_gates: clk@01c2006c {
235 #clock-cells = <1>;
236 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
237 reg = <0x01c2006c 0x4>;
238 clocks = <&apb2>;
239 clock-output-names = "apb2_i2c0", "apb2_i2c1",
240 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
241 "apb2_uart1", "apb2_uart2", "apb2_uart3",
242 "apb2_uart4", "apb2_uart5";
243 };
244
245 mmc0_clk: clk@01c20088 {
246 #clock-cells = <0>;
247 compatible = "allwinner,sun4i-a10-mod0-clk";
248 reg = <0x01c20088 0x4>;
249 clocks = <&osc24M>, <&pll6 0>;
250 clock-output-names = "mmc0";
251 };
252
253 mmc1_clk: clk@01c2008c {
254 #clock-cells = <0>;
255 compatible = "allwinner,sun4i-a10-mod0-clk";
256 reg = <0x01c2008c 0x4>;
257 clocks = <&osc24M>, <&pll6 0>;
258 clock-output-names = "mmc1";
259 };
260
261 mmc2_clk: clk@01c20090 {
262 #clock-cells = <0>;
263 compatible = "allwinner,sun4i-a10-mod0-clk";
264 reg = <0x01c20090 0x4>;
265 clocks = <&osc24M>, <&pll6 0>;
266 clock-output-names = "mmc2";
267 };
268
269 mmc3_clk: clk@01c20094 {
270 #clock-cells = <0>;
271 compatible = "allwinner,sun4i-a10-mod0-clk";
272 reg = <0x01c20094 0x4>;
273 clocks = <&osc24M>, <&pll6 0>;
274 clock-output-names = "mmc3";
275 };
276
277 spi0_clk: clk@01c200a0 {
278 #clock-cells = <0>;
279 compatible = "allwinner,sun4i-a10-mod0-clk";
280 reg = <0x01c200a0 0x4>;
281 clocks = <&osc24M>, <&pll6 0>;
282 clock-output-names = "spi0";
283 };
284
285 spi1_clk: clk@01c200a4 {
286 #clock-cells = <0>;
287 compatible = "allwinner,sun4i-a10-mod0-clk";
288 reg = <0x01c200a4 0x4>;
289 clocks = <&osc24M>, <&pll6 0>;
290 clock-output-names = "spi1";
291 };
292
293 spi2_clk: clk@01c200a8 {
294 #clock-cells = <0>;
295 compatible = "allwinner,sun4i-a10-mod0-clk";
296 reg = <0x01c200a8 0x4>;
297 clocks = <&osc24M>, <&pll6 0>;
298 clock-output-names = "spi2";
299 };
300
301 spi3_clk: clk@01c200ac {
302 #clock-cells = <0>;
303 compatible = "allwinner,sun4i-a10-mod0-clk";
304 reg = <0x01c200ac 0x4>;
305 clocks = <&osc24M>, <&pll6 0>;
306 clock-output-names = "spi3";
307 };
308
309 usb_clk: clk@01c200cc {
310 #clock-cells = <1>;
311 #reset-cells = <1>;
312 compatible = "allwinner,sun6i-a31-usb-clk";
313 reg = <0x01c200cc 0x4>;
314 clocks = <&osc24M>;
315 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
316 "usb_ohci0", "usb_ohci1",
317 "usb_ohci2";
318 };
319
320 /*
321 * The following two are dummy clocks, placeholders used in the gmac_tx
322 * clock. The gmac driver will choose one parent depending on the PHY
323 * interface mode, using clk_set_rate auto-reparenting.
324 * The actual TX clock rate is not controlled by the gmac_tx clock.
325 */
326 mii_phy_tx_clk: clk@1 {
327 #clock-cells = <0>;
328 compatible = "fixed-clock";
329 clock-frequency = <25000000>;
330 clock-output-names = "mii_phy_tx";
331 };
332
333 gmac_int_tx_clk: clk@2 {
334 #clock-cells = <0>;
335 compatible = "fixed-clock";
336 clock-frequency = <125000000>;
337 clock-output-names = "gmac_int_tx";
338 };
339
340 gmac_tx_clk: clk@01c200d0 {
341 #clock-cells = <0>;
342 compatible = "allwinner,sun7i-a20-gmac-clk";
343 reg = <0x01c200d0 0x4>;
344 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
345 clock-output-names = "gmac_tx";
346 };
347 };
348
349 soc@01c00000 {
350 compatible = "simple-bus";
351 #address-cells = <1>;
352 #size-cells = <1>;
353 ranges;
354
355 dma: dma-controller@01c02000 {
356 compatible = "allwinner,sun6i-a31-dma";
357 reg = <0x01c02000 0x1000>;
358 interrupts = <0 50 4>;
359 clocks = <&ahb1_gates 6>;
360 resets = <&ahb1_rst 6>;
361 #dma-cells = <1>;
362
363 /* DMA controller requires AHB1 clocked from PLL6 */
364 assigned-clocks = <&ahb1_mux>;
365 assigned-clock-parents = <&pll6 0>;
366 };
367
368 mmc0: mmc@01c0f000 {
369 compatible = "allwinner,sun5i-a13-mmc";
370 reg = <0x01c0f000 0x1000>;
371 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
372 clock-names = "ahb", "mmc";
373 resets = <&ahb1_rst 8>;
374 reset-names = "ahb";
375 interrupts = <0 60 4>;
376 status = "disabled";
377 };
378
379 mmc1: mmc@01c10000 {
380 compatible = "allwinner,sun5i-a13-mmc";
381 reg = <0x01c10000 0x1000>;
382 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
383 clock-names = "ahb", "mmc";
384 resets = <&ahb1_rst 9>;
385 reset-names = "ahb";
386 interrupts = <0 61 4>;
387 status = "disabled";
388 };
389
390 mmc2: mmc@01c11000 {
391 compatible = "allwinner,sun5i-a13-mmc";
392 reg = <0x01c11000 0x1000>;
393 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
394 clock-names = "ahb", "mmc";
395 resets = <&ahb1_rst 10>;
396 reset-names = "ahb";
397 interrupts = <0 62 4>;
398 status = "disabled";
399 };
400
401 mmc3: mmc@01c12000 {
402 compatible = "allwinner,sun5i-a13-mmc";
403 reg = <0x01c12000 0x1000>;
404 clocks = <&ahb1_gates 11>, <&mmc3_clk>;
405 clock-names = "ahb", "mmc";
406 resets = <&ahb1_rst 11>;
407 reset-names = "ahb";
408 interrupts = <0 63 4>;
409 status = "disabled";
410 };
411
412 usbphy: phy@01c19400 {
413 compatible = "allwinner,sun6i-a31-usb-phy";
414 reg = <0x01c19400 0x10>,
415 <0x01c1a800 0x4>,
416 <0x01c1b800 0x4>;
417 reg-names = "phy_ctrl",
418 "pmu1",
419 "pmu2";
420 clocks = <&usb_clk 8>,
421 <&usb_clk 9>,
422 <&usb_clk 10>;
423 clock-names = "usb0_phy",
424 "usb1_phy",
425 "usb2_phy";
426 resets = <&usb_clk 0>,
427 <&usb_clk 1>,
428 <&usb_clk 2>;
429 reset-names = "usb0_reset",
430 "usb1_reset",
431 "usb2_reset";
432 status = "disabled";
433 #phy-cells = <1>;
434 };
435
436 ehci0: usb@01c1a000 {
437 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
438 reg = <0x01c1a000 0x100>;
439 interrupts = <0 72 4>;
440 clocks = <&ahb1_gates 26>;
441 resets = <&ahb1_rst 26>;
442 phys = <&usbphy 1>;
443 phy-names = "usb";
444 status = "disabled";
445 };
446
447 ohci0: usb@01c1a400 {
448 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
449 reg = <0x01c1a400 0x100>;
450 interrupts = <0 73 4>;
451 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
452 resets = <&ahb1_rst 29>;
453 phys = <&usbphy 1>;
454 phy-names = "usb";
455 status = "disabled";
456 };
457
458 ehci1: usb@01c1b000 {
459 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
460 reg = <0x01c1b000 0x100>;
461 interrupts = <0 74 4>;
462 clocks = <&ahb1_gates 27>;
463 resets = <&ahb1_rst 27>;
464 phys = <&usbphy 2>;
465 phy-names = "usb";
466 status = "disabled";
467 };
468
469 ohci1: usb@01c1b400 {
470 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
471 reg = <0x01c1b400 0x100>;
472 interrupts = <0 75 4>;
473 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
474 resets = <&ahb1_rst 30>;
475 phys = <&usbphy 2>;
476 phy-names = "usb";
477 status = "disabled";
478 };
479
480 ohci2: usb@01c1c400 {
481 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
482 reg = <0x01c1c400 0x100>;
483 interrupts = <0 77 4>;
484 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
485 resets = <&ahb1_rst 31>;
486 status = "disabled";
487 };
488
489 pio: pinctrl@01c20800 {
490 compatible = "allwinner,sun6i-a31-pinctrl";
491 reg = <0x01c20800 0x400>;
492 interrupts = <0 11 4>,
493 <0 15 4>,
494 <0 16 4>,
495 <0 17 4>;
496 clocks = <&apb1_gates 5>;
497 gpio-controller;
498 interrupt-controller;
499 #interrupt-cells = <2>;
500 #size-cells = <0>;
501 #gpio-cells = <3>;
502
503 uart0_pins_a: uart0@0 {
504 allwinner,pins = "PH20", "PH21";
505 allwinner,function = "uart0";
506 allwinner,drive = <0>;
507 allwinner,pull = <0>;
508 };
509
510 i2c0_pins_a: i2c0@0 {
511 allwinner,pins = "PH14", "PH15";
512 allwinner,function = "i2c0";
513 allwinner,drive = <0>;
514 allwinner,pull = <0>;
515 };
516
517 i2c1_pins_a: i2c1@0 {
518 allwinner,pins = "PH16", "PH17";
519 allwinner,function = "i2c1";
520 allwinner,drive = <0>;
521 allwinner,pull = <0>;
522 };
523
524 i2c2_pins_a: i2c2@0 {
525 allwinner,pins = "PH18", "PH19";
526 allwinner,function = "i2c2";
527 allwinner,drive = <0>;
528 allwinner,pull = <0>;
529 };
530
531 mmc0_pins_a: mmc0@0 {
532 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
533 allwinner,function = "mmc0";
534 allwinner,drive = <2>;
535 allwinner,pull = <0>;
536 };
537
538 gmac_pins_mii_a: gmac_mii@0 {
539 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
540 "PA8", "PA9", "PA11",
541 "PA12", "PA13", "PA14", "PA19",
542 "PA20", "PA21", "PA22", "PA23",
543 "PA24", "PA26", "PA27";
544 allwinner,function = "gmac";
545 allwinner,drive = <0>;
546 allwinner,pull = <0>;
547 };
548
549 gmac_pins_gmii_a: gmac_gmii@0 {
550 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
551 "PA4", "PA5", "PA6", "PA7",
552 "PA8", "PA9", "PA10", "PA11",
553 "PA12", "PA13", "PA14", "PA15",
554 "PA16", "PA17", "PA18", "PA19",
555 "PA20", "PA21", "PA22", "PA23",
556 "PA24", "PA25", "PA26", "PA27";
557 allwinner,function = "gmac";
558 /*
559 * data lines in GMII mode run at 125MHz and
560 * might need a higher signal drive strength
561 */
562 allwinner,drive = <2>;
563 allwinner,pull = <0>;
564 };
565
566 gmac_pins_rgmii_a: gmac_rgmii@0 {
567 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
568 "PA9", "PA10", "PA11",
569 "PA12", "PA13", "PA14", "PA19",
570 "PA20", "PA25", "PA26", "PA27";
571 allwinner,function = "gmac";
572 /*
573 * data lines in RGMII mode use DDR mode
574 * and need a higher signal drive strength
575 */
576 allwinner,drive = <3>;
577 allwinner,pull = <0>;
578 };
579 };
580
581 ahb1_rst: reset@01c202c0 {
582 #reset-cells = <1>;
583 compatible = "allwinner,sun6i-a31-ahb1-reset";
584 reg = <0x01c202c0 0xc>;
585 };
586
587 apb1_rst: reset@01c202d0 {
588 #reset-cells = <1>;
589 compatible = "allwinner,sun6i-a31-clock-reset";
590 reg = <0x01c202d0 0x4>;
591 };
592
593 apb2_rst: reset@01c202d8 {
594 #reset-cells = <1>;
595 compatible = "allwinner,sun6i-a31-clock-reset";
596 reg = <0x01c202d8 0x4>;
597 };
598
599 timer@01c20c00 {
600 compatible = "allwinner,sun4i-a10-timer";
601 reg = <0x01c20c00 0xa0>;
602 interrupts = <0 18 4>,
603 <0 19 4>,
604 <0 20 4>,
605 <0 21 4>,
606 <0 22 4>;
607 clocks = <&osc24M>;
608 };
609
610 wdt1: watchdog@01c20ca0 {
611 compatible = "allwinner,sun6i-a31-wdt";
612 reg = <0x01c20ca0 0x20>;
613 };
614
615 uart0: serial@01c28000 {
616 compatible = "snps,dw-apb-uart";
617 reg = <0x01c28000 0x400>;
618 interrupts = <0 0 4>;
619 reg-shift = <2>;
620 reg-io-width = <4>;
621 clocks = <&apb2_gates 16>;
622 resets = <&apb2_rst 16>;
623 dmas = <&dma 6>, <&dma 6>;
624 dma-names = "rx", "tx";
625 status = "disabled";
626 };
627
628 uart1: serial@01c28400 {
629 compatible = "snps,dw-apb-uart";
630 reg = <0x01c28400 0x400>;
631 interrupts = <0 1 4>;
632 reg-shift = <2>;
633 reg-io-width = <4>;
634 clocks = <&apb2_gates 17>;
635 resets = <&apb2_rst 17>;
636 dmas = <&dma 7>, <&dma 7>;
637 dma-names = "rx", "tx";
638 status = "disabled";
639 };
640
641 uart2: serial@01c28800 {
642 compatible = "snps,dw-apb-uart";
643 reg = <0x01c28800 0x400>;
644 interrupts = <0 2 4>;
645 reg-shift = <2>;
646 reg-io-width = <4>;
647 clocks = <&apb2_gates 18>;
648 resets = <&apb2_rst 18>;
649 dmas = <&dma 8>, <&dma 8>;
650 dma-names = "rx", "tx";
651 status = "disabled";
652 };
653
654 uart3: serial@01c28c00 {
655 compatible = "snps,dw-apb-uart";
656 reg = <0x01c28c00 0x400>;
657 interrupts = <0 3 4>;
658 reg-shift = <2>;
659 reg-io-width = <4>;
660 clocks = <&apb2_gates 19>;
661 resets = <&apb2_rst 19>;
662 dmas = <&dma 9>, <&dma 9>;
663 dma-names = "rx", "tx";
664 status = "disabled";
665 };
666
667 uart4: serial@01c29000 {
668 compatible = "snps,dw-apb-uart";
669 reg = <0x01c29000 0x400>;
670 interrupts = <0 4 4>;
671 reg-shift = <2>;
672 reg-io-width = <4>;
673 clocks = <&apb2_gates 20>;
674 resets = <&apb2_rst 20>;
675 dmas = <&dma 10>, <&dma 10>;
676 dma-names = "rx", "tx";
677 status = "disabled";
678 };
679
680 uart5: serial@01c29400 {
681 compatible = "snps,dw-apb-uart";
682 reg = <0x01c29400 0x400>;
683 interrupts = <0 5 4>;
684 reg-shift = <2>;
685 reg-io-width = <4>;
686 clocks = <&apb2_gates 21>;
687 resets = <&apb2_rst 21>;
688 dmas = <&dma 22>, <&dma 22>;
689 dma-names = "rx", "tx";
690 status = "disabled";
691 };
692
693 i2c0: i2c@01c2ac00 {
694 compatible = "allwinner,sun6i-a31-i2c";
695 reg = <0x01c2ac00 0x400>;
696 interrupts = <0 6 4>;
697 clocks = <&apb2_gates 0>;
698 resets = <&apb2_rst 0>;
699 status = "disabled";
700 #address-cells = <1>;
701 #size-cells = <0>;
702 };
703
704 i2c1: i2c@01c2b000 {
705 compatible = "allwinner,sun6i-a31-i2c";
706 reg = <0x01c2b000 0x400>;
707 interrupts = <0 7 4>;
708 clocks = <&apb2_gates 1>;
709 resets = <&apb2_rst 1>;
710 status = "disabled";
711 #address-cells = <1>;
712 #size-cells = <0>;
713 };
714
715 i2c2: i2c@01c2b400 {
716 compatible = "allwinner,sun6i-a31-i2c";
717 reg = <0x01c2b400 0x400>;
718 interrupts = <0 8 4>;
719 clocks = <&apb2_gates 2>;
720 resets = <&apb2_rst 2>;
721 status = "disabled";
722 #address-cells = <1>;
723 #size-cells = <0>;
724 };
725
726 i2c3: i2c@01c2b800 {
727 compatible = "allwinner,sun6i-a31-i2c";
728 reg = <0x01c2b800 0x400>;
729 interrupts = <0 9 4>;
730 clocks = <&apb2_gates 3>;
731 resets = <&apb2_rst 3>;
732 status = "disabled";
733 #address-cells = <1>;
734 #size-cells = <0>;
735 };
736
737 gmac: ethernet@01c30000 {
738 compatible = "allwinner,sun7i-a20-gmac";
739 reg = <0x01c30000 0x1054>;
740 interrupts = <0 82 4>;
741 interrupt-names = "macirq";
742 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
743 clock-names = "stmmaceth", "allwinner_gmac_tx";
744 resets = <&ahb1_rst 17>;
745 reset-names = "stmmaceth";
746 snps,pbl = <2>;
747 snps,fixed-burst;
748 snps,force_sf_dma_mode;
749 status = "disabled";
750 #address-cells = <1>;
751 #size-cells = <0>;
752 };
753
754 timer@01c60000 {
755 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
756 reg = <0x01c60000 0x1000>;
757 interrupts = <0 51 4>,
758 <0 52 4>,
759 <0 53 4>,
760 <0 54 4>;
761 clocks = <&ahb1_gates 19>;
762 resets = <&ahb1_rst 19>;
763 };
764
765 spi0: spi@01c68000 {
766 compatible = "allwinner,sun6i-a31-spi";
767 reg = <0x01c68000 0x1000>;
768 interrupts = <0 65 4>;
769 clocks = <&ahb1_gates 20>, <&spi0_clk>;
770 clock-names = "ahb", "mod";
771 dmas = <&dma 23>, <&dma 23>;
772 dma-names = "rx", "tx";
773 resets = <&ahb1_rst 20>;
774 status = "disabled";
775 };
776
777 spi1: spi@01c69000 {
778 compatible = "allwinner,sun6i-a31-spi";
779 reg = <0x01c69000 0x1000>;
780 interrupts = <0 66 4>;
781 clocks = <&ahb1_gates 21>, <&spi1_clk>;
782 clock-names = "ahb", "mod";
783 dmas = <&dma 24>, <&dma 24>;
784 dma-names = "rx", "tx";
785 resets = <&ahb1_rst 21>;
786 status = "disabled";
787 };
788
789 spi2: spi@01c6a000 {
790 compatible = "allwinner,sun6i-a31-spi";
791 reg = <0x01c6a000 0x1000>;
792 interrupts = <0 67 4>;
793 clocks = <&ahb1_gates 22>, <&spi2_clk>;
794 clock-names = "ahb", "mod";
795 dmas = <&dma 25>, <&dma 25>;
796 dma-names = "rx", "tx";
797 resets = <&ahb1_rst 22>;
798 status = "disabled";
799 };
800
801 spi3: spi@01c6b000 {
802 compatible = "allwinner,sun6i-a31-spi";
803 reg = <0x01c6b000 0x1000>;
804 interrupts = <0 68 4>;
805 clocks = <&ahb1_gates 23>, <&spi3_clk>;
806 clock-names = "ahb", "mod";
807 dmas = <&dma 26>, <&dma 26>;
808 dma-names = "rx", "tx";
809 resets = <&ahb1_rst 23>;
810 status = "disabled";
811 };
812
813 gic: interrupt-controller@01c81000 {
814 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
815 reg = <0x01c81000 0x1000>,
816 <0x01c82000 0x1000>,
817 <0x01c84000 0x2000>,
818 <0x01c86000 0x2000>;
819 interrupt-controller;
820 #interrupt-cells = <3>;
821 interrupts = <1 9 0xf04>;
822 };
823
824 rtc: rtc@01f00000 {
825 compatible = "allwinner,sun6i-a31-rtc";
826 reg = <0x01f00000 0x54>;
827 interrupts = <0 40 4>, <0 41 4>;
828 };
829
830 nmi_intc: interrupt-controller@01f00c0c {
831 compatible = "allwinner,sun6i-a31-sc-nmi";
832 interrupt-controller;
833 #interrupt-cells = <2>;
834 reg = <0x01f00c0c 0x38>;
835 interrupts = <0 32 4>;
836 };
837
838 prcm@01f01400 {
839 compatible = "allwinner,sun6i-a31-prcm";
840 reg = <0x01f01400 0x200>;
841
842 ar100: ar100_clk {
843 compatible = "allwinner,sun6i-a31-ar100-clk";
844 #clock-cells = <0>;
845 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
846 clock-output-names = "ar100";
847 };
848
849 ahb0: ahb0_clk {
850 compatible = "fixed-factor-clock";
851 #clock-cells = <0>;
852 clock-div = <1>;
853 clock-mult = <1>;
854 clocks = <&ar100>;
855 clock-output-names = "ahb0";
856 };
857
858 apb0: apb0_clk {
859 compatible = "allwinner,sun6i-a31-apb0-clk";
860 #clock-cells = <0>;
861 clocks = <&ahb0>;
862 clock-output-names = "apb0";
863 };
864
865 apb0_gates: apb0_gates_clk {
866 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
867 #clock-cells = <1>;
868 clocks = <&apb0>;
869 clock-output-names = "apb0_pio", "apb0_ir",
870 "apb0_timer", "apb0_p2wi",
871 "apb0_uart", "apb0_1wire",
872 "apb0_i2c";
873 };
874
875 apb0_rst: apb0_rst {
876 compatible = "allwinner,sun6i-a31-clock-reset";
877 #reset-cells = <1>;
878 };
879 };
880
881 cpucfg@01f01c00 {
882 compatible = "allwinner,sun6i-a31-cpuconfig";
883 reg = <0x01f01c00 0x300>;
884 };
885
886 r_pio: pinctrl@01f02c00 {
887 compatible = "allwinner,sun6i-a31-r-pinctrl";
888 reg = <0x01f02c00 0x400>;
889 interrupts = <0 45 4>,
890 <0 46 4>;
891 clocks = <&apb0_gates 0>;
892 resets = <&apb0_rst 0>;
893 gpio-controller;
894 interrupt-controller;
895 #interrupt-cells = <2>;
896 #size-cells = <0>;
897 #gpio-cells = <3>;
898 };
899 };
900 };
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