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Merge tag 'ceph-for-4.11-rc1' of git://github.com/ceph/ceph-client
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / sun7i-a20.dtsi
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include "skeleton.dtsi"
46
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49
50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
51 #include <dt-bindings/dma/sun4i-a10.h>
52 #include <dt-bindings/pinctrl/sun4i-a10.h>
53
54 / {
55 interrupt-parent = <&gic>;
56
57 aliases {
58 ethernet0 = &gmac;
59 };
60
61 chosen {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65
66 framebuffer@0 {
67 compatible = "allwinner,simple-framebuffer",
68 "simple-framebuffer";
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
71 <&ahb_gates 44>, <&de_be0_clk>,
72 <&tcon0_ch1_clk>, <&dram_gates 26>;
73 status = "disabled";
74 };
75
76 framebuffer@1 {
77 compatible = "allwinner,simple-framebuffer",
78 "simple-framebuffer";
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ahb_gates 36>, <&ahb_gates 44>,
81 <&de_be0_clk>, <&tcon0_ch0_clk>,
82 <&dram_gates 26>;
83 status = "disabled";
84 };
85
86 framebuffer@2 {
87 compatible = "allwinner,simple-framebuffer",
88 "simple-framebuffer";
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&ahb_gates 34>, <&ahb_gates 36>,
91 <&ahb_gates 44>,
92 <&de_be0_clk>, <&tcon0_ch1_clk>,
93 <&dram_gates 5>, <&dram_gates 26>;
94 status = "disabled";
95 };
96 };
97
98 cpus {
99 #address-cells = <1>;
100 #size-cells = <0>;
101
102 cpu0: cpu@0 {
103 compatible = "arm,cortex-a7";
104 device_type = "cpu";
105 reg = <0>;
106 clocks = <&cpu>;
107 clock-latency = <244144>; /* 8 32k periods */
108 operating-points = <
109 /* kHz uV */
110 960000 1400000
111 912000 1400000
112 864000 1300000
113 720000 1200000
114 528000 1100000
115 312000 1000000
116 144000 1000000
117 >;
118 #cooling-cells = <2>;
119 cooling-min-level = <0>;
120 cooling-max-level = <6>;
121 };
122
123 cpu@1 {
124 compatible = "arm,cortex-a7";
125 device_type = "cpu";
126 reg = <1>;
127 };
128 };
129
130 thermal-zones {
131 cpu_thermal {
132 /* milliseconds */
133 polling-delay-passive = <250>;
134 polling-delay = <1000>;
135 thermal-sensors = <&rtp>;
136
137 cooling-maps {
138 map0 {
139 trip = <&cpu_alert0>;
140 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
141 };
142 };
143
144 trips {
145 cpu_alert0: cpu_alert0 {
146 /* milliCelsius */
147 temperature = <75000>;
148 hysteresis = <2000>;
149 type = "passive";
150 };
151
152 cpu_crit: cpu_crit {
153 /* milliCelsius */
154 temperature = <100000>;
155 hysteresis = <2000>;
156 type = "critical";
157 };
158 };
159 };
160 };
161
162 memory {
163 reg = <0x40000000 0x80000000>;
164 };
165
166 timer {
167 compatible = "arm,armv7-timer";
168 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
170 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
171 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
172 };
173
174 pmu {
175 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
176 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
178 };
179
180 clocks {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges;
184
185 osc24M: clk@01c20050 {
186 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-a10-osc-clk";
188 reg = <0x01c20050 0x4>;
189 clock-frequency = <24000000>;
190 clock-output-names = "osc24M";
191 };
192
193 osc3M: osc3M_clk {
194 #clock-cells = <0>;
195 compatible = "fixed-factor-clock";
196 clock-div = <8>;
197 clock-mult = <1>;
198 clocks = <&osc24M>;
199 clock-output-names = "osc3M";
200 };
201
202 osc32k: clk@0 {
203 #clock-cells = <0>;
204 compatible = "fixed-clock";
205 clock-frequency = <32768>;
206 clock-output-names = "osc32k";
207 };
208
209 pll1: clk@01c20000 {
210 #clock-cells = <0>;
211 compatible = "allwinner,sun4i-a10-pll1-clk";
212 reg = <0x01c20000 0x4>;
213 clocks = <&osc24M>;
214 clock-output-names = "pll1";
215 };
216
217 pll2: clk@01c20008 {
218 #clock-cells = <1>;
219 compatible = "allwinner,sun4i-a10-pll2-clk";
220 reg = <0x01c20008 0x8>;
221 clocks = <&osc24M>;
222 clock-output-names = "pll2-1x", "pll2-2x",
223 "pll2-4x", "pll2-8x";
224 };
225
226 pll3: clk@01c20010 {
227 #clock-cells = <0>;
228 compatible = "allwinner,sun4i-a10-pll3-clk";
229 reg = <0x01c20010 0x4>;
230 clocks = <&osc3M>;
231 clock-output-names = "pll3";
232 };
233
234 pll3x2: pll3x2_clk {
235 #clock-cells = <0>;
236 compatible = "fixed-factor-clock";
237 clocks = <&pll3>;
238 clock-div = <1>;
239 clock-mult = <2>;
240 clock-output-names = "pll3-2x";
241 };
242
243 pll4: clk@01c20018 {
244 #clock-cells = <0>;
245 compatible = "allwinner,sun7i-a20-pll4-clk";
246 reg = <0x01c20018 0x4>;
247 clocks = <&osc24M>;
248 clock-output-names = "pll4";
249 };
250
251 pll5: clk@01c20020 {
252 #clock-cells = <1>;
253 compatible = "allwinner,sun4i-a10-pll5-clk";
254 reg = <0x01c20020 0x4>;
255 clocks = <&osc24M>;
256 clock-output-names = "pll5_ddr", "pll5_other";
257 };
258
259 pll6: clk@01c20028 {
260 #clock-cells = <1>;
261 compatible = "allwinner,sun4i-a10-pll6-clk";
262 reg = <0x01c20028 0x4>;
263 clocks = <&osc24M>;
264 clock-output-names = "pll6_sata", "pll6_other", "pll6",
265 "pll6_div_4";
266 };
267
268 pll7: clk@01c20030 {
269 #clock-cells = <0>;
270 compatible = "allwinner,sun4i-a10-pll3-clk";
271 reg = <0x01c20030 0x4>;
272 clocks = <&osc3M>;
273 clock-output-names = "pll7";
274 };
275
276 pll7x2: pll7x2_clk {
277 #clock-cells = <0>;
278 compatible = "fixed-factor-clock";
279 clocks = <&pll7>;
280 clock-div = <1>;
281 clock-mult = <2>;
282 clock-output-names = "pll7-2x";
283 };
284
285 pll8: clk@01c20040 {
286 #clock-cells = <0>;
287 compatible = "allwinner,sun7i-a20-pll4-clk";
288 reg = <0x01c20040 0x4>;
289 clocks = <&osc24M>;
290 clock-output-names = "pll8";
291 };
292
293 cpu: cpu@01c20054 {
294 #clock-cells = <0>;
295 compatible = "allwinner,sun4i-a10-cpu-clk";
296 reg = <0x01c20054 0x4>;
297 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
298 clock-output-names = "cpu";
299 };
300
301 axi: axi@01c20054 {
302 #clock-cells = <0>;
303 compatible = "allwinner,sun4i-a10-axi-clk";
304 reg = <0x01c20054 0x4>;
305 clocks = <&cpu>;
306 clock-output-names = "axi";
307 };
308
309 ahb: ahb@01c20054 {
310 #clock-cells = <0>;
311 compatible = "allwinner,sun5i-a13-ahb-clk";
312 reg = <0x01c20054 0x4>;
313 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
314 clock-output-names = "ahb";
315 /*
316 * Use PLL6 as parent, instead of CPU/AXI
317 * which has rate changes due to cpufreq
318 */
319 assigned-clocks = <&ahb>;
320 assigned-clock-parents = <&pll6 3>;
321 };
322
323 ahb_gates: clk@01c20060 {
324 #clock-cells = <1>;
325 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
326 reg = <0x01c20060 0x8>;
327 clocks = <&ahb>;
328 clock-indices = <0>, <1>,
329 <2>, <3>, <4>,
330 <5>, <6>, <7>, <8>,
331 <9>, <10>, <11>, <12>,
332 <13>, <14>, <16>,
333 <17>, <18>, <20>, <21>,
334 <22>, <23>, <25>,
335 <28>, <32>, <33>, <34>,
336 <35>, <36>, <37>, <40>,
337 <41>, <42>, <43>,
338 <44>, <45>, <46>,
339 <47>, <49>, <50>,
340 <52>;
341 clock-output-names = "ahb_usb0", "ahb_ehci0",
342 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
343 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
344 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
345 "ahb_nand", "ahb_sdram", "ahb_ace",
346 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
347 "ahb_spi2", "ahb_spi3", "ahb_sata",
348 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
349 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
350 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
351 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
352 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
353 "ahb_mali";
354 };
355
356 apb0: apb0@01c20054 {
357 #clock-cells = <0>;
358 compatible = "allwinner,sun4i-a10-apb0-clk";
359 reg = <0x01c20054 0x4>;
360 clocks = <&ahb>;
361 clock-output-names = "apb0";
362 };
363
364 apb0_gates: clk@01c20068 {
365 #clock-cells = <1>;
366 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
367 reg = <0x01c20068 0x4>;
368 clocks = <&apb0>;
369 clock-indices = <0>, <1>,
370 <2>, <3>, <4>,
371 <5>, <6>, <7>,
372 <8>, <10>;
373 clock-output-names = "apb0_codec", "apb0_spdif",
374 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
375 "apb0_pio", "apb0_ir0", "apb0_ir1",
376 "apb0_i2s2", "apb0_keypad";
377 };
378
379 apb1: clk@01c20058 {
380 #clock-cells = <0>;
381 compatible = "allwinner,sun4i-a10-apb1-clk";
382 reg = <0x01c20058 0x4>;
383 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
384 clock-output-names = "apb1";
385 };
386
387 apb1_gates: clk@01c2006c {
388 #clock-cells = <1>;
389 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
390 reg = <0x01c2006c 0x4>;
391 clocks = <&apb1>;
392 clock-indices = <0>, <1>,
393 <2>, <3>, <4>,
394 <5>, <6>, <7>,
395 <15>, <16>, <17>,
396 <18>, <19>, <20>,
397 <21>, <22>, <23>;
398 clock-output-names = "apb1_i2c0", "apb1_i2c1",
399 "apb1_i2c2", "apb1_i2c3", "apb1_can",
400 "apb1_scr", "apb1_ps20", "apb1_ps21",
401 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
402 "apb1_uart2", "apb1_uart3", "apb1_uart4",
403 "apb1_uart5", "apb1_uart6", "apb1_uart7";
404 };
405
406 nand_clk: clk@01c20080 {
407 #clock-cells = <0>;
408 compatible = "allwinner,sun4i-a10-mod0-clk";
409 reg = <0x01c20080 0x4>;
410 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
411 clock-output-names = "nand";
412 };
413
414 ms_clk: clk@01c20084 {
415 #clock-cells = <0>;
416 compatible = "allwinner,sun4i-a10-mod0-clk";
417 reg = <0x01c20084 0x4>;
418 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
419 clock-output-names = "ms";
420 };
421
422 mmc0_clk: clk@01c20088 {
423 #clock-cells = <1>;
424 compatible = "allwinner,sun4i-a10-mmc-clk";
425 reg = <0x01c20088 0x4>;
426 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
427 clock-output-names = "mmc0",
428 "mmc0_output",
429 "mmc0_sample";
430 };
431
432 mmc1_clk: clk@01c2008c {
433 #clock-cells = <1>;
434 compatible = "allwinner,sun4i-a10-mmc-clk";
435 reg = <0x01c2008c 0x4>;
436 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
437 clock-output-names = "mmc1",
438 "mmc1_output",
439 "mmc1_sample";
440 };
441
442 mmc2_clk: clk@01c20090 {
443 #clock-cells = <1>;
444 compatible = "allwinner,sun4i-a10-mmc-clk";
445 reg = <0x01c20090 0x4>;
446 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
447 clock-output-names = "mmc2",
448 "mmc2_output",
449 "mmc2_sample";
450 };
451
452 mmc3_clk: clk@01c20094 {
453 #clock-cells = <1>;
454 compatible = "allwinner,sun4i-a10-mmc-clk";
455 reg = <0x01c20094 0x4>;
456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
457 clock-output-names = "mmc3",
458 "mmc3_output",
459 "mmc3_sample";
460 };
461
462 ts_clk: clk@01c20098 {
463 #clock-cells = <0>;
464 compatible = "allwinner,sun4i-a10-mod0-clk";
465 reg = <0x01c20098 0x4>;
466 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
467 clock-output-names = "ts";
468 };
469
470 ss_clk: clk@01c2009c {
471 #clock-cells = <0>;
472 compatible = "allwinner,sun4i-a10-mod0-clk";
473 reg = <0x01c2009c 0x4>;
474 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
475 clock-output-names = "ss";
476 };
477
478 spi0_clk: clk@01c200a0 {
479 #clock-cells = <0>;
480 compatible = "allwinner,sun4i-a10-mod0-clk";
481 reg = <0x01c200a0 0x4>;
482 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
483 clock-output-names = "spi0";
484 };
485
486 spi1_clk: clk@01c200a4 {
487 #clock-cells = <0>;
488 compatible = "allwinner,sun4i-a10-mod0-clk";
489 reg = <0x01c200a4 0x4>;
490 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
491 clock-output-names = "spi1";
492 };
493
494 spi2_clk: clk@01c200a8 {
495 #clock-cells = <0>;
496 compatible = "allwinner,sun4i-a10-mod0-clk";
497 reg = <0x01c200a8 0x4>;
498 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
499 clock-output-names = "spi2";
500 };
501
502 pata_clk: clk@01c200ac {
503 #clock-cells = <0>;
504 compatible = "allwinner,sun4i-a10-mod0-clk";
505 reg = <0x01c200ac 0x4>;
506 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
507 clock-output-names = "pata";
508 };
509
510 ir0_clk: clk@01c200b0 {
511 #clock-cells = <0>;
512 compatible = "allwinner,sun4i-a10-mod0-clk";
513 reg = <0x01c200b0 0x4>;
514 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
515 clock-output-names = "ir0";
516 };
517
518 ir1_clk: clk@01c200b4 {
519 #clock-cells = <0>;
520 compatible = "allwinner,sun4i-a10-mod0-clk";
521 reg = <0x01c200b4 0x4>;
522 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
523 clock-output-names = "ir1";
524 };
525
526 i2s0_clk: clk@01c200b8 {
527 #clock-cells = <0>;
528 compatible = "allwinner,sun4i-a10-mod1-clk";
529 reg = <0x01c200b8 0x4>;
530 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
531 <&pll2 SUN4I_A10_PLL2_4X>,
532 <&pll2 SUN4I_A10_PLL2_2X>,
533 <&pll2 SUN4I_A10_PLL2_1X>;
534 clock-output-names = "i2s0";
535 };
536
537 ac97_clk: clk@01c200bc {
538 #clock-cells = <0>;
539 compatible = "allwinner,sun4i-a10-mod1-clk";
540 reg = <0x01c200bc 0x4>;
541 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
542 <&pll2 SUN4I_A10_PLL2_4X>,
543 <&pll2 SUN4I_A10_PLL2_2X>,
544 <&pll2 SUN4I_A10_PLL2_1X>;
545 clock-output-names = "ac97";
546 };
547
548 spdif_clk: clk@01c200c0 {
549 #clock-cells = <0>;
550 compatible = "allwinner,sun4i-a10-mod1-clk";
551 reg = <0x01c200c0 0x4>;
552 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
553 <&pll2 SUN4I_A10_PLL2_4X>,
554 <&pll2 SUN4I_A10_PLL2_2X>,
555 <&pll2 SUN4I_A10_PLL2_1X>;
556 clock-output-names = "spdif";
557 };
558
559 keypad_clk: clk@01c200c4 {
560 #clock-cells = <0>;
561 compatible = "allwinner,sun4i-a10-mod0-clk";
562 reg = <0x01c200c4 0x4>;
563 clocks = <&osc24M>;
564 clock-output-names = "keypad";
565 };
566
567 usb_clk: clk@01c200cc {
568 #clock-cells = <1>;
569 #reset-cells = <1>;
570 compatible = "allwinner,sun4i-a10-usb-clk";
571 reg = <0x01c200cc 0x4>;
572 clocks = <&pll6 1>;
573 clock-output-names = "usb_ohci0", "usb_ohci1",
574 "usb_phy";
575 };
576
577 spi3_clk: clk@01c200d4 {
578 #clock-cells = <0>;
579 compatible = "allwinner,sun4i-a10-mod0-clk";
580 reg = <0x01c200d4 0x4>;
581 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
582 clock-output-names = "spi3";
583 };
584
585 i2s1_clk: clk@01c200d8 {
586 #clock-cells = <0>;
587 compatible = "allwinner,sun4i-a10-mod1-clk";
588 reg = <0x01c200d8 0x4>;
589 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
590 <&pll2 SUN4I_A10_PLL2_4X>,
591 <&pll2 SUN4I_A10_PLL2_2X>,
592 <&pll2 SUN4I_A10_PLL2_1X>;
593 clock-output-names = "i2s1";
594 };
595
596 i2s2_clk: clk@01c200dc {
597 #clock-cells = <0>;
598 compatible = "allwinner,sun4i-a10-mod1-clk";
599 reg = <0x01c200dc 0x4>;
600 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
601 <&pll2 SUN4I_A10_PLL2_4X>,
602 <&pll2 SUN4I_A10_PLL2_2X>,
603 <&pll2 SUN4I_A10_PLL2_1X>;
604 clock-output-names = "i2s2";
605 };
606
607 dram_gates: clk@01c20100 {
608 #clock-cells = <1>;
609 compatible = "allwinner,sun4i-a10-dram-gates-clk";
610 reg = <0x01c20100 0x4>;
611 clocks = <&pll5 0>;
612 clock-indices = <0>,
613 <1>, <2>,
614 <3>,
615 <4>,
616 <5>, <6>,
617 <15>,
618 <24>, <25>,
619 <26>, <27>,
620 <28>, <29>;
621 clock-output-names = "dram_ve",
622 "dram_csi0", "dram_csi1",
623 "dram_ts",
624 "dram_tvd",
625 "dram_tve0", "dram_tve1",
626 "dram_output",
627 "dram_de_fe1", "dram_de_fe0",
628 "dram_de_be0", "dram_de_be1",
629 "dram_de_mp", "dram_ace";
630 };
631
632 de_be0_clk: clk@01c20104 {
633 #clock-cells = <0>;
634 #reset-cells = <0>;
635 compatible = "allwinner,sun4i-a10-display-clk";
636 reg = <0x01c20104 0x4>;
637 clocks = <&pll3>, <&pll7>, <&pll5 1>;
638 clock-output-names = "de-be0";
639 };
640
641 de_be1_clk: clk@01c20108 {
642 #clock-cells = <0>;
643 #reset-cells = <0>;
644 compatible = "allwinner,sun4i-a10-display-clk";
645 reg = <0x01c20108 0x4>;
646 clocks = <&pll3>, <&pll7>, <&pll5 1>;
647 clock-output-names = "de-be1";
648 };
649
650 de_fe0_clk: clk@01c2010c {
651 #clock-cells = <0>;
652 #reset-cells = <0>;
653 compatible = "allwinner,sun4i-a10-display-clk";
654 reg = <0x01c2010c 0x4>;
655 clocks = <&pll3>, <&pll7>, <&pll5 1>;
656 clock-output-names = "de-fe0";
657 };
658
659 de_fe1_clk: clk@01c20110 {
660 #clock-cells = <0>;
661 #reset-cells = <0>;
662 compatible = "allwinner,sun4i-a10-display-clk";
663 reg = <0x01c20110 0x4>;
664 clocks = <&pll3>, <&pll7>, <&pll5 1>;
665 clock-output-names = "de-fe1";
666 };
667
668 tcon0_ch0_clk: clk@01c20118 {
669 #clock-cells = <0>;
670 #reset-cells = <1>;
671 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
672 reg = <0x01c20118 0x4>;
673 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
674 clock-output-names = "tcon0-ch0-sclk";
675
676 };
677
678 tcon1_ch0_clk: clk@01c2011c {
679 #clock-cells = <0>;
680 #reset-cells = <1>;
681 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
682 reg = <0x01c2011c 0x4>;
683 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
684 clock-output-names = "tcon1-ch0-sclk";
685
686 };
687
688 tcon0_ch1_clk: clk@01c2012c {
689 #clock-cells = <0>;
690 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
691 reg = <0x01c2012c 0x4>;
692 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
693 clock-output-names = "tcon0-ch1-sclk";
694
695 };
696
697 tcon1_ch1_clk: clk@01c20130 {
698 #clock-cells = <0>;
699 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
700 reg = <0x01c20130 0x4>;
701 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
702 clock-output-names = "tcon1-ch1-sclk";
703
704 };
705
706 ve_clk: clk@01c2013c {
707 #clock-cells = <0>;
708 #reset-cells = <0>;
709 compatible = "allwinner,sun4i-a10-ve-clk";
710 reg = <0x01c2013c 0x4>;
711 clocks = <&pll4>;
712 clock-output-names = "ve";
713 };
714
715 codec_clk: clk@01c20140 {
716 #clock-cells = <0>;
717 compatible = "allwinner,sun4i-a10-codec-clk";
718 reg = <0x01c20140 0x4>;
719 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
720 clock-output-names = "codec";
721 };
722
723 mbus_clk: clk@01c2015c {
724 #clock-cells = <0>;
725 compatible = "allwinner,sun5i-a13-mbus-clk";
726 reg = <0x01c2015c 0x4>;
727 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
728 clock-output-names = "mbus";
729 };
730
731 /*
732 * The following two are dummy clocks, placeholders
733 * used in the gmac_tx clock. The gmac driver will
734 * choose one parent depending on the PHY interface
735 * mode, using clk_set_rate auto-reparenting.
736 *
737 * The actual TX clock rate is not controlled by the
738 * gmac_tx clock.
739 */
740 mii_phy_tx_clk: clk@2 {
741 #clock-cells = <0>;
742 compatible = "fixed-clock";
743 clock-frequency = <25000000>;
744 clock-output-names = "mii_phy_tx";
745 };
746
747 gmac_int_tx_clk: clk@3 {
748 #clock-cells = <0>;
749 compatible = "fixed-clock";
750 clock-frequency = <125000000>;
751 clock-output-names = "gmac_int_tx";
752 };
753
754 gmac_tx_clk: clk@01c20164 {
755 #clock-cells = <0>;
756 compatible = "allwinner,sun7i-a20-gmac-clk";
757 reg = <0x01c20164 0x4>;
758 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
759 clock-output-names = "gmac_tx";
760 };
761
762 /*
763 * Dummy clock used by output clocks
764 */
765 osc24M_32k: clk@1 {
766 #clock-cells = <0>;
767 compatible = "fixed-factor-clock";
768 clock-div = <750>;
769 clock-mult = <1>;
770 clocks = <&osc24M>;
771 clock-output-names = "osc24M_32k";
772 };
773
774 clk_out_a: clk@01c201f0 {
775 #clock-cells = <0>;
776 compatible = "allwinner,sun7i-a20-out-clk";
777 reg = <0x01c201f0 0x4>;
778 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
779 clock-output-names = "clk_out_a";
780 };
781
782 clk_out_b: clk@01c201f4 {
783 #clock-cells = <0>;
784 compatible = "allwinner,sun7i-a20-out-clk";
785 reg = <0x01c201f4 0x4>;
786 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
787 clock-output-names = "clk_out_b";
788 };
789 };
790
791 soc@01c00000 {
792 compatible = "simple-bus";
793 #address-cells = <1>;
794 #size-cells = <1>;
795 ranges;
796
797 sram-controller@01c00000 {
798 compatible = "allwinner,sun4i-a10-sram-controller";
799 reg = <0x01c00000 0x30>;
800 #address-cells = <1>;
801 #size-cells = <1>;
802 ranges;
803
804 sram_a: sram@00000000 {
805 compatible = "mmio-sram";
806 reg = <0x00000000 0xc000>;
807 #address-cells = <1>;
808 #size-cells = <1>;
809 ranges = <0 0x00000000 0xc000>;
810
811 emac_sram: sram-section@8000 {
812 compatible = "allwinner,sun4i-a10-sram-a3-a4";
813 reg = <0x8000 0x4000>;
814 status = "disabled";
815 };
816 };
817
818 sram_d: sram@00010000 {
819 compatible = "mmio-sram";
820 reg = <0x00010000 0x1000>;
821 #address-cells = <1>;
822 #size-cells = <1>;
823 ranges = <0 0x00010000 0x1000>;
824
825 otg_sram: sram-section@0000 {
826 compatible = "allwinner,sun4i-a10-sram-d";
827 reg = <0x0000 0x1000>;
828 status = "disabled";
829 };
830 };
831 };
832
833 nmi_intc: interrupt-controller@01c00030 {
834 compatible = "allwinner,sun7i-a20-sc-nmi";
835 interrupt-controller;
836 #interrupt-cells = <2>;
837 reg = <0x01c00030 0x0c>;
838 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
839 };
840
841 dma: dma-controller@01c02000 {
842 compatible = "allwinner,sun4i-a10-dma";
843 reg = <0x01c02000 0x1000>;
844 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&ahb_gates 6>;
846 #dma-cells = <2>;
847 };
848
849 nfc: nand@01c03000 {
850 compatible = "allwinner,sun4i-a10-nand";
851 reg = <0x01c03000 0x1000>;
852 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&ahb_gates 13>, <&nand_clk>;
854 clock-names = "ahb", "mod";
855 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
856 dma-names = "rxtx";
857 status = "disabled";
858 #address-cells = <1>;
859 #size-cells = <0>;
860 };
861
862 spi0: spi@01c05000 {
863 compatible = "allwinner,sun4i-a10-spi";
864 reg = <0x01c05000 0x1000>;
865 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&ahb_gates 20>, <&spi0_clk>;
867 clock-names = "ahb", "mod";
868 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
869 <&dma SUN4I_DMA_DEDICATED 26>;
870 dma-names = "rx", "tx";
871 status = "disabled";
872 #address-cells = <1>;
873 #size-cells = <0>;
874 num-cs = <4>;
875 };
876
877 spi1: spi@01c06000 {
878 compatible = "allwinner,sun4i-a10-spi";
879 reg = <0x01c06000 0x1000>;
880 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&ahb_gates 21>, <&spi1_clk>;
882 clock-names = "ahb", "mod";
883 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
884 <&dma SUN4I_DMA_DEDICATED 8>;
885 dma-names = "rx", "tx";
886 status = "disabled";
887 #address-cells = <1>;
888 #size-cells = <0>;
889 num-cs = <1>;
890 };
891
892 emac: ethernet@01c0b000 {
893 compatible = "allwinner,sun4i-a10-emac";
894 reg = <0x01c0b000 0x1000>;
895 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ahb_gates 17>;
897 allwinner,sram = <&emac_sram 1>;
898 status = "disabled";
899 };
900
901 mdio: mdio@01c0b080 {
902 compatible = "allwinner,sun4i-a10-mdio";
903 reg = <0x01c0b080 0x14>;
904 status = "disabled";
905 #address-cells = <1>;
906 #size-cells = <0>;
907 };
908
909 mmc0: mmc@01c0f000 {
910 compatible = "allwinner,sun7i-a20-mmc";
911 reg = <0x01c0f000 0x1000>;
912 clocks = <&ahb_gates 8>,
913 <&mmc0_clk 0>,
914 <&mmc0_clk 1>,
915 <&mmc0_clk 2>;
916 clock-names = "ahb",
917 "mmc",
918 "output",
919 "sample";
920 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
921 status = "disabled";
922 #address-cells = <1>;
923 #size-cells = <0>;
924 };
925
926 mmc1: mmc@01c10000 {
927 compatible = "allwinner,sun7i-a20-mmc";
928 reg = <0x01c10000 0x1000>;
929 clocks = <&ahb_gates 9>,
930 <&mmc1_clk 0>,
931 <&mmc1_clk 1>,
932 <&mmc1_clk 2>;
933 clock-names = "ahb",
934 "mmc",
935 "output",
936 "sample";
937 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
938 status = "disabled";
939 #address-cells = <1>;
940 #size-cells = <0>;
941 };
942
943 mmc2: mmc@01c11000 {
944 compatible = "allwinner,sun7i-a20-mmc";
945 reg = <0x01c11000 0x1000>;
946 clocks = <&ahb_gates 10>,
947 <&mmc2_clk 0>,
948 <&mmc2_clk 1>,
949 <&mmc2_clk 2>;
950 clock-names = "ahb",
951 "mmc",
952 "output",
953 "sample";
954 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
955 status = "disabled";
956 #address-cells = <1>;
957 #size-cells = <0>;
958 };
959
960 mmc3: mmc@01c12000 {
961 compatible = "allwinner,sun7i-a20-mmc";
962 reg = <0x01c12000 0x1000>;
963 clocks = <&ahb_gates 11>,
964 <&mmc3_clk 0>,
965 <&mmc3_clk 1>,
966 <&mmc3_clk 2>;
967 clock-names = "ahb",
968 "mmc",
969 "output",
970 "sample";
971 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
972 status = "disabled";
973 #address-cells = <1>;
974 #size-cells = <0>;
975 };
976
977 usb_otg: usb@01c13000 {
978 compatible = "allwinner,sun4i-a10-musb";
979 reg = <0x01c13000 0x0400>;
980 clocks = <&ahb_gates 0>;
981 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
982 interrupt-names = "mc";
983 phys = <&usbphy 0>;
984 phy-names = "usb";
985 extcon = <&usbphy 0>;
986 allwinner,sram = <&otg_sram 1>;
987 status = "disabled";
988 };
989
990 usbphy: phy@01c13400 {
991 #phy-cells = <1>;
992 compatible = "allwinner,sun7i-a20-usb-phy";
993 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
994 reg-names = "phy_ctrl", "pmu1", "pmu2";
995 clocks = <&usb_clk 8>;
996 clock-names = "usb_phy";
997 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
998 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
999 status = "disabled";
1000 };
1001
1002 ehci0: usb@01c14000 {
1003 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1004 reg = <0x01c14000 0x100>;
1005 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&ahb_gates 1>;
1007 phys = <&usbphy 1>;
1008 phy-names = "usb";
1009 status = "disabled";
1010 };
1011
1012 ohci0: usb@01c14400 {
1013 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1014 reg = <0x01c14400 0x100>;
1015 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&usb_clk 6>, <&ahb_gates 2>;
1017 phys = <&usbphy 1>;
1018 phy-names = "usb";
1019 status = "disabled";
1020 };
1021
1022 crypto: crypto-engine@01c15000 {
1023 compatible = "allwinner,sun4i-a10-crypto";
1024 reg = <0x01c15000 0x1000>;
1025 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&ahb_gates 5>, <&ss_clk>;
1027 clock-names = "ahb", "mod";
1028 };
1029
1030 spi2: spi@01c17000 {
1031 compatible = "allwinner,sun4i-a10-spi";
1032 reg = <0x01c17000 0x1000>;
1033 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1034 clocks = <&ahb_gates 22>, <&spi2_clk>;
1035 clock-names = "ahb", "mod";
1036 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
1037 <&dma SUN4I_DMA_DEDICATED 28>;
1038 dma-names = "rx", "tx";
1039 status = "disabled";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042 num-cs = <1>;
1043 };
1044
1045 ahci: sata@01c18000 {
1046 compatible = "allwinner,sun4i-a10-ahci";
1047 reg = <0x01c18000 0x1000>;
1048 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&pll6 0>, <&ahb_gates 25>;
1050 status = "disabled";
1051 };
1052
1053 ehci1: usb@01c1c000 {
1054 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1055 reg = <0x01c1c000 0x100>;
1056 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&ahb_gates 3>;
1058 phys = <&usbphy 2>;
1059 phy-names = "usb";
1060 status = "disabled";
1061 };
1062
1063 ohci1: usb@01c1c400 {
1064 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1065 reg = <0x01c1c400 0x100>;
1066 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&usb_clk 7>, <&ahb_gates 4>;
1068 phys = <&usbphy 2>;
1069 phy-names = "usb";
1070 status = "disabled";
1071 };
1072
1073 spi3: spi@01c1f000 {
1074 compatible = "allwinner,sun4i-a10-spi";
1075 reg = <0x01c1f000 0x1000>;
1076 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&ahb_gates 23>, <&spi3_clk>;
1078 clock-names = "ahb", "mod";
1079 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
1080 <&dma SUN4I_DMA_DEDICATED 30>;
1081 dma-names = "rx", "tx";
1082 status = "disabled";
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 num-cs = <1>;
1086 };
1087
1088 pio: pinctrl@01c20800 {
1089 compatible = "allwinner,sun7i-a20-pinctrl";
1090 reg = <0x01c20800 0x400>;
1091 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
1093 clock-names = "apb", "hosc", "losc";
1094 gpio-controller;
1095 interrupt-controller;
1096 #interrupt-cells = <3>;
1097 #gpio-cells = <3>;
1098
1099 clk_out_a_pins_a: clk_out_a@0 {
1100 pins = "PI12";
1101 function = "clk_out_a";
1102 };
1103
1104 clk_out_b_pins_a: clk_out_b@0 {
1105 pins = "PI13";
1106 function = "clk_out_b";
1107 };
1108
1109 emac_pins_a: emac0@0 {
1110 pins = "PA0", "PA1", "PA2",
1111 "PA3", "PA4", "PA5", "PA6",
1112 "PA7", "PA8", "PA9", "PA10",
1113 "PA11", "PA12", "PA13", "PA14",
1114 "PA15", "PA16";
1115 function = "emac";
1116 };
1117
1118 gmac_pins_mii_a: gmac_mii@0 {
1119 pins = "PA0", "PA1", "PA2",
1120 "PA3", "PA4", "PA5", "PA6",
1121 "PA7", "PA8", "PA9", "PA10",
1122 "PA11", "PA12", "PA13", "PA14",
1123 "PA15", "PA16";
1124 function = "gmac";
1125 };
1126
1127 gmac_pins_rgmii_a: gmac_rgmii@0 {
1128 pins = "PA0", "PA1", "PA2",
1129 "PA3", "PA4", "PA5", "PA6",
1130 "PA7", "PA8", "PA10",
1131 "PA11", "PA12", "PA13",
1132 "PA15", "PA16";
1133 function = "gmac";
1134 /*
1135 * data lines in RGMII mode use DDR mode
1136 * and need a higher signal drive strength
1137 */
1138 drive-strength = <40>;
1139 };
1140
1141 i2c0_pins_a: i2c0@0 {
1142 pins = "PB0", "PB1";
1143 function = "i2c0";
1144 };
1145
1146 i2c1_pins_a: i2c1@0 {
1147 pins = "PB18", "PB19";
1148 function = "i2c1";
1149 };
1150
1151 i2c2_pins_a: i2c2@0 {
1152 pins = "PB20", "PB21";
1153 function = "i2c2";
1154 };
1155
1156 i2c3_pins_a: i2c3@0 {
1157 pins = "PI0", "PI1";
1158 function = "i2c3";
1159 };
1160
1161 ir0_rx_pins_a: ir0@0 {
1162 pins = "PB4";
1163 function = "ir0";
1164 };
1165
1166 ir0_tx_pins_a: ir0@1 {
1167 pins = "PB3";
1168 function = "ir0";
1169 };
1170
1171 ir1_rx_pins_a: ir1@0 {
1172 pins = "PB23";
1173 function = "ir1";
1174 };
1175
1176 ir1_tx_pins_a: ir1@1 {
1177 pins = "PB22";
1178 function = "ir1";
1179 };
1180
1181 mmc0_pins_a: mmc0@0 {
1182 pins = "PF0", "PF1", "PF2",
1183 "PF3", "PF4", "PF5";
1184 function = "mmc0";
1185 drive-strength = <30>;
1186 bias-pull-up;
1187 };
1188
1189 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1190 pins = "PH1";
1191 function = "gpio_in";
1192 bias-pull-up;
1193 };
1194
1195 mmc2_pins_a: mmc2@0 {
1196 pins = "PC6", "PC7", "PC8",
1197 "PC9", "PC10", "PC11";
1198 function = "mmc2";
1199 drive-strength = <30>;
1200 bias-pull-up;
1201 };
1202
1203 mmc3_pins_a: mmc3@0 {
1204 pins = "PI4", "PI5", "PI6",
1205 "PI7", "PI8", "PI9";
1206 function = "mmc3";
1207 drive-strength = <30>;
1208 bias-pull-up;
1209 };
1210
1211 ps20_pins_a: ps20@0 {
1212 pins = "PI20", "PI21";
1213 function = "ps2";
1214 };
1215
1216 ps21_pins_a: ps21@0 {
1217 pins = "PH12", "PH13";
1218 function = "ps2";
1219 };
1220
1221 pwm0_pins_a: pwm0@0 {
1222 pins = "PB2";
1223 function = "pwm";
1224 };
1225
1226 pwm1_pins_a: pwm1@0 {
1227 pins = "PI3";
1228 function = "pwm";
1229 };
1230
1231 spdif_tx_pins_a: spdif@0 {
1232 pins = "PB13";
1233 function = "spdif";
1234 bias-pull-up;
1235 };
1236
1237 spi0_pins_a: spi0@0 {
1238 pins = "PI11", "PI12", "PI13";
1239 function = "spi0";
1240 };
1241
1242 spi0_cs0_pins_a: spi0_cs0@0 {
1243 pins = "PI10";
1244 function = "spi0";
1245 };
1246
1247 spi0_cs1_pins_a: spi0_cs1@0 {
1248 pins = "PI14";
1249 function = "spi0";
1250 };
1251
1252 spi1_pins_a: spi1@0 {
1253 pins = "PI17", "PI18", "PI19";
1254 function = "spi1";
1255 };
1256
1257 spi1_cs0_pins_a: spi1_cs0@0 {
1258 pins = "PI16";
1259 function = "spi1";
1260 };
1261
1262 spi2_pins_a: spi2@0 {
1263 pins = "PC20", "PC21", "PC22";
1264 function = "spi2";
1265 };
1266
1267 spi2_pins_b: spi2@1 {
1268 pins = "PB15", "PB16", "PB17";
1269 function = "spi2";
1270 };
1271
1272 spi2_cs0_pins_a: spi2_cs0@0 {
1273 pins = "PC19";
1274 function = "spi2";
1275 };
1276
1277 spi2_cs0_pins_b: spi2_cs0@1 {
1278 pins = "PB14";
1279 function = "spi2";
1280 };
1281
1282 uart0_pins_a: uart0@0 {
1283 pins = "PB22", "PB23";
1284 function = "uart0";
1285 };
1286
1287 uart2_pins_a: uart2@0 {
1288 pins = "PI16", "PI17", "PI18", "PI19";
1289 function = "uart2";
1290 };
1291
1292 uart3_pins_a: uart3@0 {
1293 pins = "PG6", "PG7", "PG8", "PG9";
1294 function = "uart3";
1295 };
1296
1297 uart3_pins_b: uart3@1 {
1298 pins = "PH0", "PH1";
1299 function = "uart3";
1300 };
1301
1302 uart4_pins_a: uart4@0 {
1303 pins = "PG10", "PG11";
1304 function = "uart4";
1305 };
1306
1307 uart4_pins_b: uart4@1 {
1308 pins = "PH4", "PH5";
1309 function = "uart4";
1310 };
1311
1312 uart5_pins_a: uart5@0 {
1313 pins = "PI10", "PI11";
1314 function = "uart5";
1315 };
1316
1317 uart6_pins_a: uart6@0 {
1318 pins = "PI12", "PI13";
1319 function = "uart6";
1320 };
1321
1322 uart7_pins_a: uart7@0 {
1323 pins = "PI20", "PI21";
1324 function = "uart7";
1325 };
1326 };
1327
1328 timer@01c20c00 {
1329 compatible = "allwinner,sun4i-a10-timer";
1330 reg = <0x01c20c00 0x90>;
1331 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1337 clocks = <&osc24M>;
1338 };
1339
1340 wdt: watchdog@01c20c90 {
1341 compatible = "allwinner,sun4i-a10-wdt";
1342 reg = <0x01c20c90 0x10>;
1343 };
1344
1345 rtc: rtc@01c20d00 {
1346 compatible = "allwinner,sun7i-a20-rtc";
1347 reg = <0x01c20d00 0x20>;
1348 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1349 };
1350
1351 pwm: pwm@01c20e00 {
1352 compatible = "allwinner,sun7i-a20-pwm";
1353 reg = <0x01c20e00 0xc>;
1354 clocks = <&osc24M>;
1355 #pwm-cells = <3>;
1356 status = "disabled";
1357 };
1358
1359 spdif: spdif@01c21000 {
1360 #sound-dai-cells = <0>;
1361 compatible = "allwinner,sun4i-a10-spdif";
1362 reg = <0x01c21000 0x400>;
1363 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&apb0_gates 1>, <&spdif_clk>;
1365 clock-names = "apb", "spdif";
1366 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1367 <&dma SUN4I_DMA_NORMAL 2>;
1368 dma-names = "rx", "tx";
1369 status = "disabled";
1370 };
1371
1372 ir0: ir@01c21800 {
1373 compatible = "allwinner,sun4i-a10-ir";
1374 clocks = <&apb0_gates 6>, <&ir0_clk>;
1375 clock-names = "apb", "ir";
1376 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1377 reg = <0x01c21800 0x40>;
1378 status = "disabled";
1379 };
1380
1381 ir1: ir@01c21c00 {
1382 compatible = "allwinner,sun4i-a10-ir";
1383 clocks = <&apb0_gates 7>, <&ir1_clk>;
1384 clock-names = "apb", "ir";
1385 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1386 reg = <0x01c21c00 0x40>;
1387 status = "disabled";
1388 };
1389
1390 i2s1: i2s@01c22000 {
1391 #sound-dai-cells = <0>;
1392 compatible = "allwinner,sun4i-a10-i2s";
1393 reg = <0x01c22000 0x400>;
1394 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1395 clocks = <&apb0_gates 4>, <&i2s1_clk>;
1396 clock-names = "apb", "mod";
1397 dmas = <&dma SUN4I_DMA_NORMAL 4>,
1398 <&dma SUN4I_DMA_NORMAL 4>;
1399 dma-names = "rx", "tx";
1400 status = "disabled";
1401 };
1402
1403 i2s0: i2s@01c22400 {
1404 #sound-dai-cells = <0>;
1405 compatible = "allwinner,sun4i-a10-i2s";
1406 reg = <0x01c22400 0x400>;
1407 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1408 clocks = <&apb0_gates 3>, <&i2s0_clk>;
1409 clock-names = "apb", "mod";
1410 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1411 <&dma SUN4I_DMA_NORMAL 3>;
1412 dma-names = "rx", "tx";
1413 status = "disabled";
1414 };
1415
1416 lradc: lradc@01c22800 {
1417 compatible = "allwinner,sun4i-a10-lradc-keys";
1418 reg = <0x01c22800 0x100>;
1419 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1420 status = "disabled";
1421 };
1422
1423 codec: codec@01c22c00 {
1424 #sound-dai-cells = <0>;
1425 compatible = "allwinner,sun7i-a20-codec";
1426 reg = <0x01c22c00 0x40>;
1427 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1428 clocks = <&apb0_gates 0>, <&codec_clk>;
1429 clock-names = "apb", "codec";
1430 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1431 <&dma SUN4I_DMA_NORMAL 19>;
1432 dma-names = "rx", "tx";
1433 status = "disabled";
1434 };
1435
1436 sid: eeprom@01c23800 {
1437 compatible = "allwinner,sun7i-a20-sid";
1438 reg = <0x01c23800 0x200>;
1439 };
1440
1441 i2s2: i2s@01c24400 {
1442 #sound-dai-cells = <0>;
1443 compatible = "allwinner,sun4i-a10-i2s";
1444 reg = <0x01c24400 0x400>;
1445 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1446 clocks = <&apb0_gates 8>, <&i2s2_clk>;
1447 clock-names = "apb", "mod";
1448 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1449 <&dma SUN4I_DMA_NORMAL 6>;
1450 dma-names = "rx", "tx";
1451 status = "disabled";
1452 };
1453
1454 rtp: rtp@01c25000 {
1455 compatible = "allwinner,sun5i-a13-ts";
1456 reg = <0x01c25000 0x100>;
1457 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1458 #thermal-sensor-cells = <0>;
1459 };
1460
1461 uart0: serial@01c28000 {
1462 compatible = "snps,dw-apb-uart";
1463 reg = <0x01c28000 0x400>;
1464 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1465 reg-shift = <2>;
1466 reg-io-width = <4>;
1467 clocks = <&apb1_gates 16>;
1468 status = "disabled";
1469 };
1470
1471 uart1: serial@01c28400 {
1472 compatible = "snps,dw-apb-uart";
1473 reg = <0x01c28400 0x400>;
1474 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1475 reg-shift = <2>;
1476 reg-io-width = <4>;
1477 clocks = <&apb1_gates 17>;
1478 status = "disabled";
1479 };
1480
1481 uart2: serial@01c28800 {
1482 compatible = "snps,dw-apb-uart";
1483 reg = <0x01c28800 0x400>;
1484 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1485 reg-shift = <2>;
1486 reg-io-width = <4>;
1487 clocks = <&apb1_gates 18>;
1488 status = "disabled";
1489 };
1490
1491 uart3: serial@01c28c00 {
1492 compatible = "snps,dw-apb-uart";
1493 reg = <0x01c28c00 0x400>;
1494 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1495 reg-shift = <2>;
1496 reg-io-width = <4>;
1497 clocks = <&apb1_gates 19>;
1498 status = "disabled";
1499 };
1500
1501 uart4: serial@01c29000 {
1502 compatible = "snps,dw-apb-uart";
1503 reg = <0x01c29000 0x400>;
1504 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1505 reg-shift = <2>;
1506 reg-io-width = <4>;
1507 clocks = <&apb1_gates 20>;
1508 status = "disabled";
1509 };
1510
1511 uart5: serial@01c29400 {
1512 compatible = "snps,dw-apb-uart";
1513 reg = <0x01c29400 0x400>;
1514 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1515 reg-shift = <2>;
1516 reg-io-width = <4>;
1517 clocks = <&apb1_gates 21>;
1518 status = "disabled";
1519 };
1520
1521 uart6: serial@01c29800 {
1522 compatible = "snps,dw-apb-uart";
1523 reg = <0x01c29800 0x400>;
1524 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1525 reg-shift = <2>;
1526 reg-io-width = <4>;
1527 clocks = <&apb1_gates 22>;
1528 status = "disabled";
1529 };
1530
1531 uart7: serial@01c29c00 {
1532 compatible = "snps,dw-apb-uart";
1533 reg = <0x01c29c00 0x400>;
1534 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1535 reg-shift = <2>;
1536 reg-io-width = <4>;
1537 clocks = <&apb1_gates 23>;
1538 status = "disabled";
1539 };
1540
1541 i2c0: i2c@01c2ac00 {
1542 compatible = "allwinner,sun7i-a20-i2c",
1543 "allwinner,sun4i-a10-i2c";
1544 reg = <0x01c2ac00 0x400>;
1545 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1546 clocks = <&apb1_gates 0>;
1547 status = "disabled";
1548 #address-cells = <1>;
1549 #size-cells = <0>;
1550 };
1551
1552 i2c1: i2c@01c2b000 {
1553 compatible = "allwinner,sun7i-a20-i2c",
1554 "allwinner,sun4i-a10-i2c";
1555 reg = <0x01c2b000 0x400>;
1556 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1557 clocks = <&apb1_gates 1>;
1558 status = "disabled";
1559 #address-cells = <1>;
1560 #size-cells = <0>;
1561 };
1562
1563 i2c2: i2c@01c2b400 {
1564 compatible = "allwinner,sun7i-a20-i2c",
1565 "allwinner,sun4i-a10-i2c";
1566 reg = <0x01c2b400 0x400>;
1567 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1568 clocks = <&apb1_gates 2>;
1569 status = "disabled";
1570 #address-cells = <1>;
1571 #size-cells = <0>;
1572 };
1573
1574 i2c3: i2c@01c2b800 {
1575 compatible = "allwinner,sun7i-a20-i2c",
1576 "allwinner,sun4i-a10-i2c";
1577 reg = <0x01c2b800 0x400>;
1578 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1579 clocks = <&apb1_gates 3>;
1580 status = "disabled";
1581 #address-cells = <1>;
1582 #size-cells = <0>;
1583 };
1584
1585 i2c4: i2c@01c2c000 {
1586 compatible = "allwinner,sun7i-a20-i2c",
1587 "allwinner,sun4i-a10-i2c";
1588 reg = <0x01c2c000 0x400>;
1589 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1590 clocks = <&apb1_gates 15>;
1591 status = "disabled";
1592 #address-cells = <1>;
1593 #size-cells = <0>;
1594 };
1595
1596 gmac: ethernet@01c50000 {
1597 compatible = "allwinner,sun7i-a20-gmac";
1598 reg = <0x01c50000 0x10000>;
1599 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1600 interrupt-names = "macirq";
1601 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1602 clock-names = "stmmaceth", "allwinner_gmac_tx";
1603 snps,pbl = <2>;
1604 snps,fixed-burst;
1605 snps,force_sf_dma_mode;
1606 status = "disabled";
1607 #address-cells = <1>;
1608 #size-cells = <0>;
1609 };
1610
1611 hstimer@01c60000 {
1612 compatible = "allwinner,sun7i-a20-hstimer";
1613 reg = <0x01c60000 0x1000>;
1614 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1615 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1616 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1617 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&ahb_gates 28>;
1619 };
1620
1621 gic: interrupt-controller@01c81000 {
1622 compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1623 reg = <0x01c81000 0x1000>,
1624 <0x01c82000 0x2000>,
1625 <0x01c84000 0x2000>,
1626 <0x01c86000 0x2000>;
1627 interrupt-controller;
1628 #interrupt-cells = <3>;
1629 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1630 };
1631
1632 ps20: ps2@01c2a000 {
1633 compatible = "allwinner,sun4i-a10-ps2";
1634 reg = <0x01c2a000 0x400>;
1635 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1636 clocks = <&apb1_gates 6>;
1637 status = "disabled";
1638 };
1639
1640 ps21: ps2@01c2a400 {
1641 compatible = "allwinner,sun4i-a10-ps2";
1642 reg = <0x01c2a400 0x400>;
1643 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1644 clocks = <&apb1_gates 7>;
1645 status = "disabled";
1646 };
1647 };
1648 };
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