]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - arch/arm/boot/dts/sun8i-a23-a33.dtsi
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branches 'spi/topic/devprop', 'spi/topic/fsl', 'spi/topic/fsl...
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sun8i-a23-a33.dtsi
1 /*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include "skeleton.dtsi"
46
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48
49 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
51 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
52
53 / {
54 interrupt-parent = <&gic>;
55
56 chosen {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60
61 simplefb_lcd: framebuffer@0 {
62 compatible = "allwinner,simple-framebuffer",
63 "simple-framebuffer";
64 allwinner,pipeline = "de_be0-lcd0";
65 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
66 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
67 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
68 status = "disabled";
69 };
70 };
71
72 timer {
73 compatible = "arm,armv7-timer";
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
78 clock-frequency = <24000000>;
79 arm,cpu-registers-not-fw-configured;
80 };
81
82 cpus {
83 enable-method = "allwinner,sun8i-a23";
84 #address-cells = <1>;
85 #size-cells = <0>;
86
87 cpu0: cpu@0 {
88 compatible = "arm,cortex-a7";
89 device_type = "cpu";
90 reg = <0>;
91 };
92
93 cpu@1 {
94 compatible = "arm,cortex-a7";
95 device_type = "cpu";
96 reg = <1>;
97 };
98 };
99
100 clocks {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges;
104
105 osc24M: osc24M_clk {
106 #clock-cells = <0>;
107 compatible = "fixed-clock";
108 clock-frequency = <24000000>;
109 clock-accuracy = <50000>;
110 clock-output-names = "osc24M";
111 };
112
113 ext_osc32k: ext_osc32k_clk {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 clock-frequency = <32768>;
117 clock-accuracy = <50000>;
118 clock-output-names = "ext-osc32k";
119 };
120 };
121
122 soc@01c00000 {
123 compatible = "simple-bus";
124 #address-cells = <1>;
125 #size-cells = <1>;
126 ranges;
127
128 dma: dma-controller@01c02000 {
129 compatible = "allwinner,sun8i-a23-dma";
130 reg = <0x01c02000 0x1000>;
131 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&ccu CLK_BUS_DMA>;
133 resets = <&ccu RST_BUS_DMA>;
134 #dma-cells = <1>;
135 };
136
137 mmc0: mmc@01c0f000 {
138 compatible = "allwinner,sun7i-a20-mmc";
139 reg = <0x01c0f000 0x1000>;
140 clocks = <&ccu CLK_BUS_MMC0>,
141 <&ccu CLK_MMC0>,
142 <&ccu CLK_MMC0_OUTPUT>,
143 <&ccu CLK_MMC0_SAMPLE>;
144 clock-names = "ahb",
145 "mmc",
146 "output",
147 "sample";
148 resets = <&ccu RST_BUS_MMC0>;
149 reset-names = "ahb";
150 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
151 status = "disabled";
152 #address-cells = <1>;
153 #size-cells = <0>;
154 };
155
156 mmc1: mmc@01c10000 {
157 compatible = "allwinner,sun7i-a20-mmc";
158 reg = <0x01c10000 0x1000>;
159 clocks = <&ccu CLK_BUS_MMC1>,
160 <&ccu CLK_MMC1>,
161 <&ccu CLK_MMC1_OUTPUT>,
162 <&ccu CLK_MMC1_SAMPLE>;
163 clock-names = "ahb",
164 "mmc",
165 "output",
166 "sample";
167 resets = <&ccu RST_BUS_MMC1>;
168 reset-names = "ahb";
169 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
170 status = "disabled";
171 #address-cells = <1>;
172 #size-cells = <0>;
173 };
174
175 mmc2: mmc@01c11000 {
176 compatible = "allwinner,sun7i-a20-mmc";
177 reg = <0x01c11000 0x1000>;
178 clocks = <&ccu CLK_BUS_MMC2>,
179 <&ccu CLK_MMC2>,
180 <&ccu CLK_MMC2_OUTPUT>,
181 <&ccu CLK_MMC2_SAMPLE>;
182 clock-names = "ahb",
183 "mmc",
184 "output",
185 "sample";
186 resets = <&ccu RST_BUS_MMC2>;
187 reset-names = "ahb";
188 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
189 status = "disabled";
190 #address-cells = <1>;
191 #size-cells = <0>;
192 };
193
194 nfc: nand@01c03000 {
195 compatible = "allwinner,sun4i-a10-nand";
196 reg = <0x01c03000 0x1000>;
197 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
199 clock-names = "ahb", "mod";
200 resets = <&ccu RST_BUS_NAND>;
201 reset-names = "ahb";
202 status = "disabled";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 };
206
207 usb_otg: usb@01c19000 {
208 /* compatible gets set in SoC specific dtsi file */
209 reg = <0x01c19000 0x0400>;
210 clocks = <&ccu CLK_BUS_OTG>;
211 resets = <&ccu RST_BUS_OTG>;
212 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
213 interrupt-names = "mc";
214 phys = <&usbphy 0>;
215 phy-names = "usb";
216 extcon = <&usbphy 0>;
217 status = "disabled";
218 };
219
220 usbphy: phy@01c19400 {
221 /*
222 * compatible and address regions get set in
223 * SoC specific dtsi file
224 */
225 clocks = <&ccu CLK_USB_PHY0>,
226 <&ccu CLK_USB_PHY1>;
227 clock-names = "usb0_phy",
228 "usb1_phy";
229 resets = <&ccu RST_USB_PHY0>,
230 <&ccu RST_USB_PHY1>;
231 reset-names = "usb0_reset",
232 "usb1_reset";
233 status = "disabled";
234 #phy-cells = <1>;
235 };
236
237 ehci0: usb@01c1a000 {
238 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
239 reg = <0x01c1a000 0x100>;
240 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&ccu CLK_BUS_EHCI>;
242 resets = <&ccu RST_BUS_EHCI>;
243 phys = <&usbphy 1>;
244 phy-names = "usb";
245 status = "disabled";
246 };
247
248 ohci0: usb@01c1a400 {
249 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
250 reg = <0x01c1a400 0x100>;
251 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
253 resets = <&ccu RST_BUS_OHCI>;
254 phys = <&usbphy 1>;
255 phy-names = "usb";
256 status = "disabled";
257 };
258
259 ccu: clock@01c20000 {
260 reg = <0x01c20000 0x400>;
261 clocks = <&osc24M>, <&rtc 0>;
262 clock-names = "hosc", "losc";
263 #clock-cells = <1>;
264 #reset-cells = <1>;
265 };
266
267 pio: pinctrl@01c20800 {
268 /* compatible gets set in SoC specific dtsi file */
269 reg = <0x01c20800 0x400>;
270 /* interrupts get set in SoC specific dtsi file */
271 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
272 clock-names = "apb", "hosc", "losc";
273 gpio-controller;
274 interrupt-controller;
275 #interrupt-cells = <3>;
276 #gpio-cells = <3>;
277
278 uart0_pins_a: uart0@0 {
279 pins = "PF2", "PF4";
280 function = "uart0";
281 };
282
283 uart1_pins_a: uart1@0 {
284 pins = "PG6", "PG7";
285 function = "uart1";
286 };
287
288 uart1_pins_cts_rts_a: uart1-cts-rts@0 {
289 pins = "PG8", "PG9";
290 function = "uart1";
291 };
292
293 mmc0_pins_a: mmc0@0 {
294 pins = "PF0", "PF1", "PF2",
295 "PF3", "PF4", "PF5";
296 function = "mmc0";
297 drive-strength = <30>;
298 bias-pull-up;
299 };
300
301 mmc1_pins_a: mmc1@0 {
302 pins = "PG0", "PG1", "PG2",
303 "PG3", "PG4", "PG5";
304 function = "mmc1";
305 drive-strength = <30>;
306 bias-pull-up;
307 };
308
309 mmc2_8bit_pins: mmc2_8bit {
310 pins = "PC5", "PC6", "PC8",
311 "PC9", "PC10", "PC11",
312 "PC12", "PC13", "PC14",
313 "PC15", "PC16";
314 function = "mmc2";
315 drive-strength = <30>;
316 bias-pull-up;
317 };
318
319 pwm0_pins: pwm0 {
320 pins = "PH0";
321 function = "pwm0";
322 };
323
324 i2c0_pins_a: i2c0@0 {
325 pins = "PH2", "PH3";
326 function = "i2c0";
327 };
328
329 i2c1_pins_a: i2c1@0 {
330 pins = "PH4", "PH5";
331 function = "i2c1";
332 };
333
334 i2c2_pins_a: i2c2@0 {
335 pins = "PE12", "PE13";
336 function = "i2c2";
337 };
338
339 lcd_rgb666_pins: lcd-rgb666@0 {
340 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
341 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
342 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
343 "PD24", "PD25", "PD26", "PD27";
344 function = "lcd0";
345 };
346 };
347
348 timer@01c20c00 {
349 compatible = "allwinner,sun4i-a10-timer";
350 reg = <0x01c20c00 0xa0>;
351 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&osc24M>;
354 };
355
356 wdt0: watchdog@01c20ca0 {
357 compatible = "allwinner,sun6i-a31-wdt";
358 reg = <0x01c20ca0 0x20>;
359 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
360 };
361
362 pwm: pwm@01c21400 {
363 compatible = "allwinner,sun7i-a20-pwm";
364 reg = <0x01c21400 0xc>;
365 clocks = <&osc24M>;
366 #pwm-cells = <3>;
367 status = "disabled";
368 };
369
370 lradc: lradc@01c22800 {
371 compatible = "allwinner,sun4i-a10-lradc-keys";
372 reg = <0x01c22800 0x100>;
373 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
374 status = "disabled";
375 };
376
377 uart0: serial@01c28000 {
378 compatible = "snps,dw-apb-uart";
379 reg = <0x01c28000 0x400>;
380 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
381 reg-shift = <2>;
382 reg-io-width = <4>;
383 clocks = <&ccu CLK_BUS_UART0>;
384 resets = <&ccu RST_BUS_UART0>;
385 dmas = <&dma 6>, <&dma 6>;
386 dma-names = "rx", "tx";
387 status = "disabled";
388 };
389
390 uart1: serial@01c28400 {
391 compatible = "snps,dw-apb-uart";
392 reg = <0x01c28400 0x400>;
393 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
394 reg-shift = <2>;
395 reg-io-width = <4>;
396 clocks = <&ccu CLK_BUS_UART1>;
397 resets = <&ccu RST_BUS_UART1>;
398 dmas = <&dma 7>, <&dma 7>;
399 dma-names = "rx", "tx";
400 status = "disabled";
401 };
402
403 uart2: serial@01c28800 {
404 compatible = "snps,dw-apb-uart";
405 reg = <0x01c28800 0x400>;
406 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
407 reg-shift = <2>;
408 reg-io-width = <4>;
409 clocks = <&ccu CLK_BUS_UART2>;
410 resets = <&ccu RST_BUS_UART2>;
411 dmas = <&dma 8>, <&dma 8>;
412 dma-names = "rx", "tx";
413 status = "disabled";
414 };
415
416 uart3: serial@01c28c00 {
417 compatible = "snps,dw-apb-uart";
418 reg = <0x01c28c00 0x400>;
419 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
420 reg-shift = <2>;
421 reg-io-width = <4>;
422 clocks = <&ccu CLK_BUS_UART3>;
423 resets = <&ccu RST_BUS_UART3>;
424 dmas = <&dma 9>, <&dma 9>;
425 dma-names = "rx", "tx";
426 status = "disabled";
427 };
428
429 uart4: serial@01c29000 {
430 compatible = "snps,dw-apb-uart";
431 reg = <0x01c29000 0x400>;
432 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
433 reg-shift = <2>;
434 reg-io-width = <4>;
435 clocks = <&ccu CLK_BUS_UART4>;
436 resets = <&ccu RST_BUS_UART4>;
437 dmas = <&dma 10>, <&dma 10>;
438 dma-names = "rx", "tx";
439 status = "disabled";
440 };
441
442 i2c0: i2c@01c2ac00 {
443 compatible = "allwinner,sun6i-a31-i2c";
444 reg = <0x01c2ac00 0x400>;
445 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&ccu CLK_BUS_I2C0>;
447 resets = <&ccu RST_BUS_I2C0>;
448 status = "disabled";
449 #address-cells = <1>;
450 #size-cells = <0>;
451 };
452
453 i2c1: i2c@01c2b000 {
454 compatible = "allwinner,sun6i-a31-i2c";
455 reg = <0x01c2b000 0x400>;
456 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&ccu CLK_BUS_I2C1>;
458 resets = <&ccu RST_BUS_I2C1>;
459 status = "disabled";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 };
463
464 i2c2: i2c@01c2b400 {
465 compatible = "allwinner,sun6i-a31-i2c";
466 reg = <0x01c2b400 0x400>;
467 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&ccu CLK_BUS_I2C2>;
469 resets = <&ccu RST_BUS_I2C2>;
470 status = "disabled";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 };
474
475 mali: gpu@1c40000 {
476 compatible = "allwinner,sun8i-a23-mali",
477 "allwinner,sun7i-a20-mali", "arm,mali-400";
478 reg = <0x01c40000 0x10000>;
479 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
486 interrupt-names = "gp",
487 "gpmmu",
488 "pp0",
489 "ppmmu0",
490 "pp1",
491 "ppmmu1",
492 "pmu";
493 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
494 clock-names = "bus", "core";
495 resets = <&ccu RST_BUS_GPU>;
496
497 assigned-clocks = <&ccu CLK_GPU>;
498 assigned-clock-rates = <384000000>;
499 };
500
501 gic: interrupt-controller@01c81000 {
502 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
503 reg = <0x01c81000 0x1000>,
504 <0x01c82000 0x2000>,
505 <0x01c84000 0x2000>,
506 <0x01c86000 0x2000>;
507 interrupt-controller;
508 #interrupt-cells = <3>;
509 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
510 };
511
512 rtc: rtc@01f00000 {
513 compatible = "allwinner,sun6i-a31-rtc";
514 reg = <0x01f00000 0x54>;
515 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
517 clock-output-names = "osc32k";
518 clocks = <&ext_osc32k>;
519 #clock-cells = <1>;
520 };
521
522 nmi_intc: interrupt-controller@01f00c0c {
523 compatible = "allwinner,sun6i-a31-sc-nmi";
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 reg = <0x01f00c0c 0x38>;
527 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
528 };
529
530 prcm@01f01400 {
531 compatible = "allwinner,sun8i-a23-prcm";
532 reg = <0x01f01400 0x200>;
533
534 ar100: ar100_clk {
535 compatible = "fixed-factor-clock";
536 #clock-cells = <0>;
537 clock-div = <1>;
538 clock-mult = <1>;
539 clocks = <&osc24M>;
540 clock-output-names = "ar100";
541 };
542
543 ahb0: ahb0_clk {
544 compatible = "fixed-factor-clock";
545 #clock-cells = <0>;
546 clock-div = <1>;
547 clock-mult = <1>;
548 clocks = <&ar100>;
549 clock-output-names = "ahb0";
550 };
551
552 apb0: apb0_clk {
553 compatible = "allwinner,sun8i-a23-apb0-clk";
554 #clock-cells = <0>;
555 clocks = <&ahb0>;
556 clock-output-names = "apb0";
557 };
558
559 apb0_gates: apb0_gates_clk {
560 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
561 #clock-cells = <1>;
562 clocks = <&apb0>;
563 clock-output-names = "apb0_pio", "apb0_timer",
564 "apb0_rsb", "apb0_uart",
565 "apb0_i2c";
566 };
567
568 apb0_rst: apb0_rst {
569 compatible = "allwinner,sun6i-a31-clock-reset";
570 #reset-cells = <1>;
571 };
572
573 codec_analog: codec-analog {
574 compatible = "allwinner,sun8i-a23-codec-analog";
575 };
576 };
577
578 cpucfg@01f01c00 {
579 compatible = "allwinner,sun8i-a23-cpuconfig";
580 reg = <0x01f01c00 0x300>;
581 };
582
583 r_uart: serial@01f02800 {
584 compatible = "snps,dw-apb-uart";
585 reg = <0x01f02800 0x400>;
586 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
587 reg-shift = <2>;
588 reg-io-width = <4>;
589 clocks = <&apb0_gates 4>;
590 resets = <&apb0_rst 4>;
591 status = "disabled";
592 };
593
594 r_pio: pinctrl@01f02c00 {
595 compatible = "allwinner,sun8i-a23-r-pinctrl";
596 reg = <0x01f02c00 0x400>;
597 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
599 clock-names = "apb", "hosc", "losc";
600 resets = <&apb0_rst 0>;
601 gpio-controller;
602 interrupt-controller;
603 #interrupt-cells = <3>;
604 #address-cells = <1>;
605 #size-cells = <0>;
606 #gpio-cells = <3>;
607
608 r_rsb_pins: r_rsb {
609 pins = "PL0", "PL1";
610 function = "s_rsb";
611 drive-strength = <20>;
612 bias-pull-up;
613 };
614
615 r_uart_pins_a: r_uart@0 {
616 pins = "PL2", "PL3";
617 function = "s_uart";
618 };
619 };
620
621 r_rsb: rsb@01f03400 {
622 compatible = "allwinner,sun8i-a23-rsb";
623 reg = <0x01f03400 0x400>;
624 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&apb0_gates 3>;
626 clock-frequency = <3000000>;
627 resets = <&apb0_rst 3>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&r_rsb_pins>;
630 status = "disabled";
631 #address-cells = <1>;
632 #size-cells = <0>;
633 };
634 };
635 };
ubuntu-bionic-kernel mirror