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Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sun8i-a23.dtsi
1 /*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50 /include/ "skeleton.dtsi"
51
52 / {
53 interrupt-parent = <&gic>;
54
55 aliases {
56 serial0 = &uart0;
57 serial1 = &uart1;
58 serial2 = &uart2;
59 serial3 = &uart3;
60 serial4 = &uart4;
61 serial5 = &r_uart;
62 };
63
64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 cpu@0 {
69 compatible = "arm,cortex-a7";
70 device_type = "cpu";
71 reg = <0>;
72 };
73
74 cpu@1 {
75 compatible = "arm,cortex-a7";
76 device_type = "cpu";
77 reg = <1>;
78 };
79 };
80
81 memory {
82 reg = <0x40000000 0x40000000>;
83 };
84
85 clocks {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges;
89
90 osc24M: osc24M_clk {
91 #clock-cells = <0>;
92 compatible = "fixed-clock";
93 clock-frequency = <24000000>;
94 clock-output-names = "osc24M";
95 };
96
97 osc32k: osc32k_clk {
98 #clock-cells = <0>;
99 compatible = "fixed-clock";
100 clock-frequency = <32768>;
101 clock-output-names = "osc32k";
102 };
103
104 pll1: clk@01c20000 {
105 #clock-cells = <0>;
106 compatible = "allwinner,sun8i-a23-pll1-clk";
107 reg = <0x01c20000 0x4>;
108 clocks = <&osc24M>;
109 clock-output-names = "pll1";
110 };
111
112 /* dummy clock until actually implemented */
113 pll6: pll6_clk {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 clock-frequency = <600000000>;
117 clock-output-names = "pll6";
118 };
119
120 cpu: cpu_clk@01c20050 {
121 #clock-cells = <0>;
122 compatible = "allwinner,sun4i-a10-cpu-clk";
123 reg = <0x01c20050 0x4>;
124
125 /*
126 * PLL1 is listed twice here.
127 * While it looks suspicious, it's actually documented
128 * that way both in the datasheet and in the code from
129 * Allwinner.
130 */
131 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
132 clock-output-names = "cpu";
133 };
134
135 axi: axi_clk@01c20050 {
136 #clock-cells = <0>;
137 compatible = "allwinner,sun8i-a23-axi-clk";
138 reg = <0x01c20050 0x4>;
139 clocks = <&cpu>;
140 clock-output-names = "axi";
141 };
142
143 ahb1_mux: ahb1_mux_clk@01c20054 {
144 #clock-cells = <0>;
145 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
146 reg = <0x01c20054 0x4>;
147 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
148 clock-output-names = "ahb1_mux";
149 };
150
151 ahb1: ahb1_clk@01c20054 {
152 #clock-cells = <0>;
153 compatible = "allwinner,sun4i-a10-ahb-clk";
154 reg = <0x01c20054 0x4>;
155 clocks = <&ahb1_mux>;
156 clock-output-names = "ahb1";
157 };
158
159 apb1: apb1_clk@01c20054 {
160 #clock-cells = <0>;
161 compatible = "allwinner,sun4i-a10-apb0-clk";
162 reg = <0x01c20054 0x4>;
163 clocks = <&ahb1>;
164 clock-output-names = "apb1";
165 };
166
167 ahb1_gates: clk@01c20060 {
168 #clock-cells = <1>;
169 compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
170 reg = <0x01c20060 0x8>;
171 clocks = <&ahb1>;
172 clock-output-names = "ahb1_mipidsi", "ahb1_dma",
173 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
174 "ahb1_nand", "ahb1_sdram",
175 "ahb1_hstimer", "ahb1_spi0",
176 "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
177 "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
178 "ahb1_csi", "ahb1_be", "ahb1_fe",
179 "ahb1_gpu", "ahb1_spinlock",
180 "ahb1_drc";
181 };
182
183 apb1_gates: clk@01c20068 {
184 #clock-cells = <1>;
185 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
186 reg = <0x01c20068 0x4>;
187 clocks = <&apb1>;
188 clock-output-names = "apb1_codec", "apb1_pio",
189 "apb1_daudio0", "apb1_daudio1";
190 };
191
192 apb2: clk@01c20058 {
193 #clock-cells = <0>;
194 compatible = "allwinner,sun4i-a10-apb1-clk";
195 reg = <0x01c20058 0x4>;
196 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
197 clock-output-names = "apb2";
198 };
199
200 apb2_gates: clk@01c2006c {
201 #clock-cells = <1>;
202 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
203 reg = <0x01c2006c 0x4>;
204 clocks = <&apb2>;
205 clock-output-names = "apb2_i2c0", "apb2_i2c1",
206 "apb2_i2c2", "apb2_uart0",
207 "apb2_uart1", "apb2_uart2",
208 "apb2_uart3", "apb2_uart4";
209 };
210
211 mmc0_clk: clk@01c20088 {
212 #clock-cells = <0>;
213 compatible = "allwinner,sun4i-a10-mod0-clk";
214 reg = <0x01c20088 0x4>;
215 clocks = <&osc24M>, <&pll6>;
216 clock-output-names = "mmc0";
217 };
218
219 mmc1_clk: clk@01c2008c {
220 #clock-cells = <0>;
221 compatible = "allwinner,sun4i-a10-mod0-clk";
222 reg = <0x01c2008c 0x4>;
223 clocks = <&osc24M>, <&pll6>;
224 clock-output-names = "mmc1";
225 };
226
227 mmc2_clk: clk@01c20090 {
228 #clock-cells = <0>;
229 compatible = "allwinner,sun4i-a10-mod0-clk";
230 reg = <0x01c20090 0x4>;
231 clocks = <&osc24M>, <&pll6>;
232 clock-output-names = "mmc2";
233 };
234 };
235
236 soc@01c00000 {
237 compatible = "simple-bus";
238 #address-cells = <1>;
239 #size-cells = <1>;
240 ranges;
241
242 dma: dma-controller@01c02000 {
243 compatible = "allwinner,sun8i-a23-dma";
244 reg = <0x01c02000 0x1000>;
245 interrupts = <0 50 4>;
246 clocks = <&ahb1_gates 6>;
247 resets = <&ahb1_rst 6>;
248 #dma-cells = <1>;
249 };
250
251 mmc0: mmc@01c0f000 {
252 compatible = "allwinner,sun5i-a13-mmc";
253 reg = <0x01c0f000 0x1000>;
254 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
255 clock-names = "ahb", "mmc";
256 resets = <&ahb1_rst 8>;
257 reset-names = "ahb";
258 interrupts = <0 60 4>;
259 status = "disabled";
260 };
261
262 mmc1: mmc@01c10000 {
263 compatible = "allwinner,sun5i-a13-mmc";
264 reg = <0x01c10000 0x1000>;
265 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
266 clock-names = "ahb", "mmc";
267 resets = <&ahb1_rst 9>;
268 reset-names = "ahb";
269 interrupts = <0 61 4>;
270 status = "disabled";
271 };
272
273 mmc2: mmc@01c11000 {
274 compatible = "allwinner,sun5i-a13-mmc";
275 reg = <0x01c11000 0x1000>;
276 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
277 clock-names = "ahb", "mmc";
278 resets = <&ahb1_rst 10>;
279 reset-names = "ahb";
280 interrupts = <0 62 4>;
281 status = "disabled";
282 };
283
284 pio: pinctrl@01c20800 {
285 compatible = "allwinner,sun8i-a23-pinctrl";
286 reg = <0x01c20800 0x400>;
287 interrupts = <0 11 4>,
288 <0 15 4>,
289 <0 17 4>;
290 clocks = <&apb1_gates 5>;
291 gpio-controller;
292 interrupt-controller;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 #gpio-cells = <3>;
296
297 uart0_pins_a: uart0@0 {
298 allwinner,pins = "PF2", "PF4";
299 allwinner,function = "uart0";
300 allwinner,drive = <0>;
301 allwinner,pull = <0>;
302 };
303
304 mmc0_pins_a: mmc0@0 {
305 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
306 allwinner,function = "mmc0";
307 allwinner,drive = <2>;
308 allwinner,pull = <0>;
309 };
310
311 mmc1_pins_a: mmc1@0 {
312 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
313 allwinner,function = "mmc1";
314 allwinner,drive = <2>;
315 allwinner,pull = <0>;
316 };
317
318 i2c0_pins_a: i2c0@0 {
319 allwinner,pins = "PH2", "PH3";
320 allwinner,function = "i2c0";
321 allwinner,drive = <0>;
322 allwinner,pull = <0>;
323 };
324
325 i2c1_pins_a: i2c1@0 {
326 allwinner,pins = "PH4", "PH5";
327 allwinner,function = "i2c1";
328 allwinner,drive = <0>;
329 allwinner,pull = <0>;
330 };
331
332 i2c2_pins_a: i2c2@0 {
333 allwinner,pins = "PE12", "PE13";
334 allwinner,function = "i2c2";
335 allwinner,drive = <0>;
336 allwinner,pull = <0>;
337 };
338 };
339
340 ahb1_rst: reset@01c202c0 {
341 #reset-cells = <1>;
342 compatible = "allwinner,sun6i-a31-clock-reset";
343 reg = <0x01c202c0 0xc>;
344 };
345
346 apb1_rst: reset@01c202d0 {
347 #reset-cells = <1>;
348 compatible = "allwinner,sun6i-a31-clock-reset";
349 reg = <0x01c202d0 0x4>;
350 };
351
352 apb2_rst: reset@01c202d8 {
353 #reset-cells = <1>;
354 compatible = "allwinner,sun6i-a31-clock-reset";
355 reg = <0x01c202d8 0x4>;
356 };
357
358 timer@01c20c00 {
359 compatible = "allwinner,sun4i-a10-timer";
360 reg = <0x01c20c00 0xa0>;
361 interrupts = <0 18 4>,
362 <0 19 4>;
363 clocks = <&osc24M>;
364 };
365
366 wdt0: watchdog@01c20ca0 {
367 compatible = "allwinner,sun6i-a31-wdt";
368 reg = <0x01c20ca0 0x20>;
369 interrupts = <0 25 4>;
370 };
371
372 uart0: serial@01c28000 {
373 compatible = "snps,dw-apb-uart";
374 reg = <0x01c28000 0x400>;
375 interrupts = <0 0 4>;
376 reg-shift = <2>;
377 reg-io-width = <4>;
378 clocks = <&apb2_gates 16>;
379 resets = <&apb2_rst 16>;
380 dmas = <&dma 6>, <&dma 6>;
381 dma-names = "rx", "tx";
382 status = "disabled";
383 };
384
385 uart1: serial@01c28400 {
386 compatible = "snps,dw-apb-uart";
387 reg = <0x01c28400 0x400>;
388 interrupts = <0 1 4>;
389 reg-shift = <2>;
390 reg-io-width = <4>;
391 clocks = <&apb2_gates 17>;
392 resets = <&apb2_rst 17>;
393 dmas = <&dma 7>, <&dma 7>;
394 dma-names = "rx", "tx";
395 status = "disabled";
396 };
397
398 uart2: serial@01c28800 {
399 compatible = "snps,dw-apb-uart";
400 reg = <0x01c28800 0x400>;
401 interrupts = <0 2 4>;
402 reg-shift = <2>;
403 reg-io-width = <4>;
404 clocks = <&apb2_gates 18>;
405 resets = <&apb2_rst 18>;
406 dmas = <&dma 8>, <&dma 8>;
407 dma-names = "rx", "tx";
408 status = "disabled";
409 };
410
411 uart3: serial@01c28c00 {
412 compatible = "snps,dw-apb-uart";
413 reg = <0x01c28c00 0x400>;
414 interrupts = <0 3 4>;
415 reg-shift = <2>;
416 reg-io-width = <4>;
417 clocks = <&apb2_gates 19>;
418 resets = <&apb2_rst 19>;
419 dmas = <&dma 9>, <&dma 9>;
420 dma-names = "rx", "tx";
421 status = "disabled";
422 };
423
424 uart4: serial@01c29000 {
425 compatible = "snps,dw-apb-uart";
426 reg = <0x01c29000 0x400>;
427 interrupts = <0 4 4>;
428 reg-shift = <2>;
429 reg-io-width = <4>;
430 clocks = <&apb2_gates 20>;
431 resets = <&apb2_rst 20>;
432 dmas = <&dma 10>, <&dma 10>;
433 dma-names = "rx", "tx";
434 status = "disabled";
435 };
436
437 i2c0: i2c@01c2ac00 {
438 compatible = "allwinner,sun6i-a31-i2c";
439 reg = <0x01c2ac00 0x400>;
440 interrupts = <0 6 4>;
441 clocks = <&apb2_gates 0>;
442 resets = <&apb2_rst 0>;
443 status = "disabled";
444 #address-cells = <1>;
445 #size-cells = <0>;
446 };
447
448 i2c1: i2c@01c2b000 {
449 compatible = "allwinner,sun6i-a31-i2c";
450 reg = <0x01c2b000 0x400>;
451 interrupts = <0 7 4>;
452 clocks = <&apb2_gates 1>;
453 resets = <&apb2_rst 1>;
454 status = "disabled";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 };
458
459 i2c2: i2c@01c2b400 {
460 compatible = "allwinner,sun6i-a31-i2c";
461 reg = <0x01c2b400 0x400>;
462 interrupts = <0 8 4>;
463 clocks = <&apb2_gates 2>;
464 resets = <&apb2_rst 2>;
465 status = "disabled";
466 #address-cells = <1>;
467 #size-cells = <0>;
468 };
469
470 gic: interrupt-controller@01c81000 {
471 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
472 reg = <0x01c81000 0x1000>,
473 <0x01c82000 0x1000>,
474 <0x01c84000 0x2000>,
475 <0x01c86000 0x2000>;
476 interrupt-controller;
477 #interrupt-cells = <3>;
478 interrupts = <1 9 0xf04>;
479 };
480
481 rtc: rtc@01f00000 {
482 compatible = "allwinner,sun6i-a31-rtc";
483 reg = <0x01f00000 0x54>;
484 interrupts = <0 40 4>, <0 41 4>;
485 };
486
487 prcm@01f01400 {
488 compatible = "allwinner,sun8i-a23-prcm";
489 reg = <0x01f01400 0x200>;
490
491 ar100: ar100_clk {
492 compatible = "fixed-factor-clock";
493 #clock-cells = <0>;
494 clock-div = <1>;
495 clock-mult = <1>;
496 clocks = <&osc24M>;
497 clock-output-names = "ar100";
498 };
499
500 ahb0: ahb0_clk {
501 compatible = "fixed-factor-clock";
502 #clock-cells = <0>;
503 clock-div = <1>;
504 clock-mult = <1>;
505 clocks = <&ar100>;
506 clock-output-names = "ahb0";
507 };
508
509 apb0: apb0_clk {
510 compatible = "allwinner,sun8i-a23-apb0-clk";
511 #clock-cells = <0>;
512 clocks = <&ahb0>;
513 clock-output-names = "apb0";
514 };
515
516 apb0_gates: apb0_gates_clk {
517 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
518 #clock-cells = <1>;
519 clocks = <&apb0>;
520 clock-output-names = "apb0_pio", "apb0_timer",
521 "apb0_rsb", "apb0_uart",
522 "apb0_i2c";
523 };
524
525 apb0_rst: apb0_rst {
526 compatible = "allwinner,sun6i-a31-clock-reset";
527 #reset-cells = <1>;
528 };
529 };
530
531 r_uart: serial@01f02800 {
532 compatible = "snps,dw-apb-uart";
533 reg = <0x01f02800 0x400>;
534 interrupts = <0 38 4>;
535 reg-shift = <2>;
536 reg-io-width = <4>;
537 clocks = <&apb0_gates 4>;
538 resets = <&apb0_rst 4>;
539 status = "disabled";
540 };
541
542 r_pio: pinctrl@01f02c00 {
543 compatible = "allwinner,sun8i-a23-r-pinctrl";
544 reg = <0x01f02c00 0x400>;
545 interrupts = <0 45 4>;
546 clocks = <&apb0_gates 0>;
547 resets = <&apb0_rst 0>;
548 gpio-controller;
549 interrupt-controller;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 #gpio-cells = <3>;
553
554 r_uart_pins_a: r_uart@0 {
555 allwinner,pins = "PL2", "PL3";
556 allwinner,function = "s_uart";
557 allwinner,drive = <0>;
558 allwinner,pull = <0>;
559 };
560 };
561 };
562 };
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