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Merge tag 'ktest-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[mirror_ubuntu-focal-kernel.git] / arch / arm / boot / dts / sun8i-a23.dtsi
1 /*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50 /include/ "skeleton.dtsi"
51
52 / {
53 interrupt-parent = <&gic>;
54
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 cpu@0 {
60 compatible = "arm,cortex-a7";
61 device_type = "cpu";
62 reg = <0>;
63 };
64
65 cpu@1 {
66 compatible = "arm,cortex-a7";
67 device_type = "cpu";
68 reg = <1>;
69 };
70 };
71
72 memory {
73 reg = <0x40000000 0x40000000>;
74 };
75
76 clocks {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80
81 osc24M: osc24M_clk {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <24000000>;
85 clock-output-names = "osc24M";
86 };
87
88 osc32k: osc32k_clk {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <32768>;
92 clock-output-names = "osc32k";
93 };
94
95 pll1: clk@01c20000 {
96 #clock-cells = <0>;
97 compatible = "allwinner,sun8i-a23-pll1-clk";
98 reg = <0x01c20000 0x4>;
99 clocks = <&osc24M>;
100 clock-output-names = "pll1";
101 };
102
103 /* dummy clock until actually implemented */
104 pll6: pll6_clk {
105 #clock-cells = <0>;
106 compatible = "fixed-clock";
107 clock-frequency = <600000000>;
108 clock-output-names = "pll6";
109 };
110
111 cpu: cpu_clk@01c20050 {
112 #clock-cells = <0>;
113 compatible = "allwinner,sun4i-a10-cpu-clk";
114 reg = <0x01c20050 0x4>;
115
116 /*
117 * PLL1 is listed twice here.
118 * While it looks suspicious, it's actually documented
119 * that way both in the datasheet and in the code from
120 * Allwinner.
121 */
122 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
123 clock-output-names = "cpu";
124 };
125
126 axi: axi_clk@01c20050 {
127 #clock-cells = <0>;
128 compatible = "allwinner,sun8i-a23-axi-clk";
129 reg = <0x01c20050 0x4>;
130 clocks = <&cpu>;
131 clock-output-names = "axi";
132 };
133
134 ahb1_mux: ahb1_mux_clk@01c20054 {
135 #clock-cells = <0>;
136 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
137 reg = <0x01c20054 0x4>;
138 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
139 clock-output-names = "ahb1_mux";
140 };
141
142 ahb1: ahb1_clk@01c20054 {
143 #clock-cells = <0>;
144 compatible = "allwinner,sun4i-a10-ahb-clk";
145 reg = <0x01c20054 0x4>;
146 clocks = <&ahb1_mux>;
147 clock-output-names = "ahb1";
148 };
149
150 apb1: apb1_clk@01c20054 {
151 #clock-cells = <0>;
152 compatible = "allwinner,sun4i-a10-apb0-clk";
153 reg = <0x01c20054 0x4>;
154 clocks = <&ahb1>;
155 clock-output-names = "apb1";
156 };
157
158 ahb1_gates: clk@01c20060 {
159 #clock-cells = <1>;
160 compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
161 reg = <0x01c20060 0x8>;
162 clocks = <&ahb1>;
163 clock-output-names = "ahb1_mipidsi", "ahb1_dma",
164 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
165 "ahb1_nand", "ahb1_sdram",
166 "ahb1_hstimer", "ahb1_spi0",
167 "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
168 "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
169 "ahb1_csi", "ahb1_be", "ahb1_fe",
170 "ahb1_gpu", "ahb1_spinlock",
171 "ahb1_drc";
172 };
173
174 apb1_gates: clk@01c20068 {
175 #clock-cells = <1>;
176 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
177 reg = <0x01c20068 0x4>;
178 clocks = <&apb1>;
179 clock-output-names = "apb1_codec", "apb1_pio",
180 "apb1_daudio0", "apb1_daudio1";
181 };
182
183 apb2: clk@01c20058 {
184 #clock-cells = <0>;
185 compatible = "allwinner,sun4i-a10-apb1-clk";
186 reg = <0x01c20058 0x4>;
187 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
188 clock-output-names = "apb2";
189 };
190
191 apb2_gates: clk@01c2006c {
192 #clock-cells = <1>;
193 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
194 reg = <0x01c2006c 0x4>;
195 clocks = <&apb2>;
196 clock-output-names = "apb2_i2c0", "apb2_i2c1",
197 "apb2_i2c2", "apb2_uart0",
198 "apb2_uart1", "apb2_uart2",
199 "apb2_uart3", "apb2_uart4";
200 };
201
202 mmc0_clk: clk@01c20088 {
203 #clock-cells = <0>;
204 compatible = "allwinner,sun4i-a10-mod0-clk";
205 reg = <0x01c20088 0x4>;
206 clocks = <&osc24M>, <&pll6>;
207 clock-output-names = "mmc0";
208 };
209
210 mmc1_clk: clk@01c2008c {
211 #clock-cells = <0>;
212 compatible = "allwinner,sun4i-a10-mod0-clk";
213 reg = <0x01c2008c 0x4>;
214 clocks = <&osc24M>, <&pll6>;
215 clock-output-names = "mmc1";
216 };
217
218 mmc2_clk: clk@01c20090 {
219 #clock-cells = <0>;
220 compatible = "allwinner,sun4i-a10-mod0-clk";
221 reg = <0x01c20090 0x4>;
222 clocks = <&osc24M>, <&pll6>;
223 clock-output-names = "mmc2";
224 };
225 };
226
227 soc@01c00000 {
228 compatible = "simple-bus";
229 #address-cells = <1>;
230 #size-cells = <1>;
231 ranges;
232
233 dma: dma-controller@01c02000 {
234 compatible = "allwinner,sun8i-a23-dma";
235 reg = <0x01c02000 0x1000>;
236 interrupts = <0 50 4>;
237 clocks = <&ahb1_gates 6>;
238 resets = <&ahb1_rst 6>;
239 #dma-cells = <1>;
240 };
241
242 mmc0: mmc@01c0f000 {
243 compatible = "allwinner,sun5i-a13-mmc";
244 reg = <0x01c0f000 0x1000>;
245 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
246 clock-names = "ahb", "mmc";
247 resets = <&ahb1_rst 8>;
248 reset-names = "ahb";
249 interrupts = <0 60 4>;
250 status = "disabled";
251 };
252
253 mmc1: mmc@01c10000 {
254 compatible = "allwinner,sun5i-a13-mmc";
255 reg = <0x01c10000 0x1000>;
256 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
257 clock-names = "ahb", "mmc";
258 resets = <&ahb1_rst 9>;
259 reset-names = "ahb";
260 interrupts = <0 61 4>;
261 status = "disabled";
262 };
263
264 mmc2: mmc@01c11000 {
265 compatible = "allwinner,sun5i-a13-mmc";
266 reg = <0x01c11000 0x1000>;
267 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
268 clock-names = "ahb", "mmc";
269 resets = <&ahb1_rst 10>;
270 reset-names = "ahb";
271 interrupts = <0 62 4>;
272 status = "disabled";
273 };
274
275 pio: pinctrl@01c20800 {
276 compatible = "allwinner,sun8i-a23-pinctrl";
277 reg = <0x01c20800 0x400>;
278 interrupts = <0 11 4>,
279 <0 15 4>,
280 <0 17 4>;
281 clocks = <&apb1_gates 5>;
282 gpio-controller;
283 interrupt-controller;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 #gpio-cells = <3>;
287
288 uart0_pins_a: uart0@0 {
289 allwinner,pins = "PF2", "PF4";
290 allwinner,function = "uart0";
291 allwinner,drive = <0>;
292 allwinner,pull = <0>;
293 };
294
295 mmc0_pins_a: mmc0@0 {
296 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
297 allwinner,function = "mmc0";
298 allwinner,drive = <2>;
299 allwinner,pull = <0>;
300 };
301
302 mmc1_pins_a: mmc1@0 {
303 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
304 allwinner,function = "mmc1";
305 allwinner,drive = <2>;
306 allwinner,pull = <0>;
307 };
308
309 i2c0_pins_a: i2c0@0 {
310 allwinner,pins = "PH2", "PH3";
311 allwinner,function = "i2c0";
312 allwinner,drive = <0>;
313 allwinner,pull = <0>;
314 };
315
316 i2c1_pins_a: i2c1@0 {
317 allwinner,pins = "PH4", "PH5";
318 allwinner,function = "i2c1";
319 allwinner,drive = <0>;
320 allwinner,pull = <0>;
321 };
322
323 i2c2_pins_a: i2c2@0 {
324 allwinner,pins = "PE12", "PE13";
325 allwinner,function = "i2c2";
326 allwinner,drive = <0>;
327 allwinner,pull = <0>;
328 };
329 };
330
331 ahb1_rst: reset@01c202c0 {
332 #reset-cells = <1>;
333 compatible = "allwinner,sun6i-a31-clock-reset";
334 reg = <0x01c202c0 0xc>;
335 };
336
337 apb1_rst: reset@01c202d0 {
338 #reset-cells = <1>;
339 compatible = "allwinner,sun6i-a31-clock-reset";
340 reg = <0x01c202d0 0x4>;
341 };
342
343 apb2_rst: reset@01c202d8 {
344 #reset-cells = <1>;
345 compatible = "allwinner,sun6i-a31-clock-reset";
346 reg = <0x01c202d8 0x4>;
347 };
348
349 timer@01c20c00 {
350 compatible = "allwinner,sun4i-a10-timer";
351 reg = <0x01c20c00 0xa0>;
352 interrupts = <0 18 4>,
353 <0 19 4>;
354 clocks = <&osc24M>;
355 };
356
357 wdt0: watchdog@01c20ca0 {
358 compatible = "allwinner,sun6i-a31-wdt";
359 reg = <0x01c20ca0 0x20>;
360 interrupts = <0 25 4>;
361 };
362
363 uart0: serial@01c28000 {
364 compatible = "snps,dw-apb-uart";
365 reg = <0x01c28000 0x400>;
366 interrupts = <0 0 4>;
367 reg-shift = <2>;
368 reg-io-width = <4>;
369 clocks = <&apb2_gates 16>;
370 resets = <&apb2_rst 16>;
371 dmas = <&dma 6>, <&dma 6>;
372 dma-names = "rx", "tx";
373 status = "disabled";
374 };
375
376 uart1: serial@01c28400 {
377 compatible = "snps,dw-apb-uart";
378 reg = <0x01c28400 0x400>;
379 interrupts = <0 1 4>;
380 reg-shift = <2>;
381 reg-io-width = <4>;
382 clocks = <&apb2_gates 17>;
383 resets = <&apb2_rst 17>;
384 dmas = <&dma 7>, <&dma 7>;
385 dma-names = "rx", "tx";
386 status = "disabled";
387 };
388
389 uart2: serial@01c28800 {
390 compatible = "snps,dw-apb-uart";
391 reg = <0x01c28800 0x400>;
392 interrupts = <0 2 4>;
393 reg-shift = <2>;
394 reg-io-width = <4>;
395 clocks = <&apb2_gates 18>;
396 resets = <&apb2_rst 18>;
397 dmas = <&dma 8>, <&dma 8>;
398 dma-names = "rx", "tx";
399 status = "disabled";
400 };
401
402 uart3: serial@01c28c00 {
403 compatible = "snps,dw-apb-uart";
404 reg = <0x01c28c00 0x400>;
405 interrupts = <0 3 4>;
406 reg-shift = <2>;
407 reg-io-width = <4>;
408 clocks = <&apb2_gates 19>;
409 resets = <&apb2_rst 19>;
410 dmas = <&dma 9>, <&dma 9>;
411 dma-names = "rx", "tx";
412 status = "disabled";
413 };
414
415 uart4: serial@01c29000 {
416 compatible = "snps,dw-apb-uart";
417 reg = <0x01c29000 0x400>;
418 interrupts = <0 4 4>;
419 reg-shift = <2>;
420 reg-io-width = <4>;
421 clocks = <&apb2_gates 20>;
422 resets = <&apb2_rst 20>;
423 dmas = <&dma 10>, <&dma 10>;
424 dma-names = "rx", "tx";
425 status = "disabled";
426 };
427
428 i2c0: i2c@01c2ac00 {
429 compatible = "allwinner,sun6i-a31-i2c";
430 reg = <0x01c2ac00 0x400>;
431 interrupts = <0 6 4>;
432 clocks = <&apb2_gates 0>;
433 resets = <&apb2_rst 0>;
434 status = "disabled";
435 #address-cells = <1>;
436 #size-cells = <0>;
437 };
438
439 i2c1: i2c@01c2b000 {
440 compatible = "allwinner,sun6i-a31-i2c";
441 reg = <0x01c2b000 0x400>;
442 interrupts = <0 7 4>;
443 clocks = <&apb2_gates 1>;
444 resets = <&apb2_rst 1>;
445 status = "disabled";
446 #address-cells = <1>;
447 #size-cells = <0>;
448 };
449
450 i2c2: i2c@01c2b400 {
451 compatible = "allwinner,sun6i-a31-i2c";
452 reg = <0x01c2b400 0x400>;
453 interrupts = <0 8 4>;
454 clocks = <&apb2_gates 2>;
455 resets = <&apb2_rst 2>;
456 status = "disabled";
457 #address-cells = <1>;
458 #size-cells = <0>;
459 };
460
461 gic: interrupt-controller@01c81000 {
462 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
463 reg = <0x01c81000 0x1000>,
464 <0x01c82000 0x1000>,
465 <0x01c84000 0x2000>,
466 <0x01c86000 0x2000>;
467 interrupt-controller;
468 #interrupt-cells = <3>;
469 interrupts = <1 9 0xf04>;
470 };
471
472 rtc: rtc@01f00000 {
473 compatible = "allwinner,sun6i-a31-rtc";
474 reg = <0x01f00000 0x54>;
475 interrupts = <0 40 4>, <0 41 4>;
476 };
477
478 prcm@01f01400 {
479 compatible = "allwinner,sun8i-a23-prcm";
480 reg = <0x01f01400 0x200>;
481
482 ar100: ar100_clk {
483 compatible = "fixed-factor-clock";
484 #clock-cells = <0>;
485 clock-div = <1>;
486 clock-mult = <1>;
487 clocks = <&osc24M>;
488 clock-output-names = "ar100";
489 };
490
491 ahb0: ahb0_clk {
492 compatible = "fixed-factor-clock";
493 #clock-cells = <0>;
494 clock-div = <1>;
495 clock-mult = <1>;
496 clocks = <&ar100>;
497 clock-output-names = "ahb0";
498 };
499
500 apb0: apb0_clk {
501 compatible = "allwinner,sun8i-a23-apb0-clk";
502 #clock-cells = <0>;
503 clocks = <&ahb0>;
504 clock-output-names = "apb0";
505 };
506
507 apb0_gates: apb0_gates_clk {
508 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
509 #clock-cells = <1>;
510 clocks = <&apb0>;
511 clock-output-names = "apb0_pio", "apb0_timer",
512 "apb0_rsb", "apb0_uart",
513 "apb0_i2c";
514 };
515
516 apb0_rst: apb0_rst {
517 compatible = "allwinner,sun6i-a31-clock-reset";
518 #reset-cells = <1>;
519 };
520 };
521
522 r_uart: serial@01f02800 {
523 compatible = "snps,dw-apb-uart";
524 reg = <0x01f02800 0x400>;
525 interrupts = <0 38 4>;
526 reg-shift = <2>;
527 reg-io-width = <4>;
528 clocks = <&apb0_gates 4>;
529 resets = <&apb0_rst 4>;
530 status = "disabled";
531 };
532
533 r_pio: pinctrl@01f02c00 {
534 compatible = "allwinner,sun8i-a23-r-pinctrl";
535 reg = <0x01f02c00 0x400>;
536 interrupts = <0 45 4>;
537 clocks = <&apb0_gates 0>;
538 resets = <&apb0_rst 0>;
539 gpio-controller;
540 interrupt-controller;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 #gpio-cells = <3>;
544
545 r_uart_pins_a: r_uart@0 {
546 allwinner,pins = "PL2", "PL3";
547 allwinner,function = "s_uart";
548 allwinner,drive = <0>;
549 allwinner,pull = <0>;
550 };
551 };
552 };
553 };
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