arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts

   1 /*
   2  * Copyright 2017 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "sun8i-a83t.dtsi"
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49
  50 / {
  51         model = "Banana Pi BPI-M3";
  52         compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
  53
  54         aliases {
  55                 ethernet0 = &emac;
  56                 serial0 = &uart0;
  57         };
  58
  59         chosen {
  60                 stdout-path = "serial0:115200n8";
  61         };
  62
  63         connector {
  64                 compatible = "hdmi-connector";
  65                 type = "a";
  66
  67                 port {
  68                         hdmi_con_in: endpoint {
  69                                 remote-endpoint = <&hdmi_out_con>;
  70                         };
  71                 };
  72         };
  73
  74         leds {
  75                 compatible = "gpio-leds";
  76
  77                 blue {
  78                         label = "bananapi-m3:blue:usr";
  79                         gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
  80                 };
  81
  82                 green {
  83                         label = "bananapi-m3:green:usr";
  84                         gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
  85                 };
  86         };
  87
  88         reg_usb1_vbus: reg-usb1-vbus {
  89                 compatible = "regulator-fixed";
  90                 regulator-name = "usb1-vbus";
  91                 regulator-min-microvolt = <5000000>;
  92                 regulator-max-microvolt = <5000000>;
  93                 regulator-boot-on;
  94                 enable-active-high;
  95                 gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
  96         };
  97
  98         wifi_pwrseq: wifi_pwrseq {
  99                 compatible = "mmc-pwrseq-simple";
 100                 clocks = <&ac100_rtc 1>;
 101                 clock-names = "ext_clock";
 102                 /* The WiFi low power clock must be 32768 Hz */
 103                 assigned-clocks = <&ac100_rtc 1>;
 104                 assigned-clock-rates = <32768>;
 105                 /* enables internal regulator and de-asserts reset */
 106                 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
 107         };
 108 };
 109
 110 &de {
 111         status = "okay";
 112 };
 113
 114 &ehci0 {
 115         /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
 116         status = "okay";
 117
 118         /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
 119 };
 120
 121 &emac {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&emac_rgmii_pins>;
 124         phy-supply = <&reg_sw>;
 125         phy-handle = <&rgmii_phy>;
 126         phy-mode = "rgmii";
 127         allwinner,rx-delay-ps = <700>;
 128         allwinner,tx-delay-ps = <700>;
 129         status = "okay";
 130 };
 131
 132 &hdmi {
 133         status = "okay";
 134 };
 135
 136 &hdmi_out {
 137         hdmi_out_con: endpoint {
 138                 remote-endpoint = <&hdmi_con_in>;
 139         };
 140 };
 141
 142 &mdio {
 143         rgmii_phy: ethernet-phy@1 {
 144                 compatible = "ethernet-phy-ieee802.3-c22";
 145                 reg = <1>;
 146         };
 147 };
 148
 149 &mmc0 {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&mmc0_pins>;
 152         vmmc-supply = <&reg_dcdc1>;
 153         bus-width = <4>;
 154         cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
 155         status = "okay";
 156 };
 157
 158 &mmc1 {
 159         vmmc-supply = <&reg_dldo1>;
 160         vqmmc-supply = <&reg_dldo1>;
 161         mmc-pwrseq = <&wifi_pwrseq>;
 162         bus-width = <4>;
 163         non-removable;
 164         status = "okay";
 165
 166         brcmf: wifi@1 {
 167                 reg = <1>;
 168                 compatible = "brcm,bcm4329-fmac";
 169                 interrupt-parent = <&r_pio>;
 170                 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
 171                 interrupt-names = "host-wake";
 172         };
 173 };
 174
 175 &mmc2 {
 176         pinctrl-names = "default";
 177         pinctrl-0 = <&mmc2_8bit_emmc_pins>;
 178         vmmc-supply = <&reg_dcdc1>;
 179         vqmmc-supply = <&reg_dcdc1>;
 180         bus-width = <8>;
 181         non-removable;
 182         cap-mmc-hw-reset;
 183         status = "okay";
 184 };
 185
 186 &r_rsb {
 187         status = "okay";
 188
 189         axp81x: pmic@3a3 {
 190                 compatible = "x-powers,axp813";
 191                 reg = <0x3a3>;
 192                 interrupt-parent = <&r_intc>;
 193                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 194                 eldoin-supply = <&reg_dcdc1>;
 195                 fldoin-supply = <&reg_dcdc5>;
 196                 swin-supply = <&reg_dcdc1>;
 197                 x-powers,drive-vbus-en;
 198         };
 199
 200         ac100: codec@e89 {
 201                 compatible = "x-powers,ac100";
 202                 reg = <0xe89>;
 203
 204                 ac100_codec: codec {
 205                         compatible = "x-powers,ac100-codec";
 206                         interrupt-parent = <&r_pio>;
 207                         interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
 208                         #clock-cells = <0>;
 209                         clock-output-names = "4M_adda";
 210                 };
 211
 212                 ac100_rtc: rtc {
 213                         compatible = "x-powers,ac100-rtc";
 214                         interrupt-parent = <&r_intc>;
 215                         interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 216                         clocks = <&ac100_codec>;
 217                         #clock-cells = <1>;
 218                         clock-output-names = "cko1_rtc",
 219                                              "cko2_rtc",
 220                                              "cko3_rtc";
 221                 };
 222         };
 223 };
 224
 225 #include "axp81x.dtsi"
 226
 227 &reg_aldo1 {
 228         regulator-always-on;
 229         regulator-min-microvolt = <1800000>;
 230         regulator-max-microvolt = <1800000>;
 231         regulator-name = "vcc-1v8";
 232 };
 233
 234 &reg_aldo2 {
 235         regulator-always-on;
 236         regulator-min-microvolt = <1800000>;
 237         regulator-max-microvolt = <1800000>;
 238         regulator-name = "dram-pll";
 239 };
 240
 241 &reg_aldo3 {
 242         regulator-always-on;
 243         regulator-min-microvolt = <3000000>;
 244         regulator-max-microvolt = <3000000>;
 245         regulator-name = "avcc";
 246 };
 247
 248 &reg_dcdc1 {
 249         /* schematics says 3.1V but FEX file says 3.3V */
 250         regulator-always-on;
 251         regulator-min-microvolt = <3300000>;
 252         regulator-max-microvolt = <3300000>;
 253         regulator-name = "vcc-3v3";
 254 };
 255
 256 &reg_dcdc2 {
 257         regulator-always-on;
 258         regulator-min-microvolt = <700000>;
 259         regulator-max-microvolt = <1100000>;
 260         regulator-name = "vdd-cpua";
 261 };
 262
 263 &reg_dcdc3 {
 264         regulator-always-on;
 265         regulator-min-microvolt = <700000>;
 266         regulator-max-microvolt = <1100000>;
 267         regulator-name = "vdd-cpub";
 268 };
 269
 270 &reg_dcdc4 {
 271         regulator-min-microvolt = <700000>;
 272         regulator-max-microvolt = <1100000>;
 273         regulator-name = "vdd-gpu";
 274 };
 275
 276 &reg_dcdc5 {
 277         regulator-always-on;
 278         regulator-min-microvolt = <1200000>;
 279         regulator-max-microvolt = <1200000>;
 280         regulator-name = "vcc-dram";
 281 };
 282
 283 &reg_dcdc6 {
 284         regulator-always-on;
 285         regulator-min-microvolt = <900000>;
 286         regulator-max-microvolt = <900000>;
 287         regulator-name = "vdd-sys";
 288 };
 289
 290 &reg_dldo1 {
 291         /*
 292          * This powers both the WiFi/BT module's main power, I/O supply,
 293          * and external pull-ups on all the data lines. It should be set
 294          * to the same voltage as the I/O supply (DCDC1 in this case) to
 295          * avoid any leakage or mismatch.
 296          */
 297         regulator-min-microvolt = <3300000>;
 298         regulator-max-microvolt = <3300000>;
 299         regulator-name = "vcc-wifi";
 300 };
 301
 302 &reg_dldo3 {
 303         regulator-always-on;
 304         regulator-min-microvolt = <2500000>;
 305         regulator-max-microvolt = <2500000>;
 306         regulator-name = "vcc-pd";
 307 };
 308
 309 &reg_drivevbus {
 310         regulator-name = "usb0-vbus";
 311         status = "okay";
 312 };
 313
 314 &reg_fldo1 {
 315         regulator-min-microvolt = <1080000>;
 316         regulator-max-microvolt = <1320000>;
 317         regulator-name = "vdd12-hsic";
 318 };
 319
 320 &reg_fldo2 {
 321         /*
 322          * Despite the embedded CPUs core not being used in any way,
 323          * this must remain on or the system will hang.
 324          */
 325         regulator-always-on;
 326         regulator-min-microvolt = <700000>;
 327         regulator-max-microvolt = <1100000>;
 328         regulator-name = "vdd-cpus";
 329 };
 330
 331 &reg_rtc_ldo {
 332         regulator-name = "vcc-rtc";
 333 };
 334
 335 &reg_sw {
 336         /*
 337          * The PHY requires 20ms after all voltages
 338          * are applied until core logic is ready and
 339          * 30ms after the reset pin is de-asserted.
 340          * Set a 100ms delay to account for PMIC
 341          * ramp time and board traces.
 342          */
 343         regulator-enable-ramp-delay = <100000>;
 344         regulator-name = "vcc-ephy";
 345 };
 346
 347 &uart0 {
 348         pinctrl-names = "default";
 349         pinctrl-0 = <&uart0_pb_pins>;
 350         status = "okay";
 351 };
 352
 353 &usbphy {
 354         usb1_vbus-supply = <&reg_usb1_vbus>;
 355         status = "okay";
 356 };