arch/arm/boot/dts/sun8i-h3.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "skeleton.dtsi"
  44
  45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/sun4i-a10.h>
  48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu@0 {
  58                         compatible = "arm,cortex-a7";
  59                         device_type = "cpu";
  60                         reg = <0>;
  61                 };
  62
  63                 cpu@1 {
  64                         compatible = "arm,cortex-a7";
  65                         device_type = "cpu";
  66                         reg = <1>;
  67                 };
  68
  69                 cpu@2 {
  70                         compatible = "arm,cortex-a7";
  71                         device_type = "cpu";
  72                         reg = <2>;
  73                 };
  74
  75                 cpu@3 {
  76                         compatible = "arm,cortex-a7";
  77                         device_type = "cpu";
  78                         reg = <3>;
  79                 };
  80         };
  81
  82         timer {
  83                 compatible = "arm,armv7-timer";
  84                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  85                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  86                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  87                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  88         };
  89
  90         clocks {
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93                 ranges;
  94
  95                 osc24M: osc24M_clk {
  96                         #clock-cells = <0>;
  97                         compatible = "fixed-clock";
  98                         clock-frequency = <24000000>;
  99                         clock-output-names = "osc24M";
 100                 };
 101
 102                 osc32k: osc32k_clk {
 103                         #clock-cells = <0>;
 104                         compatible = "fixed-clock";
 105                         clock-frequency = <32768>;
 106                         clock-output-names = "osc32k";
 107                 };
 108
 109                 apb0: apb0_clk {
 110                         compatible = "fixed-factor-clock";
 111                         #clock-cells = <0>;
 112                         clock-div = <1>;
 113                         clock-mult = <1>;
 114                         clocks = <&osc24M>;
 115                         clock-output-names = "apb0";
 116                 };
 117
 118                 apb0_gates: clk@01f01428 {
 119                         compatible = "allwinner,sun8i-h3-apb0-gates-clk",
 120                                      "allwinner,sun4i-a10-gates-clk";
 121                         reg = <0x01f01428 0x4>;
 122                         #clock-cells = <1>;
 123                         clocks = <&apb0>;
 124                         clock-indices = <0>, <1>;
 125                         clock-output-names = "apb0_pio", "apb0_ir";
 126                 };
 127
 128                 ir_clk: ir_clk@01f01454 {
 129                         compatible = "allwinner,sun4i-a10-mod0-clk";
 130                         reg = <0x01f01454 0x4>;
 131                         #clock-cells = <0>;
 132                         clocks = <&osc32k>, <&osc24M>;
 133                         clock-output-names = "ir";
 134                 };
 135         };
 136
 137         soc {
 138                 compatible = "simple-bus";
 139                 #address-cells = <1>;
 140                 #size-cells = <1>;
 141                 ranges;
 142
 143                 dma: dma-controller@01c02000 {
 144                         compatible = "allwinner,sun8i-h3-dma";
 145                         reg = <0x01c02000 0x1000>;
 146                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&ccu CLK_BUS_DMA>;
 148                         resets = <&ccu RST_BUS_DMA>;
 149                         #dma-cells = <1>;
 150                 };
 151
 152                 mmc0: mmc@01c0f000 {
 153                         compatible = "allwinner,sun7i-a20-mmc";
 154                         reg = <0x01c0f000 0x1000>;
 155                         clocks = <&ccu CLK_BUS_MMC0>,
 156                                  <&ccu CLK_MMC0>,
 157                                  <&ccu CLK_MMC0_OUTPUT>,
 158                                  <&ccu CLK_MMC0_SAMPLE>;
 159                         clock-names = "ahb",
 160                                       "mmc",
 161                                       "output",
 162                                       "sample";
 163                         resets = <&ccu RST_BUS_MMC0>;
 164                         reset-names = "ahb";
 165                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 166                         status = "disabled";
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                 };
 170
 171                 mmc1: mmc@01c10000 {
 172                         compatible = "allwinner,sun7i-a20-mmc";
 173                         reg = <0x01c10000 0x1000>;
 174                         clocks = <&ccu CLK_BUS_MMC1>,
 175                                  <&ccu CLK_MMC1>,
 176                                  <&ccu CLK_MMC1_OUTPUT>,
 177                                  <&ccu CLK_MMC1_SAMPLE>;
 178                         clock-names = "ahb",
 179                                       "mmc",
 180                                       "output",
 181                                       "sample";
 182                         resets = <&ccu RST_BUS_MMC1>;
 183                         reset-names = "ahb";
 184                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 185                         status = "disabled";
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                 };
 189
 190                 mmc2: mmc@01c11000 {
 191                         compatible = "allwinner,sun7i-a20-mmc";
 192                         reg = <0x01c11000 0x1000>;
 193                         clocks = <&ccu CLK_BUS_MMC2>,
 194                                  <&ccu CLK_MMC2>,
 195                                  <&ccu CLK_MMC2_OUTPUT>,
 196                                  <&ccu CLK_MMC2_SAMPLE>;
 197                         clock-names = "ahb",
 198                                       "mmc",
 199                                       "output",
 200                                       "sample";
 201                         resets = <&ccu RST_BUS_MMC2>;
 202                         reset-names = "ahb";
 203                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 204                         status = "disabled";
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                 };
 208
 209                 usbphy: phy@01c19400 {
 210                         compatible = "allwinner,sun8i-h3-usb-phy";
 211                         reg = <0x01c19400 0x2c>,
 212                               <0x01c1a800 0x4>,
 213                               <0x01c1b800 0x4>,
 214                               <0x01c1c800 0x4>,
 215                               <0x01c1d800 0x4>;
 216                         reg-names = "phy_ctrl",
 217                                     "pmu0",
 218                                     "pmu1",
 219                                     "pmu2",
 220                                     "pmu3";
 221                         clocks = <&ccu CLK_USB_PHY0>,
 222                                  <&ccu CLK_USB_PHY1>,
 223                                  <&ccu CLK_USB_PHY2>,
 224                                  <&ccu CLK_USB_PHY3>;
 225                         clock-names = "usb0_phy",
 226                                       "usb1_phy",
 227                                       "usb2_phy",
 228                                       "usb3_phy";
 229                         resets = <&ccu RST_USB_PHY0>,
 230                                  <&ccu RST_USB_PHY1>,
 231                                  <&ccu RST_USB_PHY2>,
 232                                  <&ccu RST_USB_PHY3>;
 233                         reset-names = "usb0_reset",
 234                                       "usb1_reset",
 235                                       "usb2_reset",
 236                                       "usb3_reset";
 237                         status = "disabled";
 238                         #phy-cells = <1>;
 239                 };
 240
 241                 ehci1: usb@01c1b000 {
 242                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 243                         reg = <0x01c1b000 0x100>;
 244                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
 246                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 247                         phys = <&usbphy 1>;
 248                         phy-names = "usb";
 249                         status = "disabled";
 250                 };
 251
 252                 ohci1: usb@01c1b400 {
 253                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 254                         reg = <0x01c1b400 0x100>;
 255                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 256                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
 257                                  <&ccu CLK_USB_OHCI1>;
 258                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 259                         phys = <&usbphy 1>;
 260                         phy-names = "usb";
 261                         status = "disabled";
 262                 };
 263
 264                 ehci2: usb@01c1c000 {
 265                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 266                         reg = <0x01c1c000 0x100>;
 267                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 268                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
 269                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 270                         phys = <&usbphy 2>;
 271                         phy-names = "usb";
 272                         status = "disabled";
 273                 };
 274
 275                 ohci2: usb@01c1c400 {
 276                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 277                         reg = <0x01c1c400 0x100>;
 278                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
 280                                  <&ccu CLK_USB_OHCI2>;
 281                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 282                         phys = <&usbphy 2>;
 283                         phy-names = "usb";
 284                         status = "disabled";
 285                 };
 286
 287                 ehci3: usb@01c1d000 {
 288                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 289                         reg = <0x01c1d000 0x100>;
 290                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 291                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
 292                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 293                         phys = <&usbphy 3>;
 294                         phy-names = "usb";
 295                         status = "disabled";
 296                 };
 297
 298                 ohci3: usb@01c1d400 {
 299                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 300                         reg = <0x01c1d400 0x100>;
 301                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 302                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
 303                                  <&ccu CLK_USB_OHCI3>;
 304                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 305                         phys = <&usbphy 3>;
 306                         phy-names = "usb";
 307                         status = "disabled";
 308                 };
 309
 310                 ccu: clock@01c20000 {
 311                         compatible = "allwinner,sun8i-h3-ccu";
 312                         reg = <0x01c20000 0x400>;
 313                         clocks = <&osc24M>, <&osc32k>;
 314                         clock-names = "hosc", "losc";
 315                         #clock-cells = <1>;
 316                         #reset-cells = <1>;
 317                 };
 318
 319                 pio: pinctrl@01c20800 {
 320                         compatible = "allwinner,sun8i-h3-pinctrl";
 321                         reg = <0x01c20800 0x400>;
 322                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 325                         clock-names = "apb", "hosc", "losc";
 326                         gpio-controller;
 327                         #gpio-cells = <3>;
 328                         interrupt-controller;
 329                         #interrupt-cells = <3>;
 330
 331                         i2c0_pins: i2c0 {
 332                                 pins = "PA11", "PA12";
 333                                 function = "i2c0";
 334                         };
 335
 336                         i2c1_pins: i2c1 {
 337                                 pins = "PA18", "PA19";
 338                                 function = "i2c1";
 339                         };
 340
 341                         i2c2_pins: i2c2 {
 342                                 pins = "PE12", "PE13";
 343                                 function = "i2c2";
 344                         };
 345
 346                         mmc0_pins_a: mmc0@0 {
 347                                 pins = "PF0", "PF1", "PF2", "PF3",
 348                                        "PF4", "PF5";
 349                                 function = "mmc0";
 350                                 drive-strength = <30>;
 351                                 bias-pull-up;
 352                         };
 353
 354                         mmc0_cd_pin: mmc0_cd_pin@0 {
 355                                 pins = "PF6";
 356                                 function = "gpio_in";
 357                                 bias-pull-up;
 358                         };
 359
 360                         mmc1_pins_a: mmc1@0 {
 361                                 pins = "PG0", "PG1", "PG2", "PG3",
 362                                        "PG4", "PG5";
 363                                 function = "mmc1";
 364                                 drive-strength = <30>;
 365                                 bias-pull-up;
 366                         };
 367
 368                         mmc2_8bit_pins: mmc2_8bit {
 369                                 pins = "PC5", "PC6", "PC8",
 370                                        "PC9", "PC10", "PC11",
 371                                        "PC12", "PC13", "PC14",
 372                                        "PC15", "PC16";
 373                                 function = "mmc2";
 374                                 drive-strength = <30>;
 375                                 bias-pull-up;
 376                         };
 377
 378                         spdif_tx_pins_a: spdif@0 {
 379                                 pins = "PA17";
 380                                 function = "spdif";
 381                         };
 382
 383                         spi0_pins: spi0 {
 384                                 pins = "PC0", "PC1", "PC2", "PC3";
 385                                 function = "spi0";
 386                         };
 387
 388                         spi1_pins: spi1 {
 389                                 pins = "PA15", "PA16", "PA14", "PA13";
 390                                 function = "spi1";
 391                         };
 392
 393                         uart0_pins_a: uart0@0 {
 394                                 pins = "PA4", "PA5";
 395                                 function = "uart0";
 396                         };
 397
 398                         uart1_pins: uart1 {
 399                                 pins = "PG6", "PG7";
 400                                 function = "uart1";
 401                         };
 402
 403                         uart1_rts_cts_pins: uart1_rts_cts {
 404                                 pins = "PG8", "PG9";
 405                                 function = "uart1";
 406                         };
 407
 408                         uart2_pins: uart2 {
 409                                 pins = "PA0", "PA1";
 410                                 function = "uart2";
 411                         };
 412
 413                         uart3_pins: uart3 {
 414                                 pins = "PA13", "PA14";
 415                                 function = "uart3";
 416                         };
 417                 };
 418
 419                 timer@01c20c00 {
 420                         compatible = "allwinner,sun4i-a10-timer";
 421                         reg = <0x01c20c00 0xa0>;
 422                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 423                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 424                         clocks = <&osc24M>;
 425                 };
 426
 427                 spi0: spi@01c68000 {
 428                         compatible = "allwinner,sun8i-h3-spi";
 429                         reg = <0x01c68000 0x1000>;
 430                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 431                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 432                         clock-names = "ahb", "mod";
 433                         dmas = <&dma 23>, <&dma 23>;
 434                         dma-names = "rx", "tx";
 435                         pinctrl-names = "default";
 436                         pinctrl-0 = <&spi0_pins>;
 437                         resets = <&ccu RST_BUS_SPI0>;
 438                         status = "disabled";
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                 };
 442
 443                 spi1: spi@01c69000 {
 444                         compatible = "allwinner,sun8i-h3-spi";
 445                         reg = <0x01c69000 0x1000>;
 446                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 447                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 448                         clock-names = "ahb", "mod";
 449                         dmas = <&dma 24>, <&dma 24>;
 450                         dma-names = "rx", "tx";
 451                         pinctrl-names = "default";
 452                         pinctrl-0 = <&spi1_pins>;
 453                         resets = <&ccu RST_BUS_SPI1>;
 454                         status = "disabled";
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                 };
 458
 459                 wdt0: watchdog@01c20ca0 {
 460                         compatible = "allwinner,sun6i-a31-wdt";
 461                         reg = <0x01c20ca0 0x20>;
 462                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 463                 };
 464
 465                 spdif: spdif@01c21000 {
 466                         #sound-dai-cells = <0>;
 467                         compatible = "allwinner,sun8i-h3-spdif";
 468                         reg = <0x01c21000 0x400>;
 469                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 470                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 471                         resets = <&ccu RST_BUS_SPDIF>;
 472                         clock-names = "apb", "spdif";
 473                         dmas = <&dma 2>;
 474                         dma-names = "tx";
 475                         status = "disabled";
 476                 };
 477
 478                 pwm: pwm@01c21400 {
 479                         compatible = "allwinner,sun8i-h3-pwm";
 480                         reg = <0x01c21400 0x8>;
 481                         clocks = <&osc24M>;
 482                         #pwm-cells = <3>;
 483                         status = "disabled";
 484                 };
 485
 486                 codec: codec@01c22c00 {
 487                         #sound-dai-cells = <0>;
 488                         compatible = "allwinner,sun8i-h3-codec";
 489                         reg = <0x01c22c00 0x400>;
 490                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 491                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 492                         clock-names = "apb", "codec";
 493                         resets = <&ccu RST_BUS_CODEC>;
 494                         dmas = <&dma 15>, <&dma 15>;
 495                         dma-names = "rx", "tx";
 496                         allwinner,codec-analog-controls = <&codec_analog>;
 497                         status = "disabled";
 498                 };
 499
 500                 uart0: serial@01c28000 {
 501                         compatible = "snps,dw-apb-uart";
 502                         reg = <0x01c28000 0x400>;
 503                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 504                         reg-shift = <2>;
 505                         reg-io-width = <4>;
 506                         clocks = <&ccu CLK_BUS_UART0>;
 507                         resets = <&ccu RST_BUS_UART0>;
 508                         dmas = <&dma 6>, <&dma 6>;
 509                         dma-names = "rx", "tx";
 510                         status = "disabled";
 511                 };
 512
 513                 uart1: serial@01c28400 {
 514                         compatible = "snps,dw-apb-uart";
 515                         reg = <0x01c28400 0x400>;
 516                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 517                         reg-shift = <2>;
 518                         reg-io-width = <4>;
 519                         clocks = <&ccu CLK_BUS_UART1>;
 520                         resets = <&ccu RST_BUS_UART1>;
 521                         dmas = <&dma 7>, <&dma 7>;
 522                         dma-names = "rx", "tx";
 523                         status = "disabled";
 524                 };
 525
 526                 uart2: serial@01c28800 {
 527                         compatible = "snps,dw-apb-uart";
 528                         reg = <0x01c28800 0x400>;
 529                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 530                         reg-shift = <2>;
 531                         reg-io-width = <4>;
 532                         clocks = <&ccu CLK_BUS_UART2>;
 533                         resets = <&ccu RST_BUS_UART2>;
 534                         dmas = <&dma 8>, <&dma 8>;
 535                         dma-names = "rx", "tx";
 536                         status = "disabled";
 537                 };
 538
 539                 uart3: serial@01c28c00 {
 540                         compatible = "snps,dw-apb-uart";
 541                         reg = <0x01c28c00 0x400>;
 542                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 543                         reg-shift = <2>;
 544                         reg-io-width = <4>;
 545                         clocks = <&ccu CLK_BUS_UART3>;
 546                         resets = <&ccu RST_BUS_UART3>;
 547                         dmas = <&dma 9>, <&dma 9>;
 548                         dma-names = "rx", "tx";
 549                         status = "disabled";
 550                 };
 551
 552                 i2c0: i2c@01c2ac00 {
 553                         compatible = "allwinner,sun6i-a31-i2c";
 554                         reg = <0x01c2ac00 0x400>;
 555                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 556                         clocks = <&ccu CLK_BUS_I2C0>;
 557                         resets = <&ccu RST_BUS_I2C0>;
 558                         pinctrl-names = "default";
 559                         pinctrl-0 = <&i2c0_pins>;
 560                         status = "disabled";
 561                         #address-cells = <1>;
 562                         #size-cells = <0>;
 563                 };
 564
 565                 i2c1: i2c@01c2b000 {
 566                         compatible = "allwinner,sun6i-a31-i2c";
 567                         reg = <0x01c2b000 0x400>;
 568                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 569                         clocks = <&ccu CLK_BUS_I2C1>;
 570                         resets = <&ccu RST_BUS_I2C1>;
 571                         pinctrl-names = "default";
 572                         pinctrl-0 = <&i2c1_pins>;
 573                         status = "disabled";
 574                         #address-cells = <1>;
 575                         #size-cells = <0>;
 576                 };
 577
 578                 i2c2: i2c@01c2b400 {
 579                         compatible = "allwinner,sun6i-a31-i2c";
 580                         reg = <0x01c2b000 0x400>;
 581                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 582                         clocks = <&ccu CLK_BUS_I2C2>;
 583                         resets = <&ccu RST_BUS_I2C2>;
 584                         pinctrl-names = "default";
 585                         pinctrl-0 = <&i2c2_pins>;
 586                         status = "disabled";
 587                         #address-cells = <1>;
 588                         #size-cells = <0>;
 589                 };
 590
 591                 gic: interrupt-controller@01c81000 {
 592                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 593                         reg = <0x01c81000 0x1000>,
 594                               <0x01c82000 0x2000>,
 595                               <0x01c84000 0x2000>,
 596                               <0x01c86000 0x2000>;
 597                         interrupt-controller;
 598                         #interrupt-cells = <3>;
 599                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 600                 };
 601
 602                 rtc: rtc@01f00000 {
 603                         compatible = "allwinner,sun6i-a31-rtc";
 604                         reg = <0x01f00000 0x54>;
 605                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 606                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 607                 };
 608
 609                 apb0_reset: reset@01f014b0 {
 610                         reg = <0x01f014b0 0x4>;
 611                         compatible = "allwinner,sun6i-a31-clock-reset";
 612                         #reset-cells = <1>;
 613                 };
 614
 615                 codec_analog: codec-analog@01f015c0 {
 616                         compatible = "allwinner,sun8i-h3-codec-analog";
 617                         reg = <0x01f015c0 0x4>;
 618                 };
 619
 620                 ir: ir@01f02000 {
 621                         compatible = "allwinner,sun5i-a13-ir";
 622                         clocks = <&apb0_gates 1>, <&ir_clk>;
 623                         clock-names = "apb", "ir";
 624                         resets = <&apb0_reset 1>;
 625                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 626                         reg = <0x01f02000 0x40>;
 627                         status = "disabled";
 628                 };
 629
 630                 r_pio: pinctrl@01f02c00 {
 631                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 632                         reg = <0x01f02c00 0x400>;
 633                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 634                         clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
 635                         clock-names = "apb", "hosc", "losc";
 636                         resets = <&apb0_reset 0>;
 637                         gpio-controller;
 638                         #gpio-cells = <3>;
 639                         interrupt-controller;
 640                         #interrupt-cells = <3>;
 641
 642                         ir_pins_a: ir@0 {
 643                                 pins = "PL11";
 644                                 function = "s_cir_rx";
 645                         };
 646                 };
 647         };
 648 };