2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/reset/sun8i-r40-ccu.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
53 interrupt-parent = <&gic>;
62 compatible = "fixed-clock";
63 clock-frequency = <24000000>;
64 clock-output-names = "osc24M";
69 compatible = "fixed-clock";
70 clock-frequency = <32768>;
71 clock-output-names = "osc32k";
80 compatible = "arm,cortex-a7";
86 compatible = "arm,cortex-a7";
92 compatible = "arm,cortex-a7";
98 compatible = "arm,cortex-a7";
105 compatible = "allwinner,sun8i-r40-display-engine";
106 allwinner,pipelines = <&mixer0>, <&mixer1>;
111 compatible = "simple-bus";
112 #address-cells = <1>;
116 display_clocks: clock@1000000 {
117 compatible = "allwinner,sun8i-r40-de2-clk",
118 "allwinner,sun8i-h3-de2-clk";
119 reg = <0x01000000 0x100000>;
120 clocks = <&ccu CLK_DE>,
124 resets = <&ccu RST_BUS_DE>;
129 mixer0: mixer@1100000 {
130 compatible = "allwinner,sun8i-r40-de2-mixer-0";
131 reg = <0x01100000 0x100000>;
132 clocks = <&display_clocks CLK_BUS_MIXER0>,
133 <&display_clocks CLK_MIXER0>;
136 resets = <&display_clocks RST_MIXER0>;
139 #address-cells = <1>;
144 mixer0_out_tcon_top: endpoint {
145 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
151 mixer1: mixer@1200000 {
152 compatible = "allwinner,sun8i-r40-de2-mixer-1";
153 reg = <0x01200000 0x100000>;
154 clocks = <&display_clocks CLK_BUS_MIXER1>,
155 <&display_clocks CLK_MIXER1>;
158 resets = <&display_clocks RST_WB>;
161 #address-cells = <1>;
166 mixer1_out_tcon_top: endpoint {
167 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
173 nmi_intc: interrupt-controller@1c00030 {
174 compatible = "allwinner,sun7i-a20-sc-nmi";
175 interrupt-controller;
176 #interrupt-cells = <2>;
177 reg = <0x01c00030 0x0c>;
178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
182 compatible = "allwinner,sun8i-r40-mmc",
183 "allwinner,sun50i-a64-mmc";
184 reg = <0x01c0f000 0x1000>;
185 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
186 clock-names = "ahb", "mmc";
187 resets = <&ccu RST_BUS_MMC0>;
189 pinctrl-0 = <&mmc0_pins>;
190 pinctrl-names = "default";
191 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
193 #address-cells = <1>;
198 compatible = "allwinner,sun8i-r40-mmc",
199 "allwinner,sun50i-a64-mmc";
200 reg = <0x01c10000 0x1000>;
201 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
202 clock-names = "ahb", "mmc";
203 resets = <&ccu RST_BUS_MMC1>;
205 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
207 #address-cells = <1>;
212 compatible = "allwinner,sun8i-r40-emmc",
213 "allwinner,sun50i-a64-emmc";
214 reg = <0x01c11000 0x1000>;
215 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
216 clock-names = "ahb", "mmc";
217 resets = <&ccu RST_BUS_MMC2>;
219 pinctrl-0 = <&mmc2_pins>;
220 pinctrl-names = "default";
221 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
223 #address-cells = <1>;
228 compatible = "allwinner,sun8i-r40-mmc",
229 "allwinner,sun50i-a64-mmc";
230 reg = <0x01c12000 0x1000>;
231 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
232 clock-names = "ahb", "mmc";
233 resets = <&ccu RST_BUS_MMC3>;
235 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
237 #address-cells = <1>;
241 usbphy: phy@1c13400 {
242 compatible = "allwinner,sun8i-r40-usb-phy";
243 reg = <0x01c13400 0x14>,
247 reg-names = "phy_ctrl",
251 clocks = <&ccu CLK_USB_PHY0>,
254 clock-names = "usb0_phy",
257 resets = <&ccu RST_USB_PHY0>,
260 reset-names = "usb0_reset",
268 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
269 reg = <0x01c19000 0x100>;
270 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&ccu CLK_BUS_EHCI1>;
272 resets = <&ccu RST_BUS_EHCI1>;
279 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
280 reg = <0x01c19400 0x100>;
281 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&ccu CLK_BUS_OHCI1>,
283 <&ccu CLK_USB_OHCI1>;
284 resets = <&ccu RST_BUS_OHCI1>;
291 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
292 reg = <0x01c1c000 0x100>;
293 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&ccu CLK_BUS_EHCI2>;
295 resets = <&ccu RST_BUS_EHCI2>;
302 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
303 reg = <0x01c1c400 0x100>;
304 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&ccu CLK_BUS_OHCI2>,
306 <&ccu CLK_USB_OHCI2>;
307 resets = <&ccu RST_BUS_OHCI2>;
314 compatible = "allwinner,sun8i-r40-ccu";
315 reg = <0x01c20000 0x400>;
316 clocks = <&osc24M>, <&osc32k>;
317 clock-names = "hosc", "losc";
322 pio: pinctrl@1c20800 {
323 compatible = "allwinner,sun8i-r40-pinctrl";
324 reg = <0x01c20800 0x400>;
325 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
327 clock-names = "apb", "hosc", "losc";
329 interrupt-controller;
330 #interrupt-cells = <3>;
333 gmac_rgmii_pins: gmac-rgmii-pins {
334 pins = "PA0", "PA1", "PA2", "PA3",
335 "PA4", "PA5", "PA6", "PA7",
336 "PA8", "PA10", "PA11", "PA12",
337 "PA13", "PA15", "PA16";
340 * data lines in RGMII mode use DDR mode
341 * and need a higher signal drive strength
343 drive-strength = <40>;
346 i2c0_pins: i2c0-pins {
351 mmc0_pins: mmc0-pins {
352 pins = "PF0", "PF1", "PF2",
355 drive-strength = <30>;
359 mmc1_pg_pins: mmc1-pg-pins {
360 pins = "PG0", "PG1", "PG2",
363 drive-strength = <30>;
367 mmc2_pins: mmc2-pins {
368 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
369 "PC10", "PC11", "PC12", "PC13", "PC14",
372 drive-strength = <30>;
376 uart0_pb_pins: uart0-pb-pins {
377 pins = "PB22", "PB23";
382 wdt: watchdog@1c20c90 {
383 compatible = "allwinner,sun4i-a10-wdt";
384 reg = <0x01c20c90 0x10>;
387 uart0: serial@1c28000 {
388 compatible = "snps,dw-apb-uart";
389 reg = <0x01c28000 0x400>;
390 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&ccu CLK_BUS_UART0>;
394 resets = <&ccu RST_BUS_UART0>;
398 uart1: serial@1c28400 {
399 compatible = "snps,dw-apb-uart";
400 reg = <0x01c28400 0x400>;
401 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&ccu CLK_BUS_UART1>;
405 resets = <&ccu RST_BUS_UART1>;
409 uart2: serial@1c28800 {
410 compatible = "snps,dw-apb-uart";
411 reg = <0x01c28800 0x400>;
412 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&ccu CLK_BUS_UART2>;
416 resets = <&ccu RST_BUS_UART2>;
420 uart3: serial@1c28c00 {
421 compatible = "snps,dw-apb-uart";
422 reg = <0x01c28c00 0x400>;
423 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&ccu CLK_BUS_UART3>;
427 resets = <&ccu RST_BUS_UART3>;
431 uart4: serial@1c29000 {
432 compatible = "snps,dw-apb-uart";
433 reg = <0x01c29000 0x400>;
434 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&ccu CLK_BUS_UART4>;
438 resets = <&ccu RST_BUS_UART4>;
442 uart5: serial@1c29400 {
443 compatible = "snps,dw-apb-uart";
444 reg = <0x01c29400 0x400>;
445 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&ccu CLK_BUS_UART5>;
449 resets = <&ccu RST_BUS_UART5>;
453 uart6: serial@1c29800 {
454 compatible = "snps,dw-apb-uart";
455 reg = <0x01c29800 0x400>;
456 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&ccu CLK_BUS_UART6>;
460 resets = <&ccu RST_BUS_UART6>;
464 uart7: serial@1c29c00 {
465 compatible = "snps,dw-apb-uart";
466 reg = <0x01c29c00 0x400>;
467 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&ccu CLK_BUS_UART7>;
471 resets = <&ccu RST_BUS_UART7>;
476 compatible = "allwinner,sun6i-a31-i2c";
477 reg = <0x01c2ac00 0x400>;
478 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&ccu CLK_BUS_I2C0>;
480 resets = <&ccu RST_BUS_I2C0>;
481 pinctrl-0 = <&i2c0_pins>;
482 pinctrl-names = "default";
484 #address-cells = <1>;
489 compatible = "allwinner,sun6i-a31-i2c";
490 reg = <0x01c2b000 0x400>;
491 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&ccu CLK_BUS_I2C1>;
493 resets = <&ccu RST_BUS_I2C1>;
495 #address-cells = <1>;
500 compatible = "allwinner,sun6i-a31-i2c";
501 reg = <0x01c2b400 0x400>;
502 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&ccu CLK_BUS_I2C2>;
504 resets = <&ccu RST_BUS_I2C2>;
506 #address-cells = <1>;
511 compatible = "allwinner,sun6i-a31-i2c";
512 reg = <0x01c2b800 0x400>;
513 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&ccu CLK_BUS_I2C3>;
515 resets = <&ccu RST_BUS_I2C3>;
517 #address-cells = <1>;
522 compatible = "allwinner,sun6i-a31-i2c";
523 reg = <0x01c2c000 0x400>;
524 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&ccu CLK_BUS_I2C4>;
526 resets = <&ccu RST_BUS_I2C4>;
528 #address-cells = <1>;
533 compatible = "allwinner,sun8i-r40-ahci";
534 reg = <0x01c18000 0x1000>;
535 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
537 resets = <&ccu RST_BUS_SATA>;
538 resets-name = "ahci";
539 #address-cells = <1>;
545 gmac: ethernet@1c50000 {
546 compatible = "allwinner,sun8i-r40-gmac";
548 reg = <0x01c50000 0x10000>;
549 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
550 interrupt-names = "macirq";
551 resets = <&ccu RST_BUS_GMAC>;
552 reset-names = "stmmaceth";
553 clocks = <&ccu CLK_BUS_GMAC>;
554 clock-names = "stmmaceth";
558 compatible = "snps,dwmac-mdio";
559 #address-cells = <1>;
564 tcon_top: tcon-top@1c70000 {
565 compatible = "allwinner,sun8i-r40-tcon-top";
566 reg = <0x01c70000 0x1000>;
567 clocks = <&ccu CLK_BUS_TCON_TOP>,
579 clock-output-names = "tcon-top-tv0",
582 resets = <&ccu RST_BUS_TCON_TOP>;
586 #address-cells = <1>;
589 tcon_top_mixer0_in: port@0 {
590 #address-cells = <1>;
594 tcon_top_mixer0_in_mixer0: endpoint@0 {
596 remote-endpoint = <&mixer0_out_tcon_top>;
600 tcon_top_mixer0_out: port@1 {
601 #address-cells = <1>;
605 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
609 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
613 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
615 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
618 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
620 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
624 tcon_top_mixer1_in: port@2 {
625 #address-cells = <1>;
629 tcon_top_mixer1_in_mixer1: endpoint@1 {
631 remote-endpoint = <&mixer1_out_tcon_top>;
635 tcon_top_mixer1_out: port@3 {
636 #address-cells = <1>;
640 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
644 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
648 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
650 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
653 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
655 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
659 tcon_top_hdmi_in: port@4 {
660 #address-cells = <1>;
664 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
666 remote-endpoint = <&tcon_tv0_out_tcon_top>;
669 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
671 remote-endpoint = <&tcon_tv1_out_tcon_top>;
675 tcon_top_hdmi_out: port@5 {
678 tcon_top_hdmi_out_hdmi: endpoint {
679 remote-endpoint = <&hdmi_in_tcon_top>;
685 tcon_tv0: lcd-controller@1c73000 {
686 compatible = "allwinner,sun8i-r40-tcon-tv";
687 reg = <0x01c73000 0x1000>;
688 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
690 clock-names = "ahb", "tcon-ch1";
691 resets = <&ccu RST_BUS_TCON_TV0>;
696 #address-cells = <1>;
699 tcon_tv0_in: port@0 {
700 #address-cells = <1>;
704 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
706 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
709 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
711 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
715 tcon_tv0_out: port@1 {
716 #address-cells = <1>;
720 tcon_tv0_out_tcon_top: endpoint@1 {
722 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
728 tcon_tv1: lcd-controller@1c74000 {
729 compatible = "allwinner,sun8i-r40-tcon-tv";
730 reg = <0x01c74000 0x1000>;
731 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
733 clock-names = "ahb", "tcon-ch1";
734 resets = <&ccu RST_BUS_TCON_TV1>;
739 #address-cells = <1>;
742 tcon_tv1_in: port@0 {
743 #address-cells = <1>;
747 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
749 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
752 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
754 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
758 tcon_tv1_out: port@1 {
759 #address-cells = <1>;
763 tcon_tv1_out_tcon_top: endpoint@1 {
765 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
771 gic: interrupt-controller@1c81000 {
772 compatible = "arm,gic-400";
773 reg = <0x01c81000 0x1000>,
777 interrupt-controller;
778 #interrupt-cells = <3>;
779 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
783 compatible = "allwinner,sun8i-r40-dw-hdmi",
784 "allwinner,sun8i-a83t-dw-hdmi";
785 reg = <0x01ee0000 0x10000>;
787 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
790 clock-names = "iahb", "isfr", "tmds";
791 resets = <&ccu RST_BUS_HDMI1>;
792 reset-names = "ctrl";
794 phy-names = "hdmi-phy";
798 #address-cells = <1>;
804 hdmi_in_tcon_top: endpoint {
805 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
815 hdmi_phy: hdmi-phy@1ef0000 {
816 compatible = "allwinner,sun8i-r40-hdmi-phy",
817 "allwinner,sun50i-a64-hdmi-phy";
818 reg = <0x01ef0000 0x10000>;
819 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
821 clock-names = "bus", "mod", "pll-0", "pll-1";
822 resets = <&ccu RST_BUS_HDMI0>;
829 compatible = "arm,armv7-timer";
830 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
831 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
832 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
833 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;