2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
50 interrupt-parent = <&gic>;
57 compatible = "arm,cortex-a7";
60 clocks = <&ccu CLK_CPU>;
65 compatible = "allwinner,sun8i-v3s-display-engine";
66 allwinner,pipelines = <&mixer0>;
71 compatible = "arm,armv7-timer";
72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
85 compatible = "fixed-clock";
86 clock-frequency = <24000000>;
87 clock-output-names = "osc24M";
92 compatible = "fixed-clock";
93 clock-frequency = <32768>;
94 clock-output-names = "osc32k";
99 compatible = "simple-bus";
100 #address-cells = <1>;
104 display_clocks: clock@1000000 {
105 compatible = "allwinner,sun8i-v3s-de2-clk";
106 reg = <0x01000000 0x100000>;
107 clocks = <&ccu CLK_DE>,
111 resets = <&ccu RST_BUS_DE>;
116 mixer0: mixer@1100000 {
117 compatible = "allwinner,sun8i-v3s-de2-mixer";
118 reg = <0x01100000 0x100000>;
119 clocks = <&display_clocks 0>,
123 resets = <&display_clocks 0>;
124 assigned-clocks = <&display_clocks 6>;
125 assigned-clock-rates = <150000000>;
128 #address-cells = <1>;
134 mixer0_out_tcon0: endpoint {
135 remote-endpoint = <&tcon0_in_mixer0>;
141 tcon0: lcd-controller@1c0c000 {
142 compatible = "allwinner,sun8i-v3s-tcon";
143 reg = <0x01c0c000 0x1000>;
144 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&ccu CLK_BUS_TCON0>,
149 clock-output-names = "tcon-pixel-clock";
151 resets = <&ccu RST_BUS_TCON0>;
156 #address-cells = <1>;
162 tcon0_in_mixer0: endpoint {
163 remote-endpoint = <&mixer0_out_tcon0>;
168 #address-cells = <1>;
177 compatible = "allwinner,sun7i-a20-mmc";
178 reg = <0x01c0f000 0x1000>;
179 clocks = <&ccu CLK_BUS_MMC0>,
181 <&ccu CLK_MMC0_OUTPUT>,
182 <&ccu CLK_MMC0_SAMPLE>;
187 resets = <&ccu RST_BUS_MMC0>;
189 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&mmc0_pins>;
193 #address-cells = <1>;
198 compatible = "allwinner,sun7i-a20-mmc";
199 reg = <0x01c10000 0x1000>;
200 clocks = <&ccu CLK_BUS_MMC1>,
202 <&ccu CLK_MMC1_OUTPUT>,
203 <&ccu CLK_MMC1_SAMPLE>;
208 resets = <&ccu RST_BUS_MMC1>;
210 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&mmc1_pins>;
214 #address-cells = <1>;
219 compatible = "allwinner,sun7i-a20-mmc";
220 reg = <0x01c11000 0x1000>;
221 clocks = <&ccu CLK_BUS_MMC2>,
223 <&ccu CLK_MMC2_OUTPUT>,
224 <&ccu CLK_MMC2_SAMPLE>;
229 resets = <&ccu RST_BUS_MMC2>;
231 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
233 #address-cells = <1>;
237 usb_otg: usb@1c19000 {
238 compatible = "allwinner,sun8i-h3-musb";
239 reg = <0x01c19000 0x0400>;
240 clocks = <&ccu CLK_BUS_OTG>;
241 resets = <&ccu RST_BUS_OTG>;
242 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-names = "mc";
246 extcon = <&usbphy 0>;
250 usbphy: phy@1c19400 {
251 compatible = "allwinner,sun8i-v3s-usb-phy";
252 reg = <0x01c19400 0x2c>,
254 reg-names = "phy_ctrl",
256 clocks = <&ccu CLK_USB_PHY0>;
257 clock-names = "usb0_phy";
258 resets = <&ccu RST_USB_PHY0>;
259 reset-names = "usb0_reset";
265 compatible = "allwinner,sun8i-v3s-ccu";
266 reg = <0x01c20000 0x400>;
267 clocks = <&osc24M>, <&osc32k>;
268 clock-names = "hosc", "losc";
274 compatible = "allwinner,sun6i-a31-rtc";
275 reg = <0x01c20400 0x54>;
276 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
280 pio: pinctrl@1c20800 {
281 compatible = "allwinner,sun8i-v3s-pinctrl";
282 reg = <0x01c20800 0x400>;
283 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
286 clock-names = "apb", "hosc", "losc";
289 interrupt-controller;
290 #interrupt-cells = <3>;
292 i2c0_pins: i2c0-pins {
297 uart0_pb_pins: uart0-pb-pins {
302 mmc0_pins: mmc0-pins {
303 pins = "PF0", "PF1", "PF2", "PF3",
306 drive-strength = <30>;
310 mmc1_pins: mmc1-pins {
311 pins = "PG0", "PG1", "PG2", "PG3",
314 drive-strength = <30>;
318 spi0_pins: spi0-pins {
319 pins = "PC0", "PC1", "PC2", "PC3";
325 compatible = "allwinner,sun4i-a10-timer";
326 reg = <0x01c20c00 0xa0>;
327 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
332 wdt0: watchdog@1c20ca0 {
333 compatible = "allwinner,sun6i-a31-wdt";
334 reg = <0x01c20ca0 0x20>;
335 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
338 lradc: lradc@1c22800 {
339 compatible = "allwinner,sun4i-a10-lradc-keys";
340 reg = <0x01c22800 0x400>;
341 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
345 uart0: serial@1c28000 {
346 compatible = "snps,dw-apb-uart";
347 reg = <0x01c28000 0x400>;
348 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&ccu CLK_BUS_UART0>;
352 resets = <&ccu RST_BUS_UART0>;
356 uart1: serial@1c28400 {
357 compatible = "snps,dw-apb-uart";
358 reg = <0x01c28400 0x400>;
359 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&ccu CLK_BUS_UART1>;
363 resets = <&ccu RST_BUS_UART1>;
367 uart2: serial@1c28800 {
368 compatible = "snps,dw-apb-uart";
369 reg = <0x01c28800 0x400>;
370 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&ccu CLK_BUS_UART2>;
374 resets = <&ccu RST_BUS_UART2>;
379 compatible = "allwinner,sun6i-a31-i2c";
380 reg = <0x01c2ac00 0x400>;
381 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&ccu CLK_BUS_I2C0>;
383 resets = <&ccu RST_BUS_I2C0>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&i2c0_pins>;
387 #address-cells = <1>;
392 compatible = "allwinner,sun6i-a31-i2c";
393 reg = <0x01c2b000 0x400>;
394 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&ccu CLK_BUS_I2C1>;
396 resets = <&ccu RST_BUS_I2C1>;
398 #address-cells = <1>;
403 compatible = "allwinner,sun8i-h3-spi";
404 reg = <0x01c68000 0x1000>;
405 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
407 clock-names = "ahb", "mod";
408 pinctrl-names = "default";
409 pinctrl-0 = <&spi0_pins>;
410 resets = <&ccu RST_BUS_SPI0>;
412 #address-cells = <1>;
416 gic: interrupt-controller@1c81000 {
417 compatible = "arm,gic-400";
418 reg = <0x01c81000 0x1000>,
422 interrupt-controller;
423 #interrupt-cells = <3>;
424 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;