2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton64.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 interrupt-parent = <&gic>;
59 compatible = "arm,cortex-a7";
65 compatible = "arm,cortex-a7";
71 compatible = "arm,cortex-a7";
77 compatible = "arm,cortex-a7";
83 compatible = "arm,cortex-a15";
89 compatible = "arm,cortex-a15";
95 compatible = "arm,cortex-a15";
101 compatible = "arm,cortex-a15";
108 /* 8GB max. with LPAE */
109 reg = <0 0x20000000 0x02 0>;
113 compatible = "arm,armv7-timer";
114 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
118 clock-frequency = <24000000>;
119 arm,cpu-registers-not-fw-configured;
123 #address-cells = <1>;
126 * map 64 bit address range down to 32 bits,
127 * as the peripherals are all under 512MB.
129 ranges = <0 0 0 0x20000000>;
132 * This clock is actually configurable from the PRCM address
133 * space. The external 24M oscillator can be turned off, and
134 * the clock switched to an internal 16M RC oscillator. Under
135 * normal operation there's no reason to do this, and the
136 * default is to use the external good one, so just model this
137 * as a fixed clock. Also it is not entirely clear if the
138 * osc24M mux in the PRCM affects the entire clock tree, which
139 * would also throw all the PLL clock rates off, or just the
140 * downstream clocks in the PRCM.
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "osc24M";
150 * The 32k clock is from an external source, normally the
151 * AC100 codec/RTC chip. This serves as a placeholder for
152 * board dts files to specify the source.
156 compatible = "fixed-factor-clock";
159 clock-output-names = "osc32k";
162 usb_mod_clk: clk@00a08000 {
165 compatible = "allwinner,sun9i-a80-usb-mod-clk";
166 reg = <0x00a08000 0x4>;
167 clocks = <&ahb1_gates 1>;
168 clock-output-names = "usb0_ahb", "usb_ohci0",
169 "usb1_ahb", "usb_ohci1",
170 "usb2_ahb", "usb_ohci2";
173 usb_phy_clk: clk@00a08004 {
176 compatible = "allwinner,sun9i-a80-usb-phy-clk";
177 reg = <0x00a08004 0x4>;
178 clocks = <&ahb1_gates 1>;
179 clock-output-names = "usb_phy0", "usb_hsic1_480M",
180 "usb_phy1", "usb_hsic2_480M",
181 "usb_phy2", "usb_hsic_12M";
185 /* placeholder until implemented */
187 compatible = "fixed-clock";
189 clock-output-names = "pll3";
194 compatible = "allwinner,sun9i-a80-pll4-clk";
195 reg = <0x0600000c 0x4>;
197 clock-output-names = "pll4";
200 pll12: clk@0600002c {
202 compatible = "allwinner,sun9i-a80-pll4-clk";
203 reg = <0x0600002c 0x4>;
205 clock-output-names = "pll12";
208 gt_clk: clk@0600005c {
210 compatible = "allwinner,sun9i-a80-gt-clk";
211 reg = <0x0600005c 0x4>;
212 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
213 clock-output-names = "gt";
218 compatible = "allwinner,sun9i-a80-ahb-clk";
219 reg = <0x06000060 0x4>;
220 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
221 clock-output-names = "ahb0";
226 compatible = "allwinner,sun9i-a80-ahb-clk";
227 reg = <0x06000064 0x4>;
228 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
229 clock-output-names = "ahb1";
234 compatible = "allwinner,sun9i-a80-ahb-clk";
235 reg = <0x06000068 0x4>;
236 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
237 clock-output-names = "ahb2";
242 compatible = "allwinner,sun9i-a80-apb0-clk";
243 reg = <0x06000070 0x4>;
244 clocks = <&osc24M>, <&pll4>;
245 clock-output-names = "apb0";
250 compatible = "allwinner,sun9i-a80-apb1-clk";
251 reg = <0x06000074 0x4>;
252 clocks = <&osc24M>, <&pll4>;
253 clock-output-names = "apb1";
256 cci400_clk: clk@06000078 {
258 compatible = "allwinner,sun9i-a80-gt-clk";
259 reg = <0x06000078 0x4>;
260 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
261 clock-output-names = "cci400";
264 mmc0_clk: clk@06000410 {
266 compatible = "allwinner,sun9i-a80-mmc-clk";
267 reg = <0x06000410 0x4>;
268 clocks = <&osc24M>, <&pll4>;
269 clock-output-names = "mmc0", "mmc0_output",
273 mmc1_clk: clk@06000414 {
275 compatible = "allwinner,sun9i-a80-mmc-clk";
276 reg = <0x06000414 0x4>;
277 clocks = <&osc24M>, <&pll4>;
278 clock-output-names = "mmc1", "mmc1_output",
282 mmc2_clk: clk@06000418 {
284 compatible = "allwinner,sun9i-a80-mmc-clk";
285 reg = <0x06000418 0x4>;
286 clocks = <&osc24M>, <&pll4>;
287 clock-output-names = "mmc2", "mmc2_output",
291 mmc3_clk: clk@0600041c {
293 compatible = "allwinner,sun9i-a80-mmc-clk";
294 reg = <0x0600041c 0x4>;
295 clocks = <&osc24M>, <&pll4>;
296 clock-output-names = "mmc3", "mmc3_output",
300 ahb0_gates: clk@06000580 {
302 compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
303 reg = <0x06000580 0x4>;
305 clock-indices = <0>, <1>, <3>,
311 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
312 "ahb0_ss", "ahb0_sd", "ahb0_nand1",
313 "ahb0_nand0", "ahb0_sdram",
314 "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
315 "ahb0_spi0", "ahb0_spi1", "ahb0_spi2",
319 ahb1_gates: clk@06000584 {
321 compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
322 reg = <0x06000584 0x4>;
324 clock-indices = <0>, <1>,
328 clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
329 "ahb1_gmac", "ahb1_msgbox",
330 "ahb1_spinlock", "ahb1_hstimer",
334 ahb2_gates: clk@06000588 {
336 compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
337 reg = <0x06000588 0x4>;
339 clock-indices = <0>, <1>,
342 clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
343 "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
344 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
347 apb0_gates: clk@06000590 {
349 compatible = "allwinner,sun9i-a80-apb0-gates-clk";
350 reg = <0x06000590 0x4>;
352 clock-indices = <1>, <5>,
356 clock-output-names = "apb0_spdif", "apb0_pio",
357 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
358 "apb0_lradc", "apb0_gpadc", "apb0_twd",
362 apb1_gates: clk@06000594 {
364 compatible = "allwinner,sun9i-a80-apb1-gates-clk";
365 reg = <0x06000594 0x4>;
367 clock-indices = <0>, <1>,
372 clock-output-names = "apb1_i2c0", "apb1_i2c1",
373 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
374 "apb1_uart0", "apb1_uart1",
375 "apb1_uart2", "apb1_uart3",
376 "apb1_uart4", "apb1_uart5";
379 cpus_clk: clk@08001410 {
380 compatible = "allwinner,sun9i-a80-cpus-clk";
381 reg = <0x08001410 0x4>;
383 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
384 clock-output-names = "cpus";
388 compatible = "fixed-factor-clock";
392 clocks = <&cpus_clk>;
393 clock-output-names = "ahbs";
397 compatible = "allwinner,sun8i-a23-apb0-clk";
398 reg = <0x0800141c 0x4>;
401 clock-output-names = "apbs";
404 apbs_gates: clk@08001428 {
405 compatible = "allwinner,sun9i-a80-apbs-gates-clk";
406 reg = <0x08001428 0x4>;
409 clock-indices = <0>, <1>,
416 clock-output-names = "apbs_pio", "apbs_ir",
417 "apbs_timer", "apbs_rsb",
418 "apbs_uart", "apbs_1wire",
419 "apbs_i2c0", "apbs_i2c1",
420 "apbs_ps2_0", "apbs_ps2_1",
421 "apbs_dma", "apbs_i2s0",
422 "apbs_i2s1", "apbs_twd";
425 r_1wire_clk: clk@08001450 {
426 reg = <0x08001450 0x4>;
428 compatible = "allwinner,sun4i-a10-mod0-clk";
429 clocks = <&osc32k>, <&osc24M>;
430 clock-output-names = "r_1wire";
433 r_ir_clk: clk@08001454 {
434 reg = <0x08001454 0x4>;
436 compatible = "allwinner,sun4i-a10-mod0-clk";
437 clocks = <&osc32k>, <&osc24M>;
438 clock-output-names = "r_ir";
443 compatible = "simple-bus";
444 #address-cells = <1>;
447 * map 64 bit address range down to 32 bits,
448 * as the peripherals are all under 512MB.
450 ranges = <0 0 0 0x20000000>;
452 ehci0: usb@00a00000 {
453 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
454 reg = <0x00a00000 0x100>;
455 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&usb_mod_clk 1>;
457 resets = <&usb_mod_clk 17>;
463 ohci0: usb@00a00400 {
464 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
465 reg = <0x00a00400 0x100>;
466 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
468 resets = <&usb_mod_clk 17>;
474 usbphy1: phy@00a00800 {
475 compatible = "allwinner,sun9i-a80-usb-phy";
476 reg = <0x00a00800 0x4>;
477 clocks = <&usb_phy_clk 1>;
479 resets = <&usb_phy_clk 17>;
485 ehci1: usb@00a01000 {
486 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
487 reg = <0x00a01000 0x100>;
488 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&usb_mod_clk 3>;
490 resets = <&usb_mod_clk 18>;
496 usbphy2: phy@00a01800 {
497 compatible = "allwinner,sun9i-a80-usb-phy";
498 reg = <0x00a01800 0x4>;
499 clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
501 clock-names = "hsic_480M", "hsic_12M", "phy";
502 resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
503 reset-names = "hsic", "phy";
506 /* usb1 is always used with HSIC */
510 ehci2: usb@00a02000 {
511 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
512 reg = <0x00a02000 0x100>;
513 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&usb_mod_clk 5>;
515 resets = <&usb_mod_clk 19>;
521 ohci2: usb@00a02400 {
522 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
523 reg = <0x00a02400 0x100>;
524 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
526 resets = <&usb_mod_clk 19>;
532 usbphy3: phy@00a02800 {
533 compatible = "allwinner,sun9i-a80-usb-phy";
534 reg = <0x00a02800 0x4>;
535 clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
537 clock-names = "hsic_480M", "hsic_12M", "phy";
538 resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
539 reset-names = "hsic", "phy";
545 compatible = "allwinner,sun9i-a80-mmc";
546 reg = <0x01c0f000 0x1000>;
547 clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
548 <&mmc0_clk 1>, <&mmc0_clk 2>;
549 clock-names = "ahb", "mmc", "output", "sample";
550 resets = <&mmc_config_clk 0>;
552 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <1>;
559 compatible = "allwinner,sun9i-a80-mmc";
560 reg = <0x01c10000 0x1000>;
561 clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
562 <&mmc1_clk 1>, <&mmc1_clk 2>;
563 clock-names = "ahb", "mmc", "output", "sample";
564 resets = <&mmc_config_clk 1>;
566 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
568 #address-cells = <1>;
573 compatible = "allwinner,sun9i-a80-mmc";
574 reg = <0x01c11000 0x1000>;
575 clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
576 <&mmc2_clk 1>, <&mmc2_clk 2>;
577 clock-names = "ahb", "mmc", "output", "sample";
578 resets = <&mmc_config_clk 2>;
580 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
582 #address-cells = <1>;
587 compatible = "allwinner,sun9i-a80-mmc";
588 reg = <0x01c12000 0x1000>;
589 clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
590 <&mmc3_clk 1>, <&mmc3_clk 2>;
591 clock-names = "ahb", "mmc", "output", "sample";
592 resets = <&mmc_config_clk 3>;
594 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
596 #address-cells = <1>;
600 mmc_config_clk: clk@01c13000 {
601 compatible = "allwinner,sun9i-a80-mmc-config-clk";
602 reg = <0x01c13000 0x10>;
603 clocks = <&ahb0_gates 8>;
605 resets = <&ahb0_resets 8>;
609 clock-output-names = "mmc0_config", "mmc1_config",
610 "mmc2_config", "mmc3_config";
613 gic: interrupt-controller@01c41000 {
614 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
615 reg = <0x01c41000 0x1000>,
619 interrupt-controller;
620 #interrupt-cells = <3>;
621 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
624 ahb0_resets: reset@060005a0 {
626 compatible = "allwinner,sun6i-a31-clock-reset";
627 reg = <0x060005a0 0x4>;
630 ahb1_resets: reset@060005a4 {
632 compatible = "allwinner,sun6i-a31-clock-reset";
633 reg = <0x060005a4 0x4>;
636 ahb2_resets: reset@060005a8 {
638 compatible = "allwinner,sun6i-a31-clock-reset";
639 reg = <0x060005a8 0x4>;
642 apb0_resets: reset@060005b0 {
644 compatible = "allwinner,sun6i-a31-clock-reset";
645 reg = <0x060005b0 0x4>;
648 apb1_resets: reset@060005b4 {
650 compatible = "allwinner,sun6i-a31-clock-reset";
651 reg = <0x060005b4 0x4>;
655 compatible = "allwinner,sun4i-a10-timer";
656 reg = <0x06000c00 0xa0>;
657 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
667 wdt: watchdog@06000ca0 {
668 compatible = "allwinner,sun6i-a31-wdt";
669 reg = <0x06000ca0 0x20>;
670 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
673 pio: pinctrl@06000800 {
674 compatible = "allwinner,sun9i-a80-pinctrl";
675 reg = <0x06000800 0x400>;
676 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
682 clock-names = "apb", "hosc", "losc";
684 interrupt-controller;
685 #interrupt-cells = <3>;
689 i2c3_pins_a: i2c3@0 {
690 pins = "PG10", "PG11";
695 pins = "PF0", "PF1" ,"PF2", "PF3",
698 drive-strength = <30>;
703 pins = "PG0", "PG1" ,"PG2", "PG3",
706 drive-strength = <30>;
710 mmc2_8bit_pins: mmc2_8bit {
711 pins = "PC6", "PC7", "PC8", "PC9",
712 "PC10", "PC11", "PC12",
713 "PC13", "PC14", "PC15",
716 drive-strength = <30>;
720 uart0_pins_a: uart0@0 {
721 pins = "PH12", "PH13";
725 uart4_pins_a: uart4@0 {
726 pins = "PG12", "PG13", "PG14", "PG15";
731 uart0: serial@07000000 {
732 compatible = "snps,dw-apb-uart";
733 reg = <0x07000000 0x400>;
734 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&apb1_gates 16>;
738 resets = <&apb1_resets 16>;
742 uart1: serial@07000400 {
743 compatible = "snps,dw-apb-uart";
744 reg = <0x07000400 0x400>;
745 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&apb1_gates 17>;
749 resets = <&apb1_resets 17>;
753 uart2: serial@07000800 {
754 compatible = "snps,dw-apb-uart";
755 reg = <0x07000800 0x400>;
756 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&apb1_gates 18>;
760 resets = <&apb1_resets 18>;
764 uart3: serial@07000c00 {
765 compatible = "snps,dw-apb-uart";
766 reg = <0x07000c00 0x400>;
767 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&apb1_gates 19>;
771 resets = <&apb1_resets 19>;
775 uart4: serial@07001000 {
776 compatible = "snps,dw-apb-uart";
777 reg = <0x07001000 0x400>;
778 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&apb1_gates 20>;
782 resets = <&apb1_resets 20>;
786 uart5: serial@07001400 {
787 compatible = "snps,dw-apb-uart";
788 reg = <0x07001400 0x400>;
789 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&apb1_gates 21>;
793 resets = <&apb1_resets 21>;
798 compatible = "allwinner,sun6i-a31-i2c";
799 reg = <0x07002800 0x400>;
800 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&apb1_gates 0>;
802 resets = <&apb1_resets 0>;
804 #address-cells = <1>;
809 compatible = "allwinner,sun6i-a31-i2c";
810 reg = <0x07002c00 0x400>;
811 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&apb1_gates 1>;
813 resets = <&apb1_resets 1>;
815 #address-cells = <1>;
820 compatible = "allwinner,sun6i-a31-i2c";
821 reg = <0x07003000 0x400>;
822 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&apb1_gates 2>;
824 resets = <&apb1_resets 2>;
826 #address-cells = <1>;
831 compatible = "allwinner,sun6i-a31-i2c";
832 reg = <0x07003400 0x400>;
833 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&apb1_gates 3>;
835 resets = <&apb1_resets 3>;
837 #address-cells = <1>;
842 compatible = "allwinner,sun6i-a31-i2c";
843 reg = <0x07003800 0x400>;
844 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&apb1_gates 4>;
846 resets = <&apb1_resets 4>;
848 #address-cells = <1>;
852 r_wdt: watchdog@08001000 {
853 compatible = "allwinner,sun6i-a31-wdt";
854 reg = <0x08001000 0x20>;
855 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
858 apbs_rst: reset@080014b0 {
859 reg = <0x080014b0 0x4>;
860 compatible = "allwinner,sun6i-a31-clock-reset";
864 nmi_intc: interrupt-controller@080015a0 {
865 compatible = "allwinner,sun9i-a80-nmi";
866 interrupt-controller;
867 #interrupt-cells = <2>;
868 reg = <0x080015a0 0xc>;
869 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
873 compatible = "allwinner,sun5i-a13-ir";
874 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
875 pinctrl-names = "default";
876 pinctrl-0 = <&r_ir_pins>;
877 clocks = <&apbs_gates 1>, <&r_ir_clk>;
878 clock-names = "apb", "ir";
879 resets = <&apbs_rst 1>;
880 reg = <0x08002000 0x40>;
884 r_uart: serial@08002800 {
885 compatible = "snps,dw-apb-uart";
886 reg = <0x08002800 0x400>;
887 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&apbs_gates 4>;
891 resets = <&apbs_rst 4>;
895 r_pio: pinctrl@08002c00 {
896 compatible = "allwinner,sun9i-a80-r-pinctrl";
897 reg = <0x08002c00 0x400>;
898 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
901 clock-names = "apb", "hosc", "losc";
902 resets = <&apbs_rst 0>;
904 interrupt-controller;
905 #interrupt-cells = <3>;
910 function = "s_cir_rx";
916 drive-strength = <20>;
921 r_rsb: i2c@08003400 {
922 compatible = "allwinner,sun8i-a23-rsb";
923 reg = <0x08003400 0x400>;
924 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&apbs_gates 3>;
926 clock-frequency = <3000000>;
927 resets = <&apbs_rst 3>;
928 pinctrl-names = "default";
929 pinctrl-0 = <&r_rsb_pins>;
931 #address-cells = <1>;