arch/arm/boot/dts/tango4-common.dtsi

   1 /*
   2  * Based on Mans Rullgard's Tango3 DT
   3  * https://github.com/mansr/linux-tangox
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7
   8 #define  CPU_CLK        0
   9 #define  SYS_CLK        1
  10 #define  USB_CLK        2
  11 #define SDIO_CLK        3
  12
  13 / {
  14         interrupt-parent = <&gic>;
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         periph_clk: periph_clk {
  19                 compatible = "fixed-factor-clock";
  20                 clocks = <&clkgen CPU_CLK>;
  21                 clock-mult = <1>;
  22                 clock-div  = <2>;
  23                 #clock-cells = <0>;
  24         };
  25
  26         mpcore {
  27                 compatible = "simple-bus";
  28                 ranges = <0x00000000 0x20000000 0x2000>;
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31
  32                 scu@0 {
  33                         compatible = "arm,cortex-a9-scu";
  34                         reg = <0x0 0x100>;
  35                 };
  36
  37                 twd@600 {
  38                         compatible = "arm,cortex-a9-twd-timer";
  39                         reg = <0x600 0x10>;
  40                         interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
  41                         clocks = <&periph_clk>;
  42                         always-on;
  43                 };
  44
  45                 gic: interrupt-controller@1000 {
  46                         compatible = "arm,cortex-a9-gic";
  47                         #interrupt-cells = <3>;
  48                         interrupt-controller;
  49                         reg = <0x1000 0x1000>, <0x100 0x100>;
  50                 };
  51         };
  52
  53         l2cc: l2-cache-controller@20100000 {
  54                 compatible = "arm,pl310-cache";
  55                 reg = <0x20100000 0x1000>;
  56                 cache-level = <2>;
  57                 cache-unified;
  58         };
  59
  60         soc {
  61                 compatible = "simple-bus";
  62                 interrupt-parent = <&irq0>;
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 ranges;
  66
  67                 xtal: xtal {
  68                         compatible = "fixed-clock";
  69                         clock-frequency = <27000000>;
  70                         #clock-cells = <0>;
  71                 };
  72
  73                 clkgen: clkgen@10000 {
  74                         compatible = "sigma,tango4-clkgen";
  75                         reg = <0x10000 0x100>;
  76                         clocks = <&xtal>;
  77                         #clock-cells = <1>;
  78                 };
  79
  80                 tick-counter@10048 {
  81                         compatible = "sigma,tick-counter";
  82                         reg = <0x10048 0x4>;
  83                         clocks = <&xtal>;
  84                 };
  85
  86                 uart: serial@10700 {
  87                         compatible = "ralink,rt2880-uart";
  88                         reg = <0x10700 0x30>;
  89                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
  90                         clock-frequency = <7372800>;
  91                         reg-shift = <2>;
  92                 };
  93
  94                 watchdog@1fd00 {
  95                         compatible = "sigma,smp8759-wdt";
  96                         reg = <0x1fd00 8>;
  97                         clocks = <&xtal>;
  98                 };
  99
 100                 eth0: ethernet@26000 {
 101                         compatible = "sigma,smp8734-ethernet";
 102                         reg = <0x26000 0x800>;
 103                         interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
 104                         clocks = <&clkgen SYS_CLK>;
 105                 };
 106
 107                 intc: interrupt-controller@6e000 {
 108                         compatible = "sigma,smp8642-intc";
 109                         reg = <0x6e000 0x400>;
 110                         ranges = <0 0x6e000 0x400>;
 111                         interrupt-parent = <&gic>;
 112                         interrupt-controller;
 113                         #address-cells = <1>;
 114                         #size-cells = <1>;
 115
 116                         irq0: irq0@000 {
 117                                 reg = <0x000 0x100>;
 118                                 interrupt-controller;
 119                                 #interrupt-cells = <2>;
 120                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 121                         };
 122
 123                         irq1: irq1@100 {
 124                                 reg = <0x100 0x100>;
 125                                 interrupt-controller;
 126                                 #interrupt-cells = <2>;
 127                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 128                         };
 129
 130                         irq2: irq2@300 {
 131                                 reg = <0x300 0x100>;
 132                                 interrupt-controller;
 133                                 #interrupt-cells = <2>;
 134                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 135                         };
 136                 };
 137         };
 138 };