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Merge tag 'omap-for-v5.1/dt-cpsw-phy' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / tegra124-apalis-v1.2.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright 2016-2018 Toradex AG
4 */
5
6 #include "tegra124.dtsi"
7 #include "tegra124-apalis-emc.dtsi"
8
9 /*
10 * Toradex Apalis TK1 Module Device Tree
11 * Compatible for Revisions 2GB: V1.2A
12 */
13 / {
14 memory@80000000 {
15 reg = <0x0 0x80000000 0x0 0x80000000>;
16 };
17
18 pcie@1003000 {
19 status = "okay";
20 avddio-pex-supply = <&reg_1v05_vdd>;
21 avdd-pex-pll-supply = <&reg_1v05_vdd>;
22 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
23 dvddio-pex-supply = <&reg_1v05_vdd>;
24 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
25 hvdd-pex-supply = <&reg_module_3v3>;
26 vddio-pex-ctl-supply = <&reg_module_3v3>;
27
28 /* Apalis PCIe (additional lane Apalis type specific) */
29 pci@1,0 {
30 /* PCIE1_RX/TX and TS_DIFF1/2 */
31 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
32 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
33 phy-names = "pcie-0", "pcie-1";
34 };
35
36 /* I210 Gigabit Ethernet Controller (On-module) */
37 pci@2,0 {
38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
39 phy-names = "pcie-0";
40 status = "okay";
41
42 pcie@0 {
43 reg = <0 0 0 0 0>;
44 local-mac-address = [00 00 00 00 00 00];
45 };
46 };
47 };
48
49 host1x@50000000 {
50 hdmi@54280000 {
51 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
52 nvidia,hpd-gpio =
53 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
54 pll-supply = <&reg_1v05_avdd_hdmi_pll>;
55 vdd-supply = <&reg_3v3_avdd_hdmi>;
56 };
57 };
58
59 gpu@0,57000000 {
60 /*
61 * Node left disabled on purpose - the bootloader will enable
62 * it after having set the VPR up
63 */
64 vdd-supply = <&reg_vdd_gpu>;
65 };
66
67 pinmux@70000868 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&state_default>;
70
71 state_default: pinmux {
72 /* Analogue Audio (On-module) */
73 dap3-fs-pp0 {
74 nvidia,pins = "dap3_fs_pp0";
75 nvidia,function = "i2s2";
76 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77 nvidia,tristate = <TEGRA_PIN_DISABLE>;
78 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
79 };
80 dap3-din-pp1 {
81 nvidia,pins = "dap3_din_pp1";
82 nvidia,function = "i2s2";
83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84 nvidia,tristate = <TEGRA_PIN_ENABLE>;
85 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
86 };
87 dap3-dout-pp2 {
88 nvidia,pins = "dap3_dout_pp2";
89 nvidia,function = "i2s2";
90 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
91 nvidia,tristate = <TEGRA_PIN_DISABLE>;
92 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
93 };
94 dap3-sclk-pp3 {
95 nvidia,pins = "dap3_sclk_pp3";
96 nvidia,function = "i2s2";
97 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
98 nvidia,tristate = <TEGRA_PIN_DISABLE>;
99 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
100 };
101 dap-mclk1-pw4 {
102 nvidia,pins = "dap_mclk1_pw4";
103 nvidia,function = "extperiph1";
104 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
105 nvidia,tristate = <TEGRA_PIN_DISABLE>;
106 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
107 };
108
109 /* Apalis BKL1_ON */
110 pbb5 {
111 nvidia,pins = "pbb5";
112 nvidia,function = "vgp5";
113 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114 nvidia,tristate = <TEGRA_PIN_DISABLE>;
115 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
116 };
117
118 /* Apalis BKL1_PWM */
119 pu6 {
120 nvidia,pins = "pu6";
121 nvidia,function = "pwm3";
122 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
123 nvidia,tristate = <TEGRA_PIN_DISABLE>;
124 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
125 };
126
127 /* Apalis CAM1_MCLK */
128 cam-mclk-pcc0 {
129 nvidia,pins = "cam_mclk_pcc0";
130 nvidia,function = "vi_alt3";
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
134 };
135
136 /* Apalis Digital Audio */
137 dap2-fs-pa2 {
138 nvidia,pins = "dap2_fs_pa2";
139 nvidia,function = "hda";
140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
142 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143 };
144 dap2-sclk-pa3 {
145 nvidia,pins = "dap2_sclk_pa3";
146 nvidia,function = "hda";
147 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
148 nvidia,tristate = <TEGRA_PIN_DISABLE>;
149 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
150 };
151 dap2-din-pa4 {
152 nvidia,pins = "dap2_din_pa4";
153 nvidia,function = "hda";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_ENABLE>;
156 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
157 };
158 dap2-dout-pa5 {
159 nvidia,pins = "dap2_dout_pa5";
160 nvidia,function = "hda";
161 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
162 nvidia,tristate = <TEGRA_PIN_DISABLE>;
163 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
164 };
165 pbb3 { /* DAP1_RESET */
166 nvidia,pins = "pbb3";
167 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
170 };
171 clk3-out-pee0 {
172 nvidia,pins = "clk3_out_pee0";
173 nvidia,function = "extperiph3";
174 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
175 nvidia,tristate = <TEGRA_PIN_DISABLE>;
176 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
177 };
178
179 /* Apalis GPIO */
180 usb-vbus-en0-pn4 {
181 nvidia,pins = "usb_vbus_en0_pn4";
182 nvidia,function = "rsvd2";
183 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
184 nvidia,tristate = <TEGRA_PIN_DISABLE>;
185 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
186 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
187 };
188 usb-vbus-en1-pn5 {
189 nvidia,pins = "usb_vbus_en1_pn5";
190 nvidia,function = "rsvd2";
191 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
192 nvidia,tristate = <TEGRA_PIN_DISABLE>;
193 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
194 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
195 };
196 pex-l0-rst-n-pdd1 {
197 nvidia,pins = "pex_l0_rst_n_pdd1";
198 nvidia,function = "rsvd2";
199 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
200 nvidia,tristate = <TEGRA_PIN_DISABLE>;
201 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
202 };
203 pex-l0-clkreq-n-pdd2 {
204 nvidia,pins = "pex_l0_clkreq_n_pdd2";
205 nvidia,function = "rsvd2";
206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209 };
210 pex-l1-rst-n-pdd5 {
211 nvidia,pins = "pex_l1_rst_n_pdd5";
212 nvidia,function = "rsvd2";
213 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
214 nvidia,tristate = <TEGRA_PIN_DISABLE>;
215 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
216 };
217 pex-l1-clkreq-n-pdd6 {
218 nvidia,pins = "pex_l1_clkreq_n_pdd6";
219 nvidia,function = "rsvd2";
220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
221 nvidia,tristate = <TEGRA_PIN_DISABLE>;
222 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
223 };
224 dp-hpd-pff0 {
225 nvidia,pins = "dp_hpd_pff0";
226 nvidia,function = "dp";
227 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
228 nvidia,tristate = <TEGRA_PIN_DISABLE>;
229 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
230 };
231 pff2 {
232 nvidia,pins = "pff2";
233 nvidia,function = "rsvd2";
234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
235 nvidia,tristate = <TEGRA_PIN_DISABLE>;
236 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
237 };
238 owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
239 nvidia,pins = "owr";
240 nvidia,function = "rsvd2";
241 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
242 nvidia,tristate = <TEGRA_PIN_ENABLE>;
243 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
244 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
245 };
246
247 /* Apalis HDMI1_CEC */
248 hdmi-cec-pee3 {
249 nvidia,pins = "hdmi_cec_pee3";
250 nvidia,function = "cec";
251 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
252 nvidia,tristate = <TEGRA_PIN_DISABLE>;
253 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
254 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
255 };
256
257 /* Apalis HDMI1_HPD */
258 hdmi-int-pn7 {
259 nvidia,pins = "hdmi_int_pn7";
260 nvidia,function = "rsvd1";
261 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
262 nvidia,tristate = <TEGRA_PIN_ENABLE>;
263 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
264 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
265 };
266
267 /* Apalis I2C1 */
268 gen1-i2c-scl-pc4 {
269 nvidia,pins = "gen1_i2c_scl_pc4";
270 nvidia,function = "i2c1";
271 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
272 nvidia,tristate = <TEGRA_PIN_DISABLE>;
273 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
274 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
275 };
276 gen1-i2c-sda-pc5 {
277 nvidia,pins = "gen1_i2c_sda_pc5";
278 nvidia,function = "i2c1";
279 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
280 nvidia,tristate = <TEGRA_PIN_DISABLE>;
281 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
282 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
283 };
284
285 /* Apalis I2C3 (CAM) */
286 cam-i2c-scl-pbb1 {
287 nvidia,pins = "cam_i2c_scl_pbb1";
288 nvidia,function = "i2c3";
289 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
290 nvidia,tristate = <TEGRA_PIN_DISABLE>;
291 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
292 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
293 };
294 cam-i2c-sda-pbb2 {
295 nvidia,pins = "cam_i2c_sda_pbb2";
296 nvidia,function = "i2c3";
297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298 nvidia,tristate = <TEGRA_PIN_DISABLE>;
299 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
300 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
301 };
302
303 /* Apalis I2C4 (DDC) */
304 ddc-scl-pv4 {
305 nvidia,pins = "ddc_scl_pv4";
306 nvidia,function = "i2c4";
307 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
308 nvidia,tristate = <TEGRA_PIN_DISABLE>;
309 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
310 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
311 };
312 ddc-sda-pv5 {
313 nvidia,pins = "ddc_sda_pv5";
314 nvidia,function = "i2c4";
315 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316 nvidia,tristate = <TEGRA_PIN_DISABLE>;
317 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
318 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
319 };
320
321 /* Apalis MMC1 */
322 sdmmc1-cd-n-pv3 { /* CD# GPIO */
323 nvidia,pins = "sdmmc1_wp_n_pv3";
324 nvidia,function = "sdmmc1";
325 nvidia,pull = <TEGRA_PIN_PULL_UP>;
326 nvidia,tristate = <TEGRA_PIN_ENABLE>;
327 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
328 };
329 clk2-out-pw5 { /* D5 GPIO */
330 nvidia,pins = "clk2_out_pw5";
331 nvidia,function = "rsvd2";
332 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
333 nvidia,tristate = <TEGRA_PIN_DISABLE>;
334 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
335 };
336 sdmmc1-dat3-py4 {
337 nvidia,pins = "sdmmc1_dat3_py4";
338 nvidia,function = "sdmmc1";
339 nvidia,pull = <TEGRA_PIN_PULL_UP>;
340 nvidia,tristate = <TEGRA_PIN_DISABLE>;
341 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
342 };
343 sdmmc1-dat2-py5 {
344 nvidia,pins = "sdmmc1_dat2_py5";
345 nvidia,function = "sdmmc1";
346 nvidia,pull = <TEGRA_PIN_PULL_UP>;
347 nvidia,tristate = <TEGRA_PIN_DISABLE>;
348 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
349 };
350 sdmmc1-dat1-py6 {
351 nvidia,pins = "sdmmc1_dat1_py6";
352 nvidia,function = "sdmmc1";
353 nvidia,pull = <TEGRA_PIN_PULL_UP>;
354 nvidia,tristate = <TEGRA_PIN_DISABLE>;
355 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
356 };
357 sdmmc1-dat0-py7 {
358 nvidia,pins = "sdmmc1_dat0_py7";
359 nvidia,function = "sdmmc1";
360 nvidia,pull = <TEGRA_PIN_PULL_UP>;
361 nvidia,tristate = <TEGRA_PIN_DISABLE>;
362 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
363 };
364 sdmmc1-clk-pz0 {
365 nvidia,pins = "sdmmc1_clk_pz0";
366 nvidia,function = "sdmmc1";
367 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
368 nvidia,tristate = <TEGRA_PIN_DISABLE>;
369 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
370 };
371 sdmmc1-cmd-pz1 {
372 nvidia,pins = "sdmmc1_cmd_pz1";
373 nvidia,function = "sdmmc1";
374 nvidia,pull = <TEGRA_PIN_PULL_UP>;
375 nvidia,tristate = <TEGRA_PIN_DISABLE>;
376 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
377 };
378 clk2-req-pcc5 { /* D4 GPIO */
379 nvidia,pins = "clk2_req_pcc5";
380 nvidia,function = "rsvd2";
381 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
382 nvidia,tristate = <TEGRA_PIN_DISABLE>;
383 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
384 };
385 sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
386 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
387 nvidia,function = "rsvd2";
388 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
389 nvidia,tristate = <TEGRA_PIN_DISABLE>;
390 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
391 };
392 usb-vbus-en2-pff1 { /* D7 GPIO */
393 nvidia,pins = "usb_vbus_en2_pff1";
394 nvidia,function = "rsvd2";
395 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
396 nvidia,tristate = <TEGRA_PIN_DISABLE>;
397 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
398 };
399
400 /* Apalis PWM */
401 ph0 {
402 nvidia,pins = "ph0";
403 nvidia,function = "pwm0";
404 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
405 nvidia,tristate = <TEGRA_PIN_DISABLE>;
406 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
407 };
408 ph1 {
409 nvidia,pins = "ph1";
410 nvidia,function = "pwm1";
411 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412 nvidia,tristate = <TEGRA_PIN_DISABLE>;
413 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
414 };
415 ph2 {
416 nvidia,pins = "ph2";
417 nvidia,function = "pwm2";
418 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
419 nvidia,tristate = <TEGRA_PIN_DISABLE>;
420 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
421 };
422 /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
423 ph3 {
424 nvidia,pins = "ph3";
425 nvidia,function = "pwm3";
426 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
427 nvidia,tristate = <TEGRA_PIN_DISABLE>;
428 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
429 };
430
431 /* Apalis SATA1_ACT# */
432 dap1-dout-pn2 {
433 nvidia,pins = "dap1_dout_pn2";
434 nvidia,function = "gmi";
435 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
436 nvidia,tristate = <TEGRA_PIN_DISABLE>;
437 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
438 };
439
440 /* Apalis SD1 */
441 sdmmc3-clk-pa6 {
442 nvidia,pins = "sdmmc3_clk_pa6";
443 nvidia,function = "sdmmc3";
444 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
445 nvidia,tristate = <TEGRA_PIN_DISABLE>;
446 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
447 };
448 sdmmc3-cmd-pa7 {
449 nvidia,pins = "sdmmc3_cmd_pa7";
450 nvidia,function = "sdmmc3";
451 nvidia,pull = <TEGRA_PIN_PULL_UP>;
452 nvidia,tristate = <TEGRA_PIN_DISABLE>;
453 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
454 };
455 sdmmc3-dat3-pb4 {
456 nvidia,pins = "sdmmc3_dat3_pb4";
457 nvidia,function = "sdmmc3";
458 nvidia,pull = <TEGRA_PIN_PULL_UP>;
459 nvidia,tristate = <TEGRA_PIN_DISABLE>;
460 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
461 };
462 sdmmc3-dat2-pb5 {
463 nvidia,pins = "sdmmc3_dat2_pb5";
464 nvidia,function = "sdmmc3";
465 nvidia,pull = <TEGRA_PIN_PULL_UP>;
466 nvidia,tristate = <TEGRA_PIN_DISABLE>;
467 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
468 };
469 sdmmc3-dat1-pb6 {
470 nvidia,pins = "sdmmc3_dat1_pb6";
471 nvidia,function = "sdmmc3";
472 nvidia,pull = <TEGRA_PIN_PULL_UP>;
473 nvidia,tristate = <TEGRA_PIN_DISABLE>;
474 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
475 };
476 sdmmc3-dat0-pb7 {
477 nvidia,pins = "sdmmc3_dat0_pb7";
478 nvidia,function = "sdmmc3";
479 nvidia,pull = <TEGRA_PIN_PULL_UP>;
480 nvidia,tristate = <TEGRA_PIN_DISABLE>;
481 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
482 };
483 sdmmc3-cd-n-pv2 { /* CD# GPIO */
484 nvidia,pins = "sdmmc3_cd_n_pv2";
485 nvidia,function = "rsvd3";
486 nvidia,pull = <TEGRA_PIN_PULL_UP>;
487 nvidia,tristate = <TEGRA_PIN_ENABLE>;
488 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
489 };
490
491 /* Apalis SPDIF */
492 spdif-out-pk5 {
493 nvidia,pins = "spdif_out_pk5";
494 nvidia,function = "spdif";
495 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
496 nvidia,tristate = <TEGRA_PIN_DISABLE>;
497 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
498 };
499 spdif-in-pk6 {
500 nvidia,pins = "spdif_in_pk6";
501 nvidia,function = "spdif";
502 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
503 nvidia,tristate = <TEGRA_PIN_ENABLE>;
504 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
505 };
506
507 /* Apalis SPI1 */
508 ulpi-clk-py0 {
509 nvidia,pins = "ulpi_clk_py0";
510 nvidia,function = "spi1";
511 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
512 nvidia,tristate = <TEGRA_PIN_DISABLE>;
513 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
514 };
515 ulpi-dir-py1 {
516 nvidia,pins = "ulpi_dir_py1";
517 nvidia,function = "spi1";
518 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
519 nvidia,tristate = <TEGRA_PIN_ENABLE>;
520 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
521 };
522 ulpi-nxt-py2 {
523 nvidia,pins = "ulpi_nxt_py2";
524 nvidia,function = "spi1";
525 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
526 nvidia,tristate = <TEGRA_PIN_DISABLE>;
527 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
528 };
529 ulpi-stp-py3 {
530 nvidia,pins = "ulpi_stp_py3";
531 nvidia,function = "spi1";
532 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
533 nvidia,tristate = <TEGRA_PIN_DISABLE>;
534 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
535 };
536
537 /* Apalis SPI2 */
538 pg5 {
539 nvidia,pins = "pg5";
540 nvidia,function = "spi4";
541 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
542 nvidia,tristate = <TEGRA_PIN_DISABLE>;
543 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
544 };
545 pg6 {
546 nvidia,pins = "pg6";
547 nvidia,function = "spi4";
548 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
549 nvidia,tristate = <TEGRA_PIN_DISABLE>;
550 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
551 };
552 pg7 {
553 nvidia,pins = "pg7";
554 nvidia,function = "spi4";
555 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
556 nvidia,tristate = <TEGRA_PIN_ENABLE>;
557 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
558 };
559 pi3 {
560 nvidia,pins = "pi3";
561 nvidia,function = "spi4";
562 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
563 nvidia,tristate = <TEGRA_PIN_DISABLE>;
564 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
565 };
566
567 /* Apalis UART1 */
568 pb1 { /* DCD GPIO */
569 nvidia,pins = "pb1";
570 nvidia,function = "rsvd2";
571 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
572 nvidia,tristate = <TEGRA_PIN_ENABLE>;
573 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
574 };
575 pk7 { /* RI GPIO */
576 nvidia,pins = "pk7";
577 nvidia,function = "rsvd2";
578 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
579 nvidia,tristate = <TEGRA_PIN_ENABLE>;
580 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
581 };
582 uart1-txd-pu0 {
583 nvidia,pins = "pu0";
584 nvidia,function = "uarta";
585 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
586 nvidia,tristate = <TEGRA_PIN_DISABLE>;
587 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
588 };
589 uart1-rxd-pu1 {
590 nvidia,pins = "pu1";
591 nvidia,function = "uarta";
592 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
593 nvidia,tristate = <TEGRA_PIN_ENABLE>;
594 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
595 };
596 uart1-cts-n-pu2 {
597 nvidia,pins = "pu2";
598 nvidia,function = "uarta";
599 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
600 nvidia,tristate = <TEGRA_PIN_ENABLE>;
601 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
602 };
603 uart1-rts-n-pu3 {
604 nvidia,pins = "pu3";
605 nvidia,function = "uarta";
606 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
607 nvidia,tristate = <TEGRA_PIN_DISABLE>;
608 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
609 };
610 uart3-cts-n-pa1 { /* DSR GPIO */
611 nvidia,pins = "uart3_cts_n_pa1";
612 nvidia,function = "gmi";
613 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
614 nvidia,tristate = <TEGRA_PIN_ENABLE>;
615 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
616 };
617 uart3-rts-n-pc0 { /* DTR GPIO */
618 nvidia,pins = "uart3_rts_n_pc0";
619 nvidia,function = "gmi";
620 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
621 nvidia,tristate = <TEGRA_PIN_DISABLE>;
622 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
623 };
624
625 /* Apalis UART2 */
626 uart2-txd-pc2 {
627 nvidia,pins = "uart2_txd_pc2";
628 nvidia,function = "irda";
629 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
630 nvidia,tristate = <TEGRA_PIN_DISABLE>;
631 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
632 };
633 uart2-rxd-pc3 {
634 nvidia,pins = "uart2_rxd_pc3";
635 nvidia,function = "irda";
636 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
637 nvidia,tristate = <TEGRA_PIN_ENABLE>;
638 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
639 };
640 uart2-cts-n-pj5 {
641 nvidia,pins = "uart2_cts_n_pj5";
642 nvidia,function = "uartb";
643 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
644 nvidia,tristate = <TEGRA_PIN_ENABLE>;
645 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
646 };
647 uart2-rts-n-pj6 {
648 nvidia,pins = "uart2_rts_n_pj6";
649 nvidia,function = "uartb";
650 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
651 nvidia,tristate = <TEGRA_PIN_DISABLE>;
652 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
653 };
654
655 /* Apalis UART3 */
656 uart3-txd-pw6 {
657 nvidia,pins = "uart3_txd_pw6";
658 nvidia,function = "uartc";
659 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
660 nvidia,tristate = <TEGRA_PIN_DISABLE>;
661 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
662 };
663 uart3-rxd-pw7 {
664 nvidia,pins = "uart3_rxd_pw7";
665 nvidia,function = "uartc";
666 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
667 nvidia,tristate = <TEGRA_PIN_ENABLE>;
668 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
669 };
670
671 /* Apalis UART4 */
672 uart4-rxd-pb0 {
673 nvidia,pins = "pb0";
674 nvidia,function = "uartd";
675 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
676 nvidia,tristate = <TEGRA_PIN_ENABLE>;
677 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
678 };
679 uart4-txd-pj7 {
680 nvidia,pins = "pj7";
681 nvidia,function = "uartd";
682 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
683 nvidia,tristate = <TEGRA_PIN_DISABLE>;
684 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
685 };
686
687 /* Apalis USBH_EN */
688 gen2-i2c-sda-pt6 {
689 nvidia,pins = "gen2_i2c_sda_pt6";
690 nvidia,function = "rsvd2";
691 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
692 nvidia,tristate = <TEGRA_PIN_DISABLE>;
693 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
694 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
695 };
696
697 /* Apalis USBH_OC# */
698 pbb0 {
699 nvidia,pins = "pbb0";
700 nvidia,function = "vgp6";
701 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
702 nvidia,tristate = <TEGRA_PIN_ENABLE>;
703 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
704 };
705
706 /* Apalis USBO1_EN */
707 gen2-i2c-scl-pt5 {
708 nvidia,pins = "gen2_i2c_scl_pt5";
709 nvidia,function = "rsvd2";
710 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
711 nvidia,tristate = <TEGRA_PIN_DISABLE>;
712 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
713 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
714 };
715
716 /* Apalis USBO1_OC# */
717 pbb4 {
718 nvidia,pins = "pbb4";
719 nvidia,function = "vgp4";
720 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
721 nvidia,tristate = <TEGRA_PIN_ENABLE>;
722 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
723 };
724
725 /* Apalis WAKE1_MICO */
726 pex-wake-n-pdd3 {
727 nvidia,pins = "pex_wake_n_pdd3";
728 nvidia,function = "rsvd2";
729 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
730 nvidia,tristate = <TEGRA_PIN_ENABLE>;
731 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
732 };
733
734 /* CORE_PWR_REQ */
735 core-pwr-req {
736 nvidia,pins = "core_pwr_req";
737 nvidia,function = "pwron";
738 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
739 nvidia,tristate = <TEGRA_PIN_DISABLE>;
740 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
741 };
742
743 /* CPU_PWR_REQ */
744 cpu-pwr-req {
745 nvidia,pins = "cpu_pwr_req";
746 nvidia,function = "cpu";
747 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
748 nvidia,tristate = <TEGRA_PIN_DISABLE>;
749 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
750 };
751
752 /* DVFS */
753 dvfs-pwm-px0 {
754 nvidia,pins = "dvfs_pwm_px0";
755 nvidia,function = "cldvfs";
756 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
757 nvidia,tristate = <TEGRA_PIN_DISABLE>;
758 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
759 };
760 dvfs-clk-px2 {
761 nvidia,pins = "dvfs_clk_px2";
762 nvidia,function = "cldvfs";
763 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
764 nvidia,tristate = <TEGRA_PIN_DISABLE>;
765 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
766 };
767
768 /* eMMC */
769 sdmmc4-dat0-paa0 {
770 nvidia,pins = "sdmmc4_dat0_paa0";
771 nvidia,function = "sdmmc4";
772 nvidia,pull = <TEGRA_PIN_PULL_UP>;
773 nvidia,tristate = <TEGRA_PIN_DISABLE>;
774 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
775 };
776 sdmmc4-dat1-paa1 {
777 nvidia,pins = "sdmmc4_dat1_paa1";
778 nvidia,function = "sdmmc4";
779 nvidia,pull = <TEGRA_PIN_PULL_UP>;
780 nvidia,tristate = <TEGRA_PIN_DISABLE>;
781 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
782 };
783 sdmmc4-dat2-paa2 {
784 nvidia,pins = "sdmmc4_dat2_paa2";
785 nvidia,function = "sdmmc4";
786 nvidia,pull = <TEGRA_PIN_PULL_UP>;
787 nvidia,tristate = <TEGRA_PIN_DISABLE>;
788 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
789 };
790 sdmmc4-dat3-paa3 {
791 nvidia,pins = "sdmmc4_dat3_paa3";
792 nvidia,function = "sdmmc4";
793 nvidia,pull = <TEGRA_PIN_PULL_UP>;
794 nvidia,tristate = <TEGRA_PIN_DISABLE>;
795 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
796 };
797 sdmmc4-dat4-paa4 {
798 nvidia,pins = "sdmmc4_dat4_paa4";
799 nvidia,function = "sdmmc4";
800 nvidia,pull = <TEGRA_PIN_PULL_UP>;
801 nvidia,tristate = <TEGRA_PIN_DISABLE>;
802 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
803 };
804 sdmmc4-dat5-paa5 {
805 nvidia,pins = "sdmmc4_dat5_paa5";
806 nvidia,function = "sdmmc4";
807 nvidia,pull = <TEGRA_PIN_PULL_UP>;
808 nvidia,tristate = <TEGRA_PIN_DISABLE>;
809 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
810 };
811 sdmmc4-dat6-paa6 {
812 nvidia,pins = "sdmmc4_dat6_paa6";
813 nvidia,function = "sdmmc4";
814 nvidia,pull = <TEGRA_PIN_PULL_UP>;
815 nvidia,tristate = <TEGRA_PIN_DISABLE>;
816 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
817 };
818 sdmmc4-dat7-paa7 {
819 nvidia,pins = "sdmmc4_dat7_paa7";
820 nvidia,function = "sdmmc4";
821 nvidia,pull = <TEGRA_PIN_PULL_UP>;
822 nvidia,tristate = <TEGRA_PIN_DISABLE>;
823 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
824 };
825 sdmmc4-clk-pcc4 {
826 nvidia,pins = "sdmmc4_clk_pcc4";
827 nvidia,function = "sdmmc4";
828 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
829 nvidia,tristate = <TEGRA_PIN_DISABLE>;
830 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
831 };
832 sdmmc4-cmd-pt7 {
833 nvidia,pins = "sdmmc4_cmd_pt7";
834 nvidia,function = "sdmmc4";
835 nvidia,pull = <TEGRA_PIN_PULL_UP>;
836 nvidia,tristate = <TEGRA_PIN_DISABLE>;
837 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
838 };
839
840 /* JTAG_RTCK */
841 jtag-rtck {
842 nvidia,pins = "jtag_rtck";
843 nvidia,function = "rtck";
844 nvidia,pull = <TEGRA_PIN_PULL_UP>;
845 nvidia,tristate = <TEGRA_PIN_DISABLE>;
846 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
847 };
848
849 /* LAN_DEV_OFF# */
850 ulpi-data5-po6 {
851 nvidia,pins = "ulpi_data5_po6";
852 nvidia,function = "ulpi";
853 nvidia,pull = <TEGRA_PIN_PULL_UP>;
854 nvidia,tristate = <TEGRA_PIN_DISABLE>;
855 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
856 };
857
858 /* LAN_RESET# */
859 kb-row10-ps2 {
860 nvidia,pins = "kb_row10_ps2";
861 nvidia,function = "rsvd2";
862 nvidia,pull = <TEGRA_PIN_PULL_UP>;
863 nvidia,tristate = <TEGRA_PIN_DISABLE>;
864 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
865 };
866
867 /* LAN_WAKE# */
868 ulpi-data4-po5 {
869 nvidia,pins = "ulpi_data4_po5";
870 nvidia,function = "ulpi";
871 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
872 nvidia,tristate = <TEGRA_PIN_ENABLE>;
873 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
874 };
875
876 /* MCU_INT1# */
877 pk2 {
878 nvidia,pins = "pk2";
879 nvidia,function = "rsvd1";
880 nvidia,pull = <TEGRA_PIN_PULL_UP>;
881 nvidia,tristate = <TEGRA_PIN_ENABLE>;
882 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
883 };
884
885 /* MCU_INT2# */
886 pj2 {
887 nvidia,pins = "pj2";
888 nvidia,function = "rsvd1";
889 nvidia,pull = <TEGRA_PIN_PULL_UP>;
890 nvidia,tristate = <TEGRA_PIN_ENABLE>;
891 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
892 };
893
894 /* MCU_INT3# */
895 pi5 {
896 nvidia,pins = "pi5";
897 nvidia,function = "rsvd2";
898 nvidia,pull = <TEGRA_PIN_PULL_UP>;
899 nvidia,tristate = <TEGRA_PIN_ENABLE>;
900 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
901 };
902
903 /* MCU_INT4# */
904 pj0 {
905 nvidia,pins = "pj0";
906 nvidia,function = "rsvd1";
907 nvidia,pull = <TEGRA_PIN_PULL_UP>;
908 nvidia,tristate = <TEGRA_PIN_ENABLE>;
909 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
910 };
911
912 /* MCU_RESET */
913 pbb6 {
914 nvidia,pins = "pbb6";
915 nvidia,function = "rsvd2";
916 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
917 nvidia,tristate = <TEGRA_PIN_DISABLE>;
918 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
919 };
920
921 /* MCU SPI */
922 gpio-x4-aud-px4 {
923 nvidia,pins = "gpio_x4_aud_px4";
924 nvidia,function = "spi2";
925 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
926 nvidia,tristate = <TEGRA_PIN_DISABLE>;
927 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
928 };
929 gpio-x5-aud-px5 {
930 nvidia,pins = "gpio_x5_aud_px5";
931 nvidia,function = "spi2";
932 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
933 nvidia,tristate = <TEGRA_PIN_DISABLE>;
934 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
935 };
936 gpio-x6-aud-px6 { /* MCU_CS */
937 nvidia,pins = "gpio_x6_aud_px6";
938 nvidia,function = "spi2";
939 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
940 nvidia,tristate = <TEGRA_PIN_DISABLE>;
941 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
942 };
943 gpio-x7-aud-px7 {
944 nvidia,pins = "gpio_x7_aud_px7";
945 nvidia,function = "spi2";
946 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
947 nvidia,tristate = <TEGRA_PIN_ENABLE>;
948 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
949 };
950 gpio-w2-aud-pw2 { /* MCU_CSEZP */
951 nvidia,pins = "gpio_w2_aud_pw2";
952 nvidia,function = "spi2";
953 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
954 nvidia,tristate = <TEGRA_PIN_DISABLE>;
955 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
956 };
957
958 /* PMIC_CLK_32K */
959 clk-32k-in {
960 nvidia,pins = "clk_32k_in";
961 nvidia,function = "clk";
962 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
963 nvidia,tristate = <TEGRA_PIN_ENABLE>;
964 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
965 };
966
967 /* PMIC_CPU_OC_INT */
968 clk-32k-out-pa0 {
969 nvidia,pins = "clk_32k_out_pa0";
970 nvidia,function = "soc";
971 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
972 nvidia,tristate = <TEGRA_PIN_ENABLE>;
973 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
974 };
975
976 /* PWR_I2C */
977 pwr-i2c-scl-pz6 {
978 nvidia,pins = "pwr_i2c_scl_pz6";
979 nvidia,function = "i2cpwr";
980 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
981 nvidia,tristate = <TEGRA_PIN_DISABLE>;
982 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
983 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
984 };
985 pwr-i2c-sda-pz7 {
986 nvidia,pins = "pwr_i2c_sda_pz7";
987 nvidia,function = "i2cpwr";
988 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
989 nvidia,tristate = <TEGRA_PIN_DISABLE>;
990 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
991 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
992 };
993
994 /* PWR_INT_N */
995 pwr-int-n {
996 nvidia,pins = "pwr_int_n";
997 nvidia,function = "pmi";
998 nvidia,pull = <TEGRA_PIN_PULL_UP>;
999 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1000 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1001 };
1002
1003 /* RESET_MOCI_CTRL */
1004 pu4 {
1005 nvidia,pins = "pu4";
1006 nvidia,function = "gmi";
1007 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1008 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1009 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1010 };
1011
1012 /* RESET_OUT_N */
1013 reset-out-n {
1014 nvidia,pins = "reset_out_n";
1015 nvidia,function = "reset_out_n";
1016 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1017 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1018 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1019 };
1020
1021 /* SHIFT_CTRL_DIR_IN */
1022 kb-row0-pr0 {
1023 nvidia,pins = "kb_row0_pr0";
1024 nvidia,function = "rsvd2";
1025 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1026 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1027 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1028 };
1029 kb-row1-pr1 {
1030 nvidia,pins = "kb_row1_pr1";
1031 nvidia,function = "rsvd2";
1032 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1033 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1034 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1035 };
1036
1037 /* Configure level-shifter as output for HDA */
1038 kb-row11-ps3 {
1039 nvidia,pins = "kb_row11_ps3";
1040 nvidia,function = "rsvd2";
1041 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1042 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1043 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1044 };
1045
1046 /* SHIFT_CTRL_DIR_OUT */
1047 kb-col5-pq5 {
1048 nvidia,pins = "kb_col5_pq5";
1049 nvidia,function = "rsvd2";
1050 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1051 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1052 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1053 };
1054 kb-col6-pq6 {
1055 nvidia,pins = "kb_col6_pq6";
1056 nvidia,function = "rsvd2";
1057 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1058 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1059 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1060 };
1061 kb-col7-pq7 {
1062 nvidia,pins = "kb_col7_pq7";
1063 nvidia,function = "rsvd2";
1064 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1065 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1066 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1067 };
1068
1069 /* SHIFT_CTRL_OE */
1070 kb-col0-pq0 {
1071 nvidia,pins = "kb_col0_pq0";
1072 nvidia,function = "rsvd2";
1073 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1074 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1075 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1076 };
1077 kb-col1-pq1 {
1078 nvidia,pins = "kb_col1_pq1";
1079 nvidia,function = "rsvd2";
1080 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1081 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1082 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1083 };
1084 kb-col2-pq2 {
1085 nvidia,pins = "kb_col2_pq2";
1086 nvidia,function = "rsvd2";
1087 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1088 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1089 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1090 };
1091 kb-col4-pq4 {
1092 nvidia,pins = "kb_col4_pq4";
1093 nvidia,function = "kbc";
1094 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1095 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1096 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1097 };
1098 kb-row2-pr2 {
1099 nvidia,pins = "kb_row2_pr2";
1100 nvidia,function = "rsvd2";
1101 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1102 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1103 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1104 };
1105
1106 /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
1107 pi6 {
1108 nvidia,pins = "pi6";
1109 nvidia,function = "rsvd1";
1110 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1111 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1112 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1113 };
1114
1115 /* TOUCH_INT */
1116 gpio-w3-aud-pw3 {
1117 nvidia,pins = "gpio_w3_aud_pw3";
1118 nvidia,function = "spi6";
1119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1120 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1121 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1122 };
1123
1124 pc7 { /* NC */
1125 nvidia,pins = "pc7";
1126 nvidia,function = "rsvd1";
1127 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1128 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1129 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1130 };
1131 pg0 { /* NC */
1132 nvidia,pins = "pg0";
1133 nvidia,function = "rsvd1";
1134 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1135 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1136 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1137 };
1138 pg1 { /* NC */
1139 nvidia,pins = "pg1";
1140 nvidia,function = "rsvd1";
1141 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1142 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1143 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1144 };
1145 pg2 { /* NC */
1146 nvidia,pins = "pg2";
1147 nvidia,function = "rsvd1";
1148 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1149 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1150 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1151 };
1152 pg3 { /* NC */
1153 nvidia,pins = "pg3";
1154 nvidia,function = "rsvd1";
1155 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1156 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1157 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1158 };
1159 pg4 { /* NC */
1160 nvidia,pins = "pg4";
1161 nvidia,function = "rsvd1";
1162 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1163 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1164 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1165 };
1166 ph4 { /* NC */
1167 nvidia,pins = "ph4";
1168 nvidia,function = "rsvd2";
1169 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1170 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1171 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1172 };
1173 ph5 { /* NC */
1174 nvidia,pins = "ph5";
1175 nvidia,function = "rsvd2";
1176 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1177 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1178 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1179 };
1180 ph6 { /* NC */
1181 nvidia,pins = "ph6";
1182 nvidia,function = "gmi";
1183 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1184 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1185 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1186 };
1187 ph7 { /* NC */
1188 nvidia,pins = "ph7";
1189 nvidia,function = "gmi";
1190 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1191 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1192 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1193 };
1194 pi0 { /* NC */
1195 nvidia,pins = "pi0";
1196 nvidia,function = "rsvd1";
1197 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1198 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1199 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1200 };
1201 pi1 { /* NC */
1202 nvidia,pins = "pi1";
1203 nvidia,function = "rsvd1";
1204 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1205 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1206 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1207 };
1208 pi2 { /* NC */
1209 nvidia,pins = "pi2";
1210 nvidia,function = "rsvd4";
1211 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1212 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1213 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1214 };
1215 pi4 { /* NC */
1216 nvidia,pins = "pi4";
1217 nvidia,function = "gmi";
1218 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1219 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1220 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1221 };
1222 pi7 { /* NC */
1223 nvidia,pins = "pi7";
1224 nvidia,function = "rsvd1";
1225 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1226 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1227 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1228 };
1229 pk0 { /* NC */
1230 nvidia,pins = "pk0";
1231 nvidia,function = "rsvd1";
1232 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1233 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1234 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1235 };
1236 pk1 { /* NC */
1237 nvidia,pins = "pk1";
1238 nvidia,function = "rsvd4";
1239 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1241 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1242 };
1243 pk3 { /* NC */
1244 nvidia,pins = "pk3";
1245 nvidia,function = "gmi";
1246 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1247 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1248 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1249 };
1250 pk4 { /* NC */
1251 nvidia,pins = "pk4";
1252 nvidia,function = "rsvd2";
1253 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1254 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1255 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1256 };
1257 dap1-fs-pn0 { /* NC */
1258 nvidia,pins = "dap1_fs_pn0";
1259 nvidia,function = "rsvd4";
1260 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1261 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1262 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1263 };
1264 dap1-din-pn1 { /* NC */
1265 nvidia,pins = "dap1_din_pn1";
1266 nvidia,function = "rsvd4";
1267 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1268 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1269 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1270 };
1271 dap1-sclk-pn3 { /* NC */
1272 nvidia,pins = "dap1_sclk_pn3";
1273 nvidia,function = "rsvd4";
1274 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1275 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1276 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1277 };
1278 ulpi-data7-po0 { /* NC */
1279 nvidia,pins = "ulpi_data7_po0";
1280 nvidia,function = "ulpi";
1281 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1282 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1283 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1284 };
1285 ulpi-data0-po1 { /* NC */
1286 nvidia,pins = "ulpi_data0_po1";
1287 nvidia,function = "ulpi";
1288 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1289 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1290 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1291 };
1292 ulpi-data1-po2 { /* NC */
1293 nvidia,pins = "ulpi_data1_po2";
1294 nvidia,function = "ulpi";
1295 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1296 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1297 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1298 };
1299 ulpi-data2-po3 { /* NC */
1300 nvidia,pins = "ulpi_data2_po3";
1301 nvidia,function = "ulpi";
1302 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1303 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1304 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1305 };
1306 ulpi-data3-po4 { /* NC */
1307 nvidia,pins = "ulpi_data3_po4";
1308 nvidia,function = "ulpi";
1309 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1310 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1311 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1312 };
1313 ulpi-data6-po7 { /* NC */
1314 nvidia,pins = "ulpi_data6_po7";
1315 nvidia,function = "ulpi";
1316 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1317 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1318 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1319 };
1320 dap4-fs-pp4 { /* NC */
1321 nvidia,pins = "dap4_fs_pp4";
1322 nvidia,function = "rsvd4";
1323 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1324 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1325 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1326 };
1327 dap4-din-pp5 { /* NC */
1328 nvidia,pins = "dap4_din_pp5";
1329 nvidia,function = "rsvd3";
1330 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1331 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1332 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1333 };
1334 dap4-dout-pp6 { /* NC */
1335 nvidia,pins = "dap4_dout_pp6";
1336 nvidia,function = "rsvd4";
1337 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1338 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1339 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1340 };
1341 dap4-sclk-pp7 { /* NC */
1342 nvidia,pins = "dap4_sclk_pp7";
1343 nvidia,function = "rsvd3";
1344 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1345 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1346 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1347 };
1348 kb-col3-pq3 { /* NC */
1349 nvidia,pins = "kb_col3_pq3";
1350 nvidia,function = "kbc";
1351 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1352 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1353 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1354 };
1355 kb-row3-pr3 { /* NC */
1356 nvidia,pins = "kb_row3_pr3";
1357 nvidia,function = "kbc";
1358 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1359 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1360 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1361 };
1362 kb-row4-pr4 { /* NC */
1363 nvidia,pins = "kb_row4_pr4";
1364 nvidia,function = "rsvd3";
1365 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1366 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1367 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1368 };
1369 kb-row5-pr5 { /* NC */
1370 nvidia,pins = "kb_row5_pr5";
1371 nvidia,function = "rsvd3";
1372 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1373 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1374 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1375 };
1376 kb-row6-pr6 { /* NC */
1377 nvidia,pins = "kb_row6_pr6";
1378 nvidia,function = "kbc";
1379 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1380 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1381 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1382 };
1383 kb-row7-pr7 { /* NC */
1384 nvidia,pins = "kb_row7_pr7";
1385 nvidia,function = "rsvd2";
1386 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1387 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1388 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1389 };
1390 kb-row8-ps0 { /* NC */
1391 nvidia,pins = "kb_row8_ps0";
1392 nvidia,function = "rsvd2";
1393 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1394 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1395 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1396 };
1397 kb-row9-ps1 { /* NC */
1398 nvidia,pins = "kb_row9_ps1";
1399 nvidia,function = "rsvd2";
1400 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1401 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1402 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1403 };
1404 kb-row12-ps4 { /* NC */
1405 nvidia,pins = "kb_row12_ps4";
1406 nvidia,function = "rsvd2";
1407 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1408 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1409 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1410 };
1411 kb-row13-ps5 { /* NC */
1412 nvidia,pins = "kb_row13_ps5";
1413 nvidia,function = "rsvd2";
1414 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1415 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1416 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1417 };
1418 kb-row14-ps6 { /* NC */
1419 nvidia,pins = "kb_row14_ps6";
1420 nvidia,function = "rsvd2";
1421 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1422 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1423 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1424 };
1425 kb-row15-ps7 { /* NC */
1426 nvidia,pins = "kb_row15_ps7";
1427 nvidia,function = "rsvd3";
1428 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1429 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1430 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1431 };
1432 kb-row16-pt0 { /* NC */
1433 nvidia,pins = "kb_row16_pt0";
1434 nvidia,function = "rsvd2";
1435 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1436 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1437 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1438 };
1439 kb-row17-pt1 { /* NC */
1440 nvidia,pins = "kb_row17_pt1";
1441 nvidia,function = "rsvd2";
1442 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1443 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1444 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1445 };
1446 pu5 { /* NC */
1447 nvidia,pins = "pu5";
1448 nvidia,function = "gmi";
1449 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1450 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1451 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1452 };
1453 /*
1454 * PCB Version Indication: V1.2 and later have GPIO_PV0
1455 * wired to GND, was NC before
1456 */
1457 pv0 {
1458 nvidia,pins = "pv0";
1459 nvidia,function = "rsvd1";
1460 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1461 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1462 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1463 };
1464 pv1 { /* NC */
1465 nvidia,pins = "pv1";
1466 nvidia,function = "rsvd1";
1467 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1468 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1469 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1470 };
1471 gpio-x1-aud-px1 { /* NC */
1472 nvidia,pins = "gpio_x1_aud_px1";
1473 nvidia,function = "rsvd2";
1474 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1475 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1476 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1477 };
1478 gpio-x3-aud-px3 { /* NC */
1479 nvidia,pins = "gpio_x3_aud_px3";
1480 nvidia,function = "rsvd4";
1481 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1482 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1483 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1484 };
1485 pbb7 { /* NC */
1486 nvidia,pins = "pbb7";
1487 nvidia,function = "rsvd2";
1488 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1489 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1490 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1491 };
1492 pcc1 { /* NC */
1493 nvidia,pins = "pcc1";
1494 nvidia,function = "rsvd2";
1495 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1496 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1497 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1498 };
1499 pcc2 { /* NC */
1500 nvidia,pins = "pcc2";
1501 nvidia,function = "rsvd2";
1502 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1503 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1504 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1505 };
1506 clk3-req-pee1 { /* NC */
1507 nvidia,pins = "clk3_req_pee1";
1508 nvidia,function = "rsvd2";
1509 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1510 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1511 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1512 };
1513 dap-mclk1-req-pee2 { /* NC */
1514 nvidia,pins = "dap_mclk1_req_pee2";
1515 nvidia,function = "rsvd4";
1516 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1517 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1518 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1519 };
1520 /*
1521 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
1522 * driver enabled aka not tristated and input driver
1523 * enabled as well as it features some magic properties
1524 * even though the external loopback is disabled and the
1525 * internal loopback used as per
1526 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
1527 * bits being set to 0xfffd according to the TRM!
1528 */
1529 sdmmc3-clk-lb-out-pee4 { /* NC */
1530 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1531 nvidia,function = "sdmmc3";
1532 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1533 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1534 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1535 };
1536 };
1537 };
1538
1539 serial@70006040 {
1540 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1541 };
1542
1543 serial@70006200 {
1544 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1545 };
1546
1547 serial@70006300 {
1548 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
1549 };
1550
1551 hdmi_ddc: i2c@7000c700 {
1552 clock-frequency = <10000>;
1553 };
1554
1555 /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
1556 i2c@7000d000 {
1557 status = "okay";
1558 clock-frequency = <400000>;
1559
1560 /* SGTL5000 audio codec */
1561 sgtl5000: codec@a {
1562 compatible = "fsl,sgtl5000";
1563 reg = <0x0a>;
1564 VDDA-supply = <&reg_module_3v3_audio>;
1565 VDDD-supply = <&reg_1v8_vddio>;
1566 VDDIO-supply = <&reg_1v8_vddio>;
1567 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1568 };
1569
1570 pmic: pmic@40 {
1571 compatible = "ams,as3722";
1572 reg = <0x40>;
1573 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1574 ams,system-power-controller;
1575 #interrupt-cells = <2>;
1576 interrupt-controller;
1577 gpio-controller;
1578 #gpio-cells = <2>;
1579 pinctrl-names = "default";
1580 pinctrl-0 = <&as3722_default>;
1581
1582 as3722_default: pinmux {
1583 gpio2-7 {
1584 pins = "gpio2", /* PWR_EN_+V3.3 */
1585 "gpio7"; /* +V1.6_LPO */
1586 function = "gpio";
1587 bias-pull-up;
1588 };
1589
1590 gpio0-1-3-4-5-6 {
1591 pins = "gpio0", "gpio1", "gpio3",
1592 "gpio4", "gpio5", "gpio6";
1593 bias-high-impedance;
1594 };
1595 };
1596
1597 regulators {
1598 vsup-sd2-supply = <&reg_module_3v3>;
1599 vsup-sd3-supply = <&reg_module_3v3>;
1600 vsup-sd4-supply = <&reg_module_3v3>;
1601 vsup-sd5-supply = <&reg_module_3v3>;
1602 vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
1603 vin-ldo1-6-supply = <&reg_module_3v3>;
1604 vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
1605 vin-ldo3-4-supply = <&reg_module_3v3>;
1606 vin-ldo9-10-supply = <&reg_module_3v3>;
1607 vin-ldo11-supply = <&reg_module_3v3>;
1608
1609 reg_vdd_cpu: sd0 {
1610 regulator-name = "+VDD_CPU_AP";
1611 regulator-min-microvolt = <700000>;
1612 regulator-max-microvolt = <1400000>;
1613 regulator-min-microamp = <3500000>;
1614 regulator-max-microamp = <3500000>;
1615 regulator-always-on;
1616 regulator-boot-on;
1617 ams,ext-control = <2>;
1618 };
1619
1620 sd1 {
1621 regulator-name = "+VDD_CORE";
1622 regulator-min-microvolt = <700000>;
1623 regulator-max-microvolt = <1350000>;
1624 regulator-min-microamp = <2500000>;
1625 regulator-max-microamp = <4000000>;
1626 regulator-always-on;
1627 regulator-boot-on;
1628 ams,ext-control = <1>;
1629 };
1630
1631 reg_1v35_vddio_ddr: sd2 {
1632 regulator-name =
1633 "+V1.35_VDDIO_DDR(sd2)";
1634 regulator-min-microvolt = <1350000>;
1635 regulator-max-microvolt = <1350000>;
1636 regulator-always-on;
1637 regulator-boot-on;
1638 };
1639
1640 sd3 {
1641 regulator-name =
1642 "+V1.35_VDDIO_DDR(sd3)";
1643 regulator-min-microvolt = <1350000>;
1644 regulator-max-microvolt = <1350000>;
1645 regulator-always-on;
1646 regulator-boot-on;
1647 };
1648
1649 reg_1v05_vdd: sd4 {
1650 regulator-name = "+V1.05";
1651 regulator-min-microvolt = <1050000>;
1652 regulator-max-microvolt = <1050000>;
1653 };
1654
1655 reg_1v8_vddio: sd5 {
1656 regulator-name = "+V1.8";
1657 regulator-min-microvolt = <1800000>;
1658 regulator-max-microvolt = <1800000>;
1659 regulator-boot-on;
1660 regulator-always-on;
1661 };
1662
1663 reg_vdd_gpu: sd6 {
1664 regulator-name = "+VDD_GPU_AP";
1665 regulator-min-microvolt = <650000>;
1666 regulator-max-microvolt = <1200000>;
1667 regulator-min-microamp = <3500000>;
1668 regulator-max-microamp = <3500000>;
1669 regulator-boot-on;
1670 regulator-always-on;
1671 };
1672
1673 reg_1v05_avdd: ldo0 {
1674 regulator-name = "+V1.05_AVDD";
1675 regulator-min-microvolt = <1050000>;
1676 regulator-max-microvolt = <1050000>;
1677 regulator-boot-on;
1678 regulator-always-on;
1679 ams,ext-control = <1>;
1680 };
1681
1682 vddio_sdmmc1: ldo1 {
1683 regulator-name = "VDDIO_SDMMC1";
1684 regulator-min-microvolt = <1800000>;
1685 regulator-max-microvolt = <3300000>;
1686 };
1687
1688 ldo2 {
1689 regulator-name = "+V1.2";
1690 regulator-min-microvolt = <1200000>;
1691 regulator-max-microvolt = <1200000>;
1692 regulator-boot-on;
1693 regulator-always-on;
1694 };
1695
1696 ldo3 {
1697 regulator-name = "+V1.05_RTC";
1698 regulator-min-microvolt = <1000000>;
1699 regulator-max-microvolt = <1000000>;
1700 regulator-boot-on;
1701 regulator-always-on;
1702 ams,enable-tracking;
1703 };
1704
1705 /* 1.8V for LVDS, 3.3V for eDP */
1706 ldo4 {
1707 regulator-name = "AVDD_LVDS0_PLL";
1708 regulator-min-microvolt = <1800000>;
1709 regulator-max-microvolt = <1800000>;
1710 };
1711
1712 /* LDO5 not used */
1713
1714 vddio_sdmmc3: ldo6 {
1715 regulator-name = "VDDIO_SDMMC3";
1716 regulator-min-microvolt = <1800000>;
1717 regulator-max-microvolt = <3300000>;
1718 };
1719
1720 /* LDO7 not used */
1721
1722 ldo9 {
1723 regulator-name = "+V3.3_ETH(ldo9)";
1724 regulator-min-microvolt = <3300000>;
1725 regulator-max-microvolt = <3300000>;
1726 regulator-always-on;
1727 };
1728
1729 ldo10 {
1730 regulator-name = "+V3.3_ETH(ldo10)";
1731 regulator-min-microvolt = <3300000>;
1732 regulator-max-microvolt = <3300000>;
1733 regulator-always-on;
1734 };
1735
1736 ldo11 {
1737 regulator-name = "+V1.8_VPP_FUSE";
1738 regulator-min-microvolt = <1800000>;
1739 regulator-max-microvolt = <1800000>;
1740 };
1741 };
1742 };
1743
1744 /*
1745 * TMP451 temperature sensor
1746 * Note: THERM_N directly connected to AS3722 PMIC THERM
1747 */
1748 temp-sensor@4c {
1749 compatible = "ti,tmp451";
1750 reg = <0x4c>;
1751 interrupt-parent = <&gpio>;
1752 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1753 #thermal-sensor-cells = <1>;
1754 vcc-supply = <&reg_module_3v3>;
1755 };
1756 };
1757
1758 /* SPI2: MCU SPI */
1759 spi@7000d600 {
1760 status = "okay";
1761 spi-max-frequency = <25000000>;
1762 };
1763
1764 pmc@7000e400 {
1765 nvidia,invert-interrupt;
1766 nvidia,suspend-mode = <1>;
1767 nvidia,cpu-pwr-good-time = <500>;
1768 nvidia,cpu-pwr-off-time = <300>;
1769 nvidia,core-pwr-good-time = <641 3845>;
1770 nvidia,core-pwr-off-time = <61036>;
1771 nvidia,core-power-req-active-high;
1772 nvidia,sys-clock-req-active-high;
1773
1774 /* Set power_off bit in ResetControl register of AS3722 PMIC */
1775 i2c-thermtrip {
1776 nvidia,i2c-controller-id = <4>;
1777 nvidia,bus-addr = <0x40>;
1778 nvidia,reg-addr = <0x36>;
1779 nvidia,reg-data = <0x2>;
1780 };
1781 };
1782
1783 sata@70020000 {
1784 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1785 phy-names = "sata-0";
1786 avdd-supply = <&reg_1v05_vdd>;
1787 hvdd-supply = <&reg_module_3v3>;
1788 vddio-supply = <&reg_1v05_vdd>;
1789 };
1790
1791 usb@70090000 {
1792 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
1793 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1794 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
1795 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1796 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1797 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1798 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1799 avddio-pex-supply = <&reg_1v05_vdd>;
1800 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
1801 avdd-pll-utmip-supply = <&reg_1v8_vddio>;
1802 avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
1803 avdd-usb-supply = <&reg_module_3v3>;
1804 dvddio-pex-supply = <&reg_1v05_vdd>;
1805 hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
1806 hvdd-usb-ss-supply = <&reg_module_3v3>;
1807 };
1808
1809 padctl@7009f000 {
1810 pads {
1811 usb2 {
1812 status = "okay";
1813
1814 lanes {
1815 usb2-0 {
1816 status = "okay";
1817 nvidia,function = "xusb";
1818 };
1819
1820 usb2-1 {
1821 status = "okay";
1822 nvidia,function = "xusb";
1823 };
1824
1825 usb2-2 {
1826 status = "okay";
1827 nvidia,function = "xusb";
1828 };
1829 };
1830 };
1831
1832 pcie {
1833 status = "okay";
1834
1835 lanes {
1836 pcie-0 {
1837 status = "okay";
1838 nvidia,function = "usb3-ss";
1839 };
1840
1841 pcie-1 {
1842 status = "okay";
1843 nvidia,function = "usb3-ss";
1844 };
1845
1846 pcie-2 {
1847 status = "okay";
1848 nvidia,function = "pcie";
1849 };
1850
1851 pcie-3 {
1852 status = "okay";
1853 nvidia,function = "pcie";
1854 };
1855
1856 pcie-4 {
1857 status = "okay";
1858 nvidia,function = "pcie";
1859 };
1860 };
1861 };
1862
1863 sata {
1864 status = "okay";
1865
1866 lanes {
1867 sata-0 {
1868 status = "okay";
1869 nvidia,function = "sata";
1870 };
1871 };
1872 };
1873 };
1874
1875 ports {
1876 /* USBO1 */
1877 usb2-0 {
1878 status = "okay";
1879 mode = "otg";
1880 vbus-supply = <&reg_usbo1_vbus>;
1881 };
1882
1883 /* USBH2 */
1884 usb2-1 {
1885 status = "okay";
1886 mode = "host";
1887 vbus-supply = <&reg_usbh_vbus>;
1888 };
1889
1890 /* USBH4 */
1891 usb2-2 {
1892 status = "okay";
1893 mode = "host";
1894 vbus-supply = <&reg_usbh_vbus>;
1895 };
1896
1897 usb3-0 {
1898 status = "okay";
1899 nvidia,usb2-companion = <2>;
1900 vbus-supply = <&reg_usbh_vbus>;
1901 };
1902
1903 usb3-1 {
1904 status = "okay";
1905 nvidia,usb2-companion = <0>;
1906 vbus-supply = <&reg_usbo1_vbus>;
1907 };
1908 };
1909 };
1910
1911 /* eMMC */
1912 sdhci@700b0600 {
1913 status = "okay";
1914 bus-width = <8>;
1915 non-removable;
1916 vmmc-supply = <&reg_module_3v3>; /* VCC */
1917 vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
1918 mmc-ddr-1_8v;
1919 };
1920
1921 /* CPU DFLL clock */
1922 clock@70110000 {
1923 status = "okay";
1924 nvidia,i2c-fs-rate = <400000>;
1925 vdd-cpu-supply = <&reg_vdd_cpu>;
1926 };
1927
1928 ahub@70300000 {
1929 i2s@70301200 {
1930 status = "okay";
1931 };
1932 };
1933
1934 clk32k_in: osc3 {
1935 compatible = "fixed-clock";
1936 #clock-cells = <0>;
1937 clock-frequency = <32768>;
1938 };
1939
1940 cpus {
1941 cpu@0 {
1942 vdd-cpu-supply = <&reg_vdd_cpu>;
1943 };
1944 };
1945
1946 reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
1947 compatible = "regulator-fixed";
1948 regulator-name = "+V1.05_AVDD_HDMI_PLL";
1949 regulator-min-microvolt = <1050000>;
1950 regulator-max-microvolt = <1050000>;
1951 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1952 vin-supply = <&reg_1v05_vdd>;
1953 };
1954
1955 reg_3v3_mxm: regulator-3v3-mxm {
1956 compatible = "regulator-fixed";
1957 regulator-name = "+V3.3_MXM";
1958 regulator-min-microvolt = <3300000>;
1959 regulator-max-microvolt = <3300000>;
1960 regulator-always-on;
1961 regulator-boot-on;
1962 };
1963
1964 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1965 compatible = "regulator-fixed";
1966 regulator-name = "+V3.3_AVDD_HDMI";
1967 regulator-min-microvolt = <3300000>;
1968 regulator-max-microvolt = <3300000>;
1969 vin-supply = <&reg_1v05_vdd>;
1970 };
1971
1972 reg_module_3v3: regulator-module-3v3 {
1973 compatible = "regulator-fixed";
1974 regulator-name = "+V3.3";
1975 regulator-min-microvolt = <3300000>;
1976 regulator-max-microvolt = <3300000>;
1977 regulator-always-on;
1978 regulator-boot-on;
1979 /* PWR_EN_+V3.3 */
1980 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1981 enable-active-high;
1982 vin-supply = <&reg_3v3_mxm>;
1983 };
1984
1985 reg_module_3v3_audio: regulator-module-3v3-audio {
1986 compatible = "regulator-fixed";
1987 regulator-name = "+V3.3_AUDIO_AVDD_S";
1988 regulator-min-microvolt = <3300000>;
1989 regulator-max-microvolt = <3300000>;
1990 regulator-always-on;
1991 };
1992
1993 sound {
1994 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
1995 "nvidia,tegra-audio-sgtl5000";
1996 nvidia,model = "Toradex Apalis TK1";
1997 nvidia,audio-routing =
1998 "Headphone Jack", "HP_OUT",
1999 "LINE_IN", "Line In Jack",
2000 "MIC_IN", "Mic Jack";
2001 nvidia,i2s-controller = <&tegra_i2s2>;
2002 nvidia,audio-codec = <&sgtl5000>;
2003 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
2004 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2005 <&tegra_car TEGRA124_CLK_EXTERN1>;
2006 clock-names = "pll_a", "pll_a_out0", "mclk";
2007 };
2008
2009 thermal-zones {
2010 cpu {
2011 trips {
2012 cpu-shutdown-trip {
2013 temperature = <101000>;
2014 hysteresis = <0>;
2015 type = "critical";
2016 };
2017 };
2018 };
2019
2020 mem {
2021 trips {
2022 mem-shutdown-trip {
2023 temperature = <101000>;
2024 hysteresis = <0>;
2025 type = "critical";
2026 };
2027 };
2028 };
2029
2030 gpu {
2031 trips {
2032 gpu-shutdown-trip {
2033 temperature = <101000>;
2034 hysteresis = <0>;
2035 type = "critical";
2036 };
2037 };
2038 };
2039 };
2040 };
2041
2042 &gpio {
2043 /* I210 Gigabit Ethernet Controller Reset */
2044 lan-reset-n {
2045 gpio-hog;
2046 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
2047 output-high;
2048 line-name = "LAN_RESET_N";
2049 };
2050
2051 /* Control MXM3 pin 26 Reset Module Output Carrier Input */
2052 reset-moci-ctrl {
2053 gpio-hog;
2054 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
2055 output-high;
2056 line-name = "RESET_MOCI_CTRL";
2057 };
2058 };
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