1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra20.dtsi"
5 model = "Toradex Colibri T20 512MB";
6 compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
9 rtc0 = "/i2c@7000d000/tps6586x@34";
10 rtc1 = "/rtc@7000e000";
14 reg = <0x00000000 0x20000000>;
19 vdd-supply = <&hdmi_vdd_reg>;
20 pll-supply = <&hdmi_pll_reg>;
22 nvidia,ddc-i2c-bus = <&i2c_ddc>;
23 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
32 state_default: pinmux {
34 nvidia,pins = "cdev1";
35 nvidia,function = "plla_out";
36 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
37 nvidia,tristate = <TEGRA_PIN_DISABLE>;
41 nvidia,function = "crt";
42 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
43 nvidia,tristate = <TEGRA_PIN_ENABLE>;
47 nvidia,function = "dap3";
48 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
49 nvidia,tristate = <TEGRA_PIN_DISABLE>;
52 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
53 "ld4", "ld5", "ld6", "ld7", "ld8",
54 "ld9", "ld10", "ld11", "ld12", "ld13",
55 "ld14", "ld15", "ld16", "ld17",
56 "lhs", "lpw0", "lpw2", "lsc0",
57 "lsc1", "lsck", "lsda", "lspi", "lvs";
58 nvidia,function = "displaya";
59 nvidia,tristate = <TEGRA_PIN_ENABLE>;
63 nvidia,function = "rsvd1";
64 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
65 nvidia,tristate = <TEGRA_PIN_DISABLE>;
68 nvidia,pins = "ata", "atc", "atd", "ate",
69 "dap1", "dap2", "dap4", "gpu", "irrx",
70 "irtx", "spia", "spib", "spic";
71 nvidia,function = "gmi";
72 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
73 nvidia,tristate = <TEGRA_PIN_DISABLE>;
77 nvidia,function = "rsvd4";
78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
83 nvidia,function = "rsvd2";
84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
88 nvidia,pins = "hdint";
89 nvidia,function = "hdmi";
90 nvidia,tristate = <TEGRA_PIN_ENABLE>;
94 nvidia,function = "i2c1";
95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <TEGRA_PIN_ENABLE>;
100 nvidia,function = "i2c3";
101 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
102 nvidia,tristate = <TEGRA_PIN_ENABLE>;
106 nvidia,function = "i2c2";
107 nvidia,pull = <TEGRA_PIN_PULL_UP>;
108 nvidia,tristate = <TEGRA_PIN_ENABLE>;
111 nvidia,pins = "i2cp";
112 nvidia,function = "i2cp";
113 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114 nvidia,tristate = <TEGRA_PIN_DISABLE>;
118 nvidia,function = "irda";
119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120 nvidia,tristate = <TEGRA_PIN_ENABLE>;
123 nvidia,pins = "kbca", "kbcc", "kbcd",
125 nvidia,function = "nand";
126 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
127 nvidia,tristate = <TEGRA_PIN_DISABLE>;
131 nvidia,function = "owr";
132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristate = <TEGRA_PIN_ENABLE>;
137 nvidia,function = "pwr_on";
138 nvidia,tristate = <TEGRA_PIN_DISABLE>;
141 nvidia,pins = "sdb", "sdc", "sdd";
142 nvidia,function = "pwm";
143 nvidia,tristate = <TEGRA_PIN_ENABLE>;
146 nvidia,pins = "atb", "gma", "gme";
147 nvidia,function = "sdio4";
148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <TEGRA_PIN_ENABLE>;
152 nvidia,pins = "spid", "spie", "spif";
153 nvidia,function = "spi1";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_ENABLE>;
158 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
159 nvidia,function = "spi4";
160 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
161 nvidia,tristate = <TEGRA_PIN_ENABLE>;
164 nvidia,pins = "sdio1";
165 nvidia,function = "uarta";
166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristate = <TEGRA_PIN_ENABLE>;
171 nvidia,function = "uartd";
172 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173 nvidia,tristate = <TEGRA_PIN_ENABLE>;
176 nvidia,pins = "uaa", "uab", "uda";
177 nvidia,function = "ulpi";
178 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
179 nvidia,tristate = <TEGRA_PIN_DISABLE>;
182 nvidia,pins = "cdev2";
183 nvidia,function = "pllp_out4";
184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
188 nvidia,pins = "spig", "spih";
189 nvidia,function = "spi2_alt";
190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 nvidia,tristate = <TEGRA_PIN_DISABLE>;
194 nvidia,pins = "dta", "dtb", "dtc", "dtd";
195 nvidia,function = "vi";
196 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
197 nvidia,tristate = <TEGRA_PIN_ENABLE>;
200 nvidia,pins = "csus";
201 nvidia,function = "vi_sensor_clk";
202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
203 nvidia,tristate = <TEGRA_PIN_ENABLE>;
208 ac97: ac97@70002000 {
210 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
212 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
217 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
221 clock-frequency = <400000>;
224 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
225 i2c_ddc: i2c@7000c400 {
226 clock-frequency = <10000>;
229 /* GEN2_I2C: unused */
231 /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
233 /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
236 clock-frequency = <100000>;
239 compatible = "ti,tps6586x";
241 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
243 ti,system-power-controller;
248 sys-supply = <&vdd_3v3_reg>;
249 vin-sm0-supply = <&sys_reg>;
250 vin-sm1-supply = <&sys_reg>;
251 vin-sm2-supply = <&sys_reg>;
252 vinldo01-supply = <&sm2_reg>;
253 vinldo23-supply = <&vdd_3v3_reg>;
254 vinldo4-supply = <&vdd_3v3_reg>;
255 vinldo678-supply = <&vdd_3v3_reg>;
256 vinldo9-supply = <&vdd_3v3_reg>;
259 #address-cells = <1>;
262 sys_reg: regulator@0 {
264 regulator-compatible = "sys";
265 regulator-name = "vdd_sys";
271 regulator-compatible = "sm0";
272 regulator-name = "vdd_sm0,vdd_core";
273 regulator-min-microvolt = <1200000>;
274 regulator-max-microvolt = <1200000>;
280 regulator-compatible = "sm1";
281 regulator-name = "vdd_sm1,vdd_cpu";
282 regulator-min-microvolt = <1000000>;
283 regulator-max-microvolt = <1000000>;
287 sm2_reg: regulator@3 {
289 regulator-compatible = "sm2";
290 regulator-name = "vdd_sm2,vin_ldo*";
291 regulator-min-microvolt = <1800000>;
292 regulator-max-microvolt = <1800000>;
296 /* LDO0 is not connected to anything */
300 regulator-compatible = "ldo1";
301 regulator-name = "vdd_ldo1,avdd_pll*";
302 regulator-min-microvolt = <1100000>;
303 regulator-max-microvolt = <1100000>;
309 regulator-compatible = "ldo2";
310 regulator-name = "vdd_ldo2,vdd_rtc";
311 regulator-min-microvolt = <1200000>;
312 regulator-max-microvolt = <1200000>;
315 /* LDO3 is not connected to anything */
319 regulator-compatible = "ldo4";
320 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
321 regulator-min-microvolt = <1800000>;
322 regulator-max-microvolt = <1800000>;
326 ldo5_reg: regulator@9 {
328 regulator-compatible = "ldo5";
329 regulator-name = "vdd_ldo5,vdd_fuse";
330 regulator-min-microvolt = <3300000>;
331 regulator-max-microvolt = <3300000>;
337 regulator-compatible = "ldo6";
338 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
339 regulator-min-microvolt = <2850000>;
340 regulator-max-microvolt = <2850000>;
343 hdmi_vdd_reg: regulator@11 {
345 regulator-compatible = "ldo7";
346 regulator-name = "vdd_ldo7,avdd_hdmi";
347 regulator-min-microvolt = <3300000>;
348 regulator-max-microvolt = <3300000>;
351 hdmi_pll_reg: regulator@12 {
353 regulator-compatible = "ldo8";
354 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
355 regulator-min-microvolt = <1800000>;
356 regulator-max-microvolt = <1800000>;
361 regulator-compatible = "ldo9";
362 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
363 regulator-min-microvolt = <2850000>;
364 regulator-max-microvolt = <2850000>;
370 regulator-compatible = "ldo_rtc";
371 regulator-name = "vdd_rtc_out,vdd_cell";
372 regulator-min-microvolt = <3300000>;
373 regulator-max-microvolt = <3300000>;
379 temperature-sensor@4c {
380 compatible = "national,lm95245";
386 nvidia,suspend-mode = <1>;
387 nvidia,cpu-pwr-good-time = <5000>;
388 nvidia,cpu-pwr-off-time = <5000>;
389 nvidia,core-pwr-good-time = <3845 3845>;
390 nvidia,core-pwr-off-time = <3875>;
391 nvidia,sys-clock-req-active-high;
394 memory-controller@7000f400 {
397 compatible = "nvidia,tegra20-emc-table";
398 clock-frequency = <83250>;
399 nvidia,emc-registers = <0x00000005 0x00000011
400 0x00000004 0x00000002 0x00000004 0x00000004
401 0x00000001 0x0000000a 0x00000002 0x00000002
402 0x00000001 0x00000001 0x00000003 0x00000004
403 0x00000003 0x00000009 0x0000000c 0x0000025f
404 0x00000000 0x00000003 0x00000003 0x00000002
405 0x00000002 0x00000001 0x00000008 0x000000c8
406 0x00000003 0x00000005 0x00000003 0x0000000c
407 0x00000002 0x00000000 0x00000000 0x00000002
408 0x00000000 0x00000000 0x00000083 0x00520006
409 0x00000010 0x00000008 0x00000000 0x00000000
410 0x00000000 0x00000000 0x00000000 0x00000000>;
414 compatible = "nvidia,tegra20-emc-table";
415 clock-frequency = <133200>;
416 nvidia,emc-registers = <0x00000008 0x00000019
417 0x00000006 0x00000002 0x00000004 0x00000004
418 0x00000001 0x0000000a 0x00000002 0x00000002
419 0x00000002 0x00000001 0x00000003 0x00000004
420 0x00000003 0x00000009 0x0000000c 0x0000039f
421 0x00000000 0x00000003 0x00000003 0x00000002
422 0x00000002 0x00000001 0x00000008 0x000000c8
423 0x00000003 0x00000007 0x00000003 0x0000000c
424 0x00000002 0x00000000 0x00000000 0x00000002
425 0x00000000 0x00000000 0x00000083 0x00510006
426 0x00000010 0x00000008 0x00000000 0x00000000
427 0x00000000 0x00000000 0x00000000 0x00000000>;
431 compatible = "nvidia,tegra20-emc-table";
432 clock-frequency = <166500>;
433 nvidia,emc-registers = <0x0000000a 0x00000021
434 0x00000008 0x00000003 0x00000004 0x00000004
435 0x00000002 0x0000000a 0x00000003 0x00000003
436 0x00000002 0x00000001 0x00000003 0x00000004
437 0x00000003 0x00000009 0x0000000c 0x000004df
438 0x00000000 0x00000003 0x00000003 0x00000003
439 0x00000003 0x00000001 0x00000009 0x000000c8
440 0x00000003 0x00000009 0x00000004 0x0000000c
441 0x00000002 0x00000000 0x00000000 0x00000002
442 0x00000000 0x00000000 0x00000083 0x004f0006
443 0x00000010 0x00000008 0x00000000 0x00000000
444 0x00000000 0x00000000 0x00000000 0x00000000>;
448 compatible = "nvidia,tegra20-emc-table";
449 clock-frequency = <333000>;
450 nvidia,emc-registers = <0x00000014 0x00000041
451 0x0000000f 0x00000005 0x00000004 0x00000005
452 0x00000003 0x0000000a 0x00000005 0x00000005
453 0x00000004 0x00000001 0x00000003 0x00000004
454 0x00000003 0x00000009 0x0000000c 0x000009ff
455 0x00000000 0x00000003 0x00000003 0x00000005
456 0x00000005 0x00000001 0x0000000e 0x000000c8
457 0x00000003 0x00000011 0x00000006 0x0000000c
458 0x00000002 0x00000000 0x00000000 0x00000002
459 0x00000000 0x00000000 0x00000083 0x00380006
460 0x00000010 0x00000008 0x00000000 0x00000000
461 0x00000000 0x00000000 0x00000000 0x00000000>;
467 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
473 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
478 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
482 compatible = "simple-bus";
483 #address-cells = <1>;
487 compatible = "fixed-clock";
490 clock-frequency = <32768>;
495 compatible = "simple-bus";
496 #address-cells = <1>;
499 vdd_3v3_reg: regulator@100 {
500 compatible = "regulator-fixed";
502 regulator-name = "vdd_3v3";
503 regulator-min-microvolt = <3300000>;
504 regulator-max-microvolt = <3300000>;
509 compatible = "regulator-fixed";
511 regulator-name = "internal_usb";
512 regulator-min-microvolt = <5000000>;
513 regulator-max-microvolt = <5000000>;
517 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
522 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
523 "nvidia,tegra-audio-wm9712";
524 nvidia,model = "Colibri T20 AC97 Audio";
526 nvidia,audio-routing =
527 "Headphone", "HPOUTL",
528 "Headphone", "HPOUTR",
533 nvidia,ac97-controller = <&ac97>;
535 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
536 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
537 <&tegra_car TEGRA20_CLK_CDEV1>;
538 clock-names = "pll_a", "pll_a_out0", "mclk";