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[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / tegra20-ventana.dts
1 /dts-v1/;
2
3 #include <dt-bindings/input/input.h>
4 #include "tegra20.dtsi"
5
6 / {
7 model = "NVIDIA Tegra20 Ventana evaluation board";
8 compatible = "nvidia,ventana", "nvidia,tegra20";
9
10 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
13 serial0 = &uartd;
14 };
15
16 memory {
17 reg = <0x00000000 0x40000000>;
18 };
19
20 host1x@50000000 {
21 dc@54200000 {
22 rgb {
23 status = "okay";
24
25 nvidia,panel = <&panel>;
26 };
27 };
28
29 hdmi@54280000 {
30 status = "okay";
31
32 vdd-supply = <&hdmi_vdd_reg>;
33 pll-supply = <&hdmi_pll_reg>;
34
35 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
36 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
37 GPIO_ACTIVE_HIGH>;
38 };
39 };
40
41 pinmux@70000014 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&state_default>;
44
45 state_default: pinmux {
46 ata {
47 nvidia,pins = "ata";
48 nvidia,function = "ide";
49 };
50 atb {
51 nvidia,pins = "atb", "gma", "gme";
52 nvidia,function = "sdio4";
53 };
54 atc {
55 nvidia,pins = "atc";
56 nvidia,function = "nand";
57 };
58 atd {
59 nvidia,pins = "atd", "ate", "gmb", "spia",
60 "spib", "spic";
61 nvidia,function = "gmi";
62 };
63 cdev1 {
64 nvidia,pins = "cdev1";
65 nvidia,function = "plla_out";
66 };
67 cdev2 {
68 nvidia,pins = "cdev2";
69 nvidia,function = "pllp_out4";
70 };
71 crtp {
72 nvidia,pins = "crtp", "lm1";
73 nvidia,function = "crt";
74 };
75 csus {
76 nvidia,pins = "csus";
77 nvidia,function = "vi_sensor_clk";
78 };
79 dap1 {
80 nvidia,pins = "dap1";
81 nvidia,function = "dap1";
82 };
83 dap2 {
84 nvidia,pins = "dap2";
85 nvidia,function = "dap2";
86 };
87 dap3 {
88 nvidia,pins = "dap3";
89 nvidia,function = "dap3";
90 };
91 dap4 {
92 nvidia,pins = "dap4";
93 nvidia,function = "dap4";
94 };
95 dta {
96 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
97 nvidia,function = "vi";
98 };
99 dtf {
100 nvidia,pins = "dtf";
101 nvidia,function = "i2c3";
102 };
103 gmc {
104 nvidia,pins = "gmc";
105 nvidia,function = "uartd";
106 };
107 gmd {
108 nvidia,pins = "gmd";
109 nvidia,function = "sflash";
110 };
111 gpu {
112 nvidia,pins = "gpu";
113 nvidia,function = "pwm";
114 };
115 gpu7 {
116 nvidia,pins = "gpu7";
117 nvidia,function = "rtck";
118 };
119 gpv {
120 nvidia,pins = "gpv", "slxa", "slxk";
121 nvidia,function = "pcie";
122 };
123 hdint {
124 nvidia,pins = "hdint";
125 nvidia,function = "hdmi";
126 };
127 i2cp {
128 nvidia,pins = "i2cp";
129 nvidia,function = "i2cp";
130 };
131 irrx {
132 nvidia,pins = "irrx", "irtx";
133 nvidia,function = "uartb";
134 };
135 kbca {
136 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
137 "kbce", "kbcf";
138 nvidia,function = "kbc";
139 };
140 lcsn {
141 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
142 "lsdi", "lvp0";
143 nvidia,function = "rsvd4";
144 };
145 ld0 {
146 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
147 "ld5", "ld6", "ld7", "ld8", "ld9",
148 "ld10", "ld11", "ld12", "ld13", "ld14",
149 "ld15", "ld16", "ld17", "ldi", "lhp0",
150 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
151 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
152 "lspi", "lvp1", "lvs";
153 nvidia,function = "displaya";
154 };
155 owc {
156 nvidia,pins = "owc", "spdi", "spdo", "uac";
157 nvidia,function = "rsvd2";
158 };
159 pmc {
160 nvidia,pins = "pmc";
161 nvidia,function = "pwr_on";
162 };
163 rm {
164 nvidia,pins = "rm";
165 nvidia,function = "i2c1";
166 };
167 sdb {
168 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
169 nvidia,function = "sdio3";
170 };
171 sdio1 {
172 nvidia,pins = "sdio1";
173 nvidia,function = "sdio1";
174 };
175 slxd {
176 nvidia,pins = "slxd";
177 nvidia,function = "spdif";
178 };
179 spid {
180 nvidia,pins = "spid", "spie", "spif";
181 nvidia,function = "spi1";
182 };
183 spig {
184 nvidia,pins = "spig", "spih";
185 nvidia,function = "spi2_alt";
186 };
187 uaa {
188 nvidia,pins = "uaa", "uab", "uda";
189 nvidia,function = "ulpi";
190 };
191 uad {
192 nvidia,pins = "uad";
193 nvidia,function = "irda";
194 };
195 uca {
196 nvidia,pins = "uca", "ucb";
197 nvidia,function = "uartc";
198 };
199 conf_ata {
200 nvidia,pins = "ata", "atb", "atc", "atd",
201 "cdev1", "cdev2", "dap1", "dap2",
202 "dap4", "ddc", "dtf", "gma", "gmc",
203 "gme", "gpu", "gpu7", "i2cp", "irrx",
204 "irtx", "pta", "rm", "sdc", "sdd",
205 "slxc", "slxd", "slxk", "spdi", "spdo",
206 "uac", "uad", "uca", "ucb", "uda";
207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
209 };
210 conf_ate {
211 nvidia,pins = "ate", "csus", "dap3", "gmd",
212 "gpv", "owc", "spia", "spib", "spic",
213 "spid", "spie", "spig";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_ENABLE>;
216 };
217 conf_ck32 {
218 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
219 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
221 };
222 conf_crtp {
223 nvidia,pins = "crtp", "gmb", "slxa", "spih";
224 nvidia,pull = <TEGRA_PIN_PULL_UP>;
225 nvidia,tristate = <TEGRA_PIN_ENABLE>;
226 };
227 conf_dta {
228 nvidia,pins = "dta", "dtb", "dtc", "dtd";
229 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
230 nvidia,tristate = <TEGRA_PIN_DISABLE>;
231 };
232 conf_dte {
233 nvidia,pins = "dte", "spif";
234 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
236 };
237 conf_hdint {
238 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
239 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
241 };
242 conf_kbca {
243 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
244 "kbce", "kbcf", "sdio1", "uaa", "uab";
245 nvidia,pull = <TEGRA_PIN_PULL_UP>;
246 nvidia,tristate = <TEGRA_PIN_DISABLE>;
247 };
248 conf_lc {
249 nvidia,pins = "lc", "ls";
250 nvidia,pull = <TEGRA_PIN_PULL_UP>;
251 };
252 conf_ld0 {
253 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
254 "ld5", "ld6", "ld7", "ld8", "ld9",
255 "ld10", "ld11", "ld12", "ld13", "ld14",
256 "ld15", "ld16", "ld17", "ldi", "lhp0",
257 "lhp1", "lhp2", "lhs", "lm0", "lpp",
258 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
259 "lvp1", "lvs", "pmc", "sdb";
260 nvidia,tristate = <TEGRA_PIN_DISABLE>;
261 };
262 conf_ld17_0 {
263 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
264 "ld23_22";
265 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
266 };
267 drive_sdio1 {
268 nvidia,pins = "drive_sdio1";
269 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
270 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
271 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
272 nvidia,pull-down-strength = <31>;
273 nvidia,pull-up-strength = <31>;
274 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
275 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
276 };
277 };
278
279 state_i2cmux_ddc: pinmux_i2cmux_ddc {
280 ddc {
281 nvidia,pins = "ddc";
282 nvidia,function = "i2c2";
283 };
284 pta {
285 nvidia,pins = "pta";
286 nvidia,function = "rsvd4";
287 };
288 };
289
290 state_i2cmux_pta: pinmux_i2cmux_pta {
291 ddc {
292 nvidia,pins = "ddc";
293 nvidia,function = "rsvd4";
294 };
295 pta {
296 nvidia,pins = "pta";
297 nvidia,function = "i2c2";
298 };
299 };
300
301 state_i2cmux_idle: pinmux_i2cmux_idle {
302 ddc {
303 nvidia,pins = "ddc";
304 nvidia,function = "rsvd4";
305 };
306 pta {
307 nvidia,pins = "pta";
308 nvidia,function = "rsvd4";
309 };
310 };
311 };
312
313 i2s@70002800 {
314 status = "okay";
315 };
316
317 serial@70006300 {
318 status = "okay";
319 };
320
321 pwm: pwm@7000a000 {
322 status = "okay";
323 };
324
325 i2c@7000c000 {
326 status = "okay";
327 clock-frequency = <400000>;
328
329 wm8903: wm8903@1a {
330 compatible = "wlf,wm8903";
331 reg = <0x1a>;
332 interrupt-parent = <&gpio>;
333 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
334
335 gpio-controller;
336 #gpio-cells = <2>;
337
338 micdet-cfg = <0>;
339 micdet-delay = <100>;
340 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
341 };
342
343 /* ALS and proximity sensor */
344 isl29018@44 {
345 compatible = "isil,isl29018";
346 reg = <0x44>;
347 interrupt-parent = <&gpio>;
348 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
349 };
350 };
351
352 i2c@7000c400 {
353 status = "okay";
354 clock-frequency = <100000>;
355 };
356
357 i2cmux {
358 compatible = "i2c-mux-pinctrl";
359 #address-cells = <1>;
360 #size-cells = <0>;
361
362 i2c-parent = <&{/i2c@7000c400}>;
363
364 pinctrl-names = "ddc", "pta", "idle";
365 pinctrl-0 = <&state_i2cmux_ddc>;
366 pinctrl-1 = <&state_i2cmux_pta>;
367 pinctrl-2 = <&state_i2cmux_idle>;
368
369 hdmi_ddc: i2c@0 {
370 reg = <0>;
371 #address-cells = <1>;
372 #size-cells = <0>;
373 };
374
375 lvds_ddc: i2c@1 {
376 reg = <1>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 };
380 };
381
382 i2c@7000c500 {
383 status = "okay";
384 clock-frequency = <400000>;
385 };
386
387 i2c@7000d000 {
388 status = "okay";
389 clock-frequency = <400000>;
390
391 pmic: tps6586x@34 {
392 compatible = "ti,tps6586x";
393 reg = <0x34>;
394 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
395
396 ti,system-power-controller;
397
398 #gpio-cells = <2>;
399 gpio-controller;
400
401 sys-supply = <&vdd_5v0_reg>;
402 vin-sm0-supply = <&sys_reg>;
403 vin-sm1-supply = <&sys_reg>;
404 vin-sm2-supply = <&sys_reg>;
405 vinldo01-supply = <&sm2_reg>;
406 vinldo23-supply = <&sm2_reg>;
407 vinldo4-supply = <&sm2_reg>;
408 vinldo678-supply = <&sm2_reg>;
409 vinldo9-supply = <&sm2_reg>;
410
411 regulators {
412 sys_reg: sys {
413 regulator-name = "vdd_sys";
414 regulator-always-on;
415 };
416
417 sm0 {
418 regulator-name = "vdd_sm0,vdd_core";
419 regulator-min-microvolt = <1200000>;
420 regulator-max-microvolt = <1200000>;
421 regulator-always-on;
422 };
423
424 sm1 {
425 regulator-name = "vdd_sm1,vdd_cpu";
426 regulator-min-microvolt = <1000000>;
427 regulator-max-microvolt = <1000000>;
428 regulator-always-on;
429 };
430
431 sm2_reg: sm2 {
432 regulator-name = "vdd_sm2,vin_ldo*";
433 regulator-min-microvolt = <3700000>;
434 regulator-max-microvolt = <3700000>;
435 regulator-always-on;
436 };
437
438 /* LDO0 is not connected to anything */
439
440 ldo1 {
441 regulator-name = "vdd_ldo1,avdd_pll*";
442 regulator-min-microvolt = <1100000>;
443 regulator-max-microvolt = <1100000>;
444 regulator-always-on;
445 };
446
447 ldo2 {
448 regulator-name = "vdd_ldo2,vdd_rtc";
449 regulator-min-microvolt = <1200000>;
450 regulator-max-microvolt = <1200000>;
451 };
452
453 ldo3 {
454 regulator-name = "vdd_ldo3,avdd_usb*";
455 regulator-min-microvolt = <3300000>;
456 regulator-max-microvolt = <3300000>;
457 regulator-always-on;
458 };
459
460 ldo4 {
461 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
462 regulator-min-microvolt = <1800000>;
463 regulator-max-microvolt = <1800000>;
464 regulator-always-on;
465 };
466
467 ldo5 {
468 regulator-name = "vdd_ldo5,vcore_mmc";
469 regulator-min-microvolt = <2850000>;
470 regulator-max-microvolt = <2850000>;
471 regulator-always-on;
472 };
473
474 ldo6 {
475 regulator-name = "vdd_ldo6,avdd_vdac";
476 regulator-min-microvolt = <1800000>;
477 regulator-max-microvolt = <1800000>;
478 };
479
480 hdmi_vdd_reg: ldo7 {
481 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
482 regulator-min-microvolt = <3300000>;
483 regulator-max-microvolt = <3300000>;
484 };
485
486 hdmi_pll_reg: ldo8 {
487 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
488 regulator-min-microvolt = <1800000>;
489 regulator-max-microvolt = <1800000>;
490 };
491
492 ldo9 {
493 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
494 regulator-min-microvolt = <2850000>;
495 regulator-max-microvolt = <2850000>;
496 regulator-always-on;
497 };
498
499 ldo_rtc {
500 regulator-name = "vdd_rtc_out,vdd_cell";
501 regulator-min-microvolt = <3300000>;
502 regulator-max-microvolt = <3300000>;
503 regulator-always-on;
504 };
505 };
506 };
507
508 temperature-sensor@4c {
509 compatible = "onnn,nct1008";
510 reg = <0x4c>;
511 };
512 };
513
514 pmc@7000e400 {
515 nvidia,invert-interrupt;
516 nvidia,suspend-mode = <1>;
517 nvidia,cpu-pwr-good-time = <2000>;
518 nvidia,cpu-pwr-off-time = <100>;
519 nvidia,core-pwr-good-time = <3845 3845>;
520 nvidia,core-pwr-off-time = <458>;
521 nvidia,sys-clock-req-active-high;
522 };
523
524 usb@c5000000 {
525 status = "okay";
526 };
527
528 usb-phy@c5000000 {
529 status = "okay";
530 };
531
532 usb@c5004000 {
533 status = "okay";
534 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
535 GPIO_ACTIVE_LOW>;
536 };
537
538 usb-phy@c5004000 {
539 status = "okay";
540 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
541 GPIO_ACTIVE_LOW>;
542 };
543
544 usb@c5008000 {
545 status = "okay";
546 };
547
548 usb-phy@c5008000 {
549 status = "okay";
550 };
551
552 sdhci@c8000000 {
553 status = "okay";
554 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
555 bus-width = <4>;
556 keep-power-in-suspend;
557 };
558
559 sdhci@c8000400 {
560 status = "okay";
561 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
562 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
563 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
564 bus-width = <4>;
565 };
566
567 sdhci@c8000600 {
568 status = "okay";
569 bus-width = <8>;
570 non-removable;
571 };
572
573 backlight: backlight {
574 compatible = "pwm-backlight";
575
576 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
577 power-supply = <&vdd_bl_reg>;
578 pwms = <&pwm 2 5000000>;
579
580 brightness-levels = <0 4 8 16 32 64 128 255>;
581 default-brightness-level = <6>;
582 };
583
584 clocks {
585 compatible = "simple-bus";
586 #address-cells = <1>;
587 #size-cells = <0>;
588
589 clk32k_in: clock@0 {
590 compatible = "fixed-clock";
591 reg=<0>;
592 #clock-cells = <0>;
593 clock-frequency = <32768>;
594 };
595 };
596
597 gpio-keys {
598 compatible = "gpio-keys";
599
600 power {
601 label = "Power";
602 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
603 linux,code = <KEY_POWER>;
604 gpio-key,wakeup;
605 };
606 };
607
608 panel: panel {
609 compatible = "chunghwa,claa101wa01a", "simple-panel";
610
611 power-supply = <&vdd_pnl_reg>;
612 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
613
614 backlight = <&backlight>;
615 ddc-i2c-bus = <&lvds_ddc>;
616 };
617
618 regulators {
619 compatible = "simple-bus";
620 #address-cells = <1>;
621 #size-cells = <0>;
622
623 vdd_5v0_reg: regulator@0 {
624 compatible = "regulator-fixed";
625 reg = <0>;
626 regulator-name = "vdd_5v0";
627 regulator-min-microvolt = <5000000>;
628 regulator-max-microvolt = <5000000>;
629 regulator-always-on;
630 };
631
632 regulator@1 {
633 compatible = "regulator-fixed";
634 reg = <1>;
635 regulator-name = "vdd_1v5";
636 regulator-min-microvolt = <1500000>;
637 regulator-max-microvolt = <1500000>;
638 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
639 };
640
641 regulator@2 {
642 compatible = "regulator-fixed";
643 reg = <2>;
644 regulator-name = "vdd_1v2";
645 regulator-min-microvolt = <1200000>;
646 regulator-max-microvolt = <1200000>;
647 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
648 enable-active-high;
649 };
650
651 vdd_pnl_reg: regulator@3 {
652 compatible = "regulator-fixed";
653 reg = <3>;
654 regulator-name = "vdd_pnl";
655 regulator-min-microvolt = <2800000>;
656 regulator-max-microvolt = <2800000>;
657 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
658 enable-active-high;
659 };
660
661 vdd_bl_reg: regulator@4 {
662 compatible = "regulator-fixed";
663 reg = <4>;
664 regulator-name = "vdd_bl";
665 regulator-min-microvolt = <2800000>;
666 regulator-max-microvolt = <2800000>;
667 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
668 enable-active-high;
669 };
670 };
671
672 sound {
673 compatible = "nvidia,tegra-audio-wm8903-ventana",
674 "nvidia,tegra-audio-wm8903";
675 nvidia,model = "NVIDIA Tegra Ventana";
676
677 nvidia,audio-routing =
678 "Headphone Jack", "HPOUTR",
679 "Headphone Jack", "HPOUTL",
680 "Int Spk", "ROP",
681 "Int Spk", "RON",
682 "Int Spk", "LOP",
683 "Int Spk", "LON",
684 "Mic Jack", "MICBIAS",
685 "IN1L", "Mic Jack";
686
687 nvidia,i2s-controller = <&tegra_i2s1>;
688 nvidia,audio-codec = <&wm8903>;
689
690 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
691 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
692 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
693 GPIO_ACTIVE_HIGH>;
694 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
695 GPIO_ACTIVE_HIGH>;
696
697 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
698 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
699 <&tegra_car TEGRA20_CLK_CDEV1>;
700 clock-names = "pll_a", "pll_a_out0", "mclk";
701 };
702 };