arch/arm/boot/dts/tegra20.dtsi

   1 #include <dt-bindings/clock/tegra20-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra20";
  10         interrupt-parent = <&lic>;
  11
  12         host1x@50000000 {
  13                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  14                 reg = <0x50000000 0x00024000>;
  15                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  16                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  17                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  18                 resets = <&tegra_car 28>;
  19                 reset-names = "host1x";
  20
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23
  24                 ranges = <0x54000000 0x54000000 0x04000000>;
  25
  26                 mpe@54040000 {
  27                         compatible = "nvidia,tegra20-mpe";
  28                         reg = <0x54040000 0x00040000>;
  29                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  30                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
  31                         resets = <&tegra_car 60>;
  32                         reset-names = "mpe";
  33                 };
  34
  35                 vi@54080000 {
  36                         compatible = "nvidia,tegra20-vi";
  37                         reg = <0x54080000 0x00040000>;
  38                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  39                         clocks = <&tegra_car TEGRA20_CLK_VI>;
  40                         resets = <&tegra_car 20>;
  41                         reset-names = "vi";
  42                 };
  43
  44                 epp@540c0000 {
  45                         compatible = "nvidia,tegra20-epp";
  46                         reg = <0x540c0000 0x00040000>;
  47                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  48                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  49                         resets = <&tegra_car 19>;
  50                         reset-names = "epp";
  51                 };
  52
  53                 isp@54100000 {
  54                         compatible = "nvidia,tegra20-isp";
  55                         reg = <0x54100000 0x00040000>;
  56                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  57                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
  58                         resets = <&tegra_car 23>;
  59                         reset-names = "isp";
  60                 };
  61
  62                 gr2d@54140000 {
  63                         compatible = "nvidia,tegra20-gr2d";
  64                         reg = <0x54140000 0x00040000>;
  65                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  66                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
  67                         resets = <&tegra_car 21>;
  68                         reset-names = "2d";
  69                 };
  70
  71                 gr3d@54180000 {
  72                         compatible = "nvidia,tegra20-gr3d";
  73                         reg = <0x54180000 0x00040000>;
  74                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
  75                         resets = <&tegra_car 24>;
  76                         reset-names = "3d";
  77                 };
  78
  79                 dc@54200000 {
  80                         compatible = "nvidia,tegra20-dc";
  81                         reg = <0x54200000 0x00040000>;
  82                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  83                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
  84                                  <&tegra_car TEGRA20_CLK_PLL_P>;
  85                         clock-names = "dc", "parent";
  86                         resets = <&tegra_car 27>;
  87                         reset-names = "dc";
  88
  89                         nvidia,head = <0>;
  90
  91                         rgb {
  92                                 status = "disabled";
  93                         };
  94                 };
  95
  96                 dc@54240000 {
  97                         compatible = "nvidia,tegra20-dc";
  98                         reg = <0x54240000 0x00040000>;
  99                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 100                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 101                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 102                         clock-names = "dc", "parent";
 103                         resets = <&tegra_car 26>;
 104                         reset-names = "dc";
 105
 106                         nvidia,head = <1>;
 107
 108                         rgb {
 109                                 status = "disabled";
 110                         };
 111                 };
 112
 113                 hdmi@54280000 {
 114                         compatible = "nvidia,tegra20-hdmi";
 115                         reg = <0x54280000 0x00040000>;
 116                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 117                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 118                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 119                         clock-names = "hdmi", "parent";
 120                         resets = <&tegra_car 51>;
 121                         reset-names = "hdmi";
 122                         status = "disabled";
 123                 };
 124
 125                 tvo@542c0000 {
 126                         compatible = "nvidia,tegra20-tvo";
 127                         reg = <0x542c0000 0x00040000>;
 128                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 129                         clocks = <&tegra_car TEGRA20_CLK_TVO>;
 130                         status = "disabled";
 131                 };
 132
 133                 dsi@54300000 {
 134                         compatible = "nvidia,tegra20-dsi";
 135                         reg = <0x54300000 0x00040000>;
 136                         clocks = <&tegra_car TEGRA20_CLK_DSI>;
 137                         resets = <&tegra_car 48>;
 138                         reset-names = "dsi";
 139                         status = "disabled";
 140                 };
 141         };
 142
 143         timer@50040600 {
 144                 compatible = "arm,cortex-a9-twd-timer";
 145                 interrupt-parent = <&intc>;
 146                 reg = <0x50040600 0x20>;
 147                 interrupts = <GIC_PPI 13
 148                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 149                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
 150         };
 151
 152         intc: interrupt-controller@50041000 {
 153                 compatible = "arm,cortex-a9-gic";
 154                 reg = <0x50041000 0x1000
 155                        0x50040100 0x0100>;
 156                 interrupt-controller;
 157                 #interrupt-cells = <3>;
 158                 interrupt-parent = <&intc>;
 159         };
 160
 161         cache-controller@50043000 {
 162                 compatible = "arm,pl310-cache";
 163                 reg = <0x50043000 0x1000>;
 164                 arm,data-latency = <5 5 2>;
 165                 arm,tag-latency = <4 4 2>;
 166                 cache-unified;
 167                 cache-level = <2>;
 168         };
 169
 170         lic: interrupt-controller@60004000 {
 171                 compatible = "nvidia,tegra20-ictlr";
 172                 reg = <0x60004000 0x100>,
 173                       <0x60004100 0x50>,
 174                       <0x60004200 0x50>,
 175                       <0x60004300 0x50>;
 176                 interrupt-controller;
 177                 #interrupt-cells = <3>;
 178                 interrupt-parent = <&intc>;
 179         };
 180
 181         timer@60005000 {
 182                 compatible = "nvidia,tegra20-timer";
 183                 reg = <0x60005000 0x60>;
 184                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 189         };
 190
 191         tegra_car: clock@60006000 {
 192                 compatible = "nvidia,tegra20-car";
 193                 reg = <0x60006000 0x1000>;
 194                 #clock-cells = <1>;
 195                 #reset-cells = <1>;
 196         };
 197
 198         flow-controller@60007000 {
 199                 compatible = "nvidia,tegra20-flowctrl";
 200                 reg = <0x60007000 0x1000>;
 201         };
 202
 203         apbdma: dma@6000a000 {
 204                 compatible = "nvidia,tegra20-apbdma";
 205                 reg = <0x6000a000 0x1200>;
 206                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 223                 resets = <&tegra_car 34>;
 224                 reset-names = "dma";
 225                 #dma-cells = <1>;
 226         };
 227
 228         ahb@6000c000 {
 229                 compatible = "nvidia,tegra20-ahb";
 230                 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
 231         };
 232
 233         gpio: gpio@6000d000 {
 234                 compatible = "nvidia,tegra20-gpio";
 235                 reg = <0x6000d000 0x1000>;
 236                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 243                 #gpio-cells = <2>;
 244                 gpio-controller;
 245                 #interrupt-cells = <2>;
 246                 interrupt-controller;
 247                 /*
 248                 gpio-ranges = <&pinmux 0 0 224>;
 249                 */
 250         };
 251
 252         apbmisc@70000800 {
 253                 compatible = "nvidia,tegra20-apbmisc";
 254                 reg = <0x70000800 0x64   /* Chip revision */
 255                        0x70000008 0x04>; /* Strapping options */
 256         };
 257
 258         pinmux: pinmux@70000014 {
 259                 compatible = "nvidia,tegra20-pinmux";
 260                 reg = <0x70000014 0x10   /* Tri-state registers */
 261                        0x70000080 0x20   /* Mux registers */
 262                        0x700000a0 0x14   /* Pull-up/down registers */
 263                        0x70000868 0xa8>; /* Pad control registers */
 264         };
 265
 266         das@70000c00 {
 267                 compatible = "nvidia,tegra20-das";
 268                 reg = <0x70000c00 0x80>;
 269         };
 270
 271         tegra_ac97: ac97@70002000 {
 272                 compatible = "nvidia,tegra20-ac97";
 273                 reg = <0x70002000 0x200>;
 274                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 275                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
 276                 resets = <&tegra_car 3>;
 277                 reset-names = "ac97";
 278                 dmas = <&apbdma 12>, <&apbdma 12>;
 279                 dma-names = "rx", "tx";
 280                 status = "disabled";
 281         };
 282
 283         tegra_i2s1: i2s@70002800 {
 284                 compatible = "nvidia,tegra20-i2s";
 285                 reg = <0x70002800 0x200>;
 286                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 287                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 288                 resets = <&tegra_car 11>;
 289                 reset-names = "i2s";
 290                 dmas = <&apbdma 2>, <&apbdma 2>;
 291                 dma-names = "rx", "tx";
 292                 status = "disabled";
 293         };
 294
 295         tegra_i2s2: i2s@70002a00 {
 296                 compatible = "nvidia,tegra20-i2s";
 297                 reg = <0x70002a00 0x200>;
 298                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 300                 resets = <&tegra_car 18>;
 301                 reset-names = "i2s";
 302                 dmas = <&apbdma 1>, <&apbdma 1>;
 303                 dma-names = "rx", "tx";
 304                 status = "disabled";
 305         };
 306
 307         /*
 308          * There are two serial driver i.e. 8250 based simple serial
 309          * driver and APB DMA based serial driver for higher baudrate
 310          * and performace. To enable the 8250 based driver, the compatible
 311          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 312          * driver, the comptible is "nvidia,tegra20-hsuart".
 313          */
 314         uarta: serial@70006000 {
 315                 compatible = "nvidia,tegra20-uart";
 316                 reg = <0x70006000 0x40>;
 317                 reg-shift = <2>;
 318                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 320                 resets = <&tegra_car 6>;
 321                 reset-names = "serial";
 322                 dmas = <&apbdma 8>, <&apbdma 8>;
 323                 dma-names = "rx", "tx";
 324                 status = "disabled";
 325         };
 326
 327         uartb: serial@70006040 {
 328                 compatible = "nvidia,tegra20-uart";
 329                 reg = <0x70006040 0x40>;
 330                 reg-shift = <2>;
 331                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 333                 resets = <&tegra_car 7>;
 334                 reset-names = "serial";
 335                 dmas = <&apbdma 9>, <&apbdma 9>;
 336                 dma-names = "rx", "tx";
 337                 status = "disabled";
 338         };
 339
 340         uartc: serial@70006200 {
 341                 compatible = "nvidia,tegra20-uart";
 342                 reg = <0x70006200 0x100>;
 343                 reg-shift = <2>;
 344                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 345                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 346                 resets = <&tegra_car 55>;
 347                 reset-names = "serial";
 348                 dmas = <&apbdma 10>, <&apbdma 10>;
 349                 dma-names = "rx", "tx";
 350                 status = "disabled";
 351         };
 352
 353         uartd: serial@70006300 {
 354                 compatible = "nvidia,tegra20-uart";
 355                 reg = <0x70006300 0x100>;
 356                 reg-shift = <2>;
 357                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 359                 resets = <&tegra_car 65>;
 360                 reset-names = "serial";
 361                 dmas = <&apbdma 19>, <&apbdma 19>;
 362                 dma-names = "rx", "tx";
 363                 status = "disabled";
 364         };
 365
 366         uarte: serial@70006400 {
 367                 compatible = "nvidia,tegra20-uart";
 368                 reg = <0x70006400 0x100>;
 369                 reg-shift = <2>;
 370                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 371                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 372                 resets = <&tegra_car 66>;
 373                 reset-names = "serial";
 374                 dmas = <&apbdma 20>, <&apbdma 20>;
 375                 dma-names = "rx", "tx";
 376                 status = "disabled";
 377         };
 378
 379         pwm: pwm@7000a000 {
 380                 compatible = "nvidia,tegra20-pwm";
 381                 reg = <0x7000a000 0x100>;
 382                 #pwm-cells = <2>;
 383                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
 384                 resets = <&tegra_car 17>;
 385                 reset-names = "pwm";
 386                 status = "disabled";
 387         };
 388
 389         rtc@7000e000 {
 390                 compatible = "nvidia,tegra20-rtc";
 391                 reg = <0x7000e000 0x100>;
 392                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&tegra_car TEGRA20_CLK_RTC>;
 394         };
 395
 396         i2c@7000c000 {
 397                 compatible = "nvidia,tegra20-i2c";
 398                 reg = <0x7000c000 0x100>;
 399                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 403                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 404                 clock-names = "div-clk", "fast-clk";
 405                 resets = <&tegra_car 12>;
 406                 reset-names = "i2c";
 407                 dmas = <&apbdma 21>, <&apbdma 21>;
 408                 dma-names = "rx", "tx";
 409                 status = "disabled";
 410         };
 411
 412         spi@7000c380 {
 413                 compatible = "nvidia,tegra20-sflash";
 414                 reg = <0x7000c380 0x80>;
 415                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
 419                 resets = <&tegra_car 43>;
 420                 reset-names = "spi";
 421                 dmas = <&apbdma 11>, <&apbdma 11>;
 422                 dma-names = "rx", "tx";
 423                 status = "disabled";
 424         };
 425
 426         i2c@7000c400 {
 427                 compatible = "nvidia,tegra20-i2c";
 428                 reg = <0x7000c400 0x100>;
 429                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 433                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 434                 clock-names = "div-clk", "fast-clk";
 435                 resets = <&tegra_car 54>;
 436                 reset-names = "i2c";
 437                 dmas = <&apbdma 22>, <&apbdma 22>;
 438                 dma-names = "rx", "tx";
 439                 status = "disabled";
 440         };
 441
 442         i2c@7000c500 {
 443                 compatible = "nvidia,tegra20-i2c";
 444                 reg = <0x7000c500 0x100>;
 445                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 449                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 450                 clock-names = "div-clk", "fast-clk";
 451                 resets = <&tegra_car 67>;
 452                 reset-names = "i2c";
 453                 dmas = <&apbdma 23>, <&apbdma 23>;
 454                 dma-names = "rx", "tx";
 455                 status = "disabled";
 456         };
 457
 458         i2c@7000d000 {
 459                 compatible = "nvidia,tegra20-i2c-dvc";
 460                 reg = <0x7000d000 0x200>;
 461                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
 465                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 466                 clock-names = "div-clk", "fast-clk";
 467                 resets = <&tegra_car 47>;
 468                 reset-names = "i2c";
 469                 dmas = <&apbdma 24>, <&apbdma 24>;
 470                 dma-names = "rx", "tx";
 471                 status = "disabled";
 472         };
 473
 474         spi@7000d400 {
 475                 compatible = "nvidia,tegra20-slink";
 476                 reg = <0x7000d400 0x200>;
 477                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 481                 resets = <&tegra_car 41>;
 482                 reset-names = "spi";
 483                 dmas = <&apbdma 15>, <&apbdma 15>;
 484                 dma-names = "rx", "tx";
 485                 status = "disabled";
 486         };
 487
 488         spi@7000d600 {
 489                 compatible = "nvidia,tegra20-slink";
 490                 reg = <0x7000d600 0x200>;
 491                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 492                 #address-cells = <1>;
 493                 #size-cells = <0>;
 494                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 495                 resets = <&tegra_car 44>;
 496                 reset-names = "spi";
 497                 dmas = <&apbdma 16>, <&apbdma 16>;
 498                 dma-names = "rx", "tx";
 499                 status = "disabled";
 500         };
 501
 502         spi@7000d800 {
 503                 compatible = "nvidia,tegra20-slink";
 504                 reg = <0x7000d800 0x200>;
 505                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 509                 resets = <&tegra_car 46>;
 510                 reset-names = "spi";
 511                 dmas = <&apbdma 17>, <&apbdma 17>;
 512                 dma-names = "rx", "tx";
 513                 status = "disabled";
 514         };
 515
 516         spi@7000da00 {
 517                 compatible = "nvidia,tegra20-slink";
 518                 reg = <0x7000da00 0x200>;
 519                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 523                 resets = <&tegra_car 68>;
 524                 reset-names = "spi";
 525                 dmas = <&apbdma 18>, <&apbdma 18>;
 526                 dma-names = "rx", "tx";
 527                 status = "disabled";
 528         };
 529
 530         kbc@7000e200 {
 531                 compatible = "nvidia,tegra20-kbc";
 532                 reg = <0x7000e200 0x100>;
 533                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 534                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
 535                 resets = <&tegra_car 36>;
 536                 reset-names = "kbc";
 537                 status = "disabled";
 538         };
 539
 540         pmc@7000e400 {
 541                 compatible = "nvidia,tegra20-pmc";
 542                 reg = <0x7000e400 0x400>;
 543                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 544                 clock-names = "pclk", "clk32k_in";
 545         };
 546
 547         memory-controller@7000f000 {
 548                 compatible = "nvidia,tegra20-mc";
 549                 reg = <0x7000f000 0x024
 550                        0x7000f03c 0x3c4>;
 551                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 552         };
 553
 554         iommu@7000f024 {
 555                 compatible = "nvidia,tegra20-gart";
 556                 reg = <0x7000f024 0x00000018    /* controller registers */
 557                        0x58000000 0x02000000>;  /* GART aperture */
 558         };
 559
 560         memory-controller@7000f400 {
 561                 compatible = "nvidia,tegra20-emc";
 562                 reg = <0x7000f400 0x200>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565         };
 566
 567         fuse@7000f800 {
 568                 compatible = "nvidia,tegra20-efuse";
 569                 reg = <0x7000f800 0x400>;
 570                 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
 571                 clock-names = "fuse";
 572                 resets = <&tegra_car 39>;
 573                 reset-names = "fuse";
 574         };
 575
 576         pcie-controller@80003000 {
 577                 compatible = "nvidia,tegra20-pcie";
 578                 device_type = "pci";
 579                 reg = <0x80003000 0x00000800   /* PADS registers */
 580                        0x80003800 0x00000200   /* AFI registers */
 581                        0x90000000 0x10000000>; /* configuration space */
 582                 reg-names = "pads", "afi", "cs";
 583                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
 584                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 585                 interrupt-names = "intr", "msi";
 586
 587                 #interrupt-cells = <1>;
 588                 interrupt-map-mask = <0 0 0 0>;
 589                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 590
 591                 bus-range = <0x00 0xff>;
 592                 #address-cells = <3>;
 593                 #size-cells = <2>;
 594
 595                 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
 596                           0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
 597                           0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
 598                           0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
 599                           0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
 600
 601                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
 602                          <&tegra_car TEGRA20_CLK_AFI>,
 603                          <&tegra_car TEGRA20_CLK_PLL_E>;
 604                 clock-names = "pex", "afi", "pll_e";
 605                 resets = <&tegra_car 70>,
 606                          <&tegra_car 72>,
 607                          <&tegra_car 74>;
 608                 reset-names = "pex", "afi", "pcie_x";
 609                 status = "disabled";
 610
 611                 pci@1,0 {
 612                         device_type = "pci";
 613                         assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
 614                         reg = <0x000800 0 0 0 0>;
 615                         status = "disabled";
 616
 617                         #address-cells = <3>;
 618                         #size-cells = <2>;
 619                         ranges;
 620
 621                         nvidia,num-lanes = <2>;
 622                 };
 623
 624                 pci@2,0 {
 625                         device_type = "pci";
 626                         assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
 627                         reg = <0x001000 0 0 0 0>;
 628                         status = "disabled";
 629
 630                         #address-cells = <3>;
 631                         #size-cells = <2>;
 632                         ranges;
 633
 634                         nvidia,num-lanes = <2>;
 635                 };
 636         };
 637
 638         usb@c5000000 {
 639                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 640                 reg = <0xc5000000 0x4000>;
 641                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 642                 phy_type = "utmi";
 643                 nvidia,has-legacy-mode;
 644                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
 645                 resets = <&tegra_car 22>;
 646                 reset-names = "usb";
 647                 nvidia,needs-double-reset;
 648                 nvidia,phy = <&phy1>;
 649                 status = "disabled";
 650         };
 651
 652         phy1: usb-phy@c5000000 {
 653                 compatible = "nvidia,tegra20-usb-phy";
 654                 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
 655                 phy_type = "utmi";
 656                 clocks = <&tegra_car TEGRA20_CLK_USBD>,
 657                          <&tegra_car TEGRA20_CLK_PLL_U>,
 658                          <&tegra_car TEGRA20_CLK_CLK_M>,
 659                          <&tegra_car TEGRA20_CLK_USBD>;
 660                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 661                 resets = <&tegra_car 22>, <&tegra_car 22>;
 662                 reset-names = "usb", "utmi-pads";
 663                 nvidia,has-legacy-mode;
 664                 nvidia,hssync-start-delay = <9>;
 665                 nvidia,idle-wait-delay = <17>;
 666                 nvidia,elastic-limit = <16>;
 667                 nvidia,term-range-adj = <6>;
 668                 nvidia,xcvr-setup = <9>;
 669                 nvidia,xcvr-lsfslew = <1>;
 670                 nvidia,xcvr-lsrslew = <1>;
 671                 nvidia,has-utmi-pad-registers;
 672                 status = "disabled";
 673         };
 674
 675         usb@c5004000 {
 676                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 677                 reg = <0xc5004000 0x4000>;
 678                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 679                 phy_type = "ulpi";
 680                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
 681                 resets = <&tegra_car 58>;
 682                 reset-names = "usb";
 683                 nvidia,phy = <&phy2>;
 684                 status = "disabled";
 685         };
 686
 687         phy2: usb-phy@c5004000 {
 688                 compatible = "nvidia,tegra20-usb-phy";
 689                 reg = <0xc5004000 0x4000>;
 690                 phy_type = "ulpi";
 691                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
 692                          <&tegra_car TEGRA20_CLK_PLL_U>,
 693                          <&tegra_car TEGRA20_CLK_CDEV2>;
 694                 clock-names = "reg", "pll_u", "ulpi-link";
 695                 resets = <&tegra_car 58>, <&tegra_car 22>;
 696                 reset-names = "usb", "utmi-pads";
 697                 status = "disabled";
 698         };
 699
 700         usb@c5008000 {
 701                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 702                 reg = <0xc5008000 0x4000>;
 703                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 704                 phy_type = "utmi";
 705                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
 706                 resets = <&tegra_car 59>;
 707                 reset-names = "usb";
 708                 nvidia,phy = <&phy3>;
 709                 status = "disabled";
 710         };
 711
 712         phy3: usb-phy@c5008000 {
 713                 compatible = "nvidia,tegra20-usb-phy";
 714                 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
 715                 phy_type = "utmi";
 716                 clocks = <&tegra_car TEGRA20_CLK_USB3>,
 717                          <&tegra_car TEGRA20_CLK_PLL_U>,
 718                          <&tegra_car TEGRA20_CLK_CLK_M>,
 719                          <&tegra_car TEGRA20_CLK_USBD>;
 720                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 721                 resets = <&tegra_car 59>, <&tegra_car 22>;
 722                 reset-names = "usb", "utmi-pads";
 723                 nvidia,hssync-start-delay = <9>;
 724                 nvidia,idle-wait-delay = <17>;
 725                 nvidia,elastic-limit = <16>;
 726                 nvidia,term-range-adj = <6>;
 727                 nvidia,xcvr-setup = <9>;
 728                 nvidia,xcvr-lsfslew = <2>;
 729                 nvidia,xcvr-lsrslew = <2>;
 730                 status = "disabled";
 731         };
 732
 733         sdhci@c8000000 {
 734                 compatible = "nvidia,tegra20-sdhci";
 735                 reg = <0xc8000000 0x200>;
 736                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 737                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 738                 resets = <&tegra_car 14>;
 739                 reset-names = "sdhci";
 740                 status = "disabled";
 741         };
 742
 743         sdhci@c8000200 {
 744                 compatible = "nvidia,tegra20-sdhci";
 745                 reg = <0xc8000200 0x200>;
 746                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 747                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 748                 resets = <&tegra_car 9>;
 749                 reset-names = "sdhci";
 750                 status = "disabled";
 751         };
 752
 753         sdhci@c8000400 {
 754                 compatible = "nvidia,tegra20-sdhci";
 755                 reg = <0xc8000400 0x200>;
 756                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 757                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 758                 resets = <&tegra_car 69>;
 759                 reset-names = "sdhci";
 760                 status = "disabled";
 761         };
 762
 763         sdhci@c8000600 {
 764                 compatible = "nvidia,tegra20-sdhci";
 765                 reg = <0xc8000600 0x200>;
 766                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 767                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
 768                 resets = <&tegra_car 15>;
 769                 reset-names = "sdhci";
 770                 status = "disabled";
 771         };
 772
 773         cpus {
 774                 #address-cells = <1>;
 775                 #size-cells = <0>;
 776
 777                 cpu@0 {
 778                         device_type = "cpu";
 779                         compatible = "arm,cortex-a9";
 780                         reg = <0>;
 781                 };
 782
 783                 cpu@1 {
 784                         device_type = "cpu";
 785                         compatible = "arm,cortex-a9";
 786                         reg = <1>;
 787                 };
 788         };
 789
 790         pmu {
 791                 compatible = "arm,cortex-a9-pmu";
 792                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 793                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 794         };
 795 };