arch/arm/boot/dts/tegra20.dtsi

   1 #include <dt-bindings/clock/tegra20-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra20";
  10         interrupt-parent = <&intc>;
  11
  12         aliases {
  13                 serial0 = &uarta;
  14                 serial1 = &uartb;
  15                 serial2 = &uartc;
  16                 serial3 = &uartd;
  17                 serial4 = &uarte;
  18         };
  19
  20         host1x@50000000 {
  21                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  22                 reg = <0x50000000 0x00024000>;
  23                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  24                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  25                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  26                 resets = <&tegra_car 28>;
  27                 reset-names = "host1x";
  28
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31
  32                 ranges = <0x54000000 0x54000000 0x04000000>;
  33
  34                 mpe@54040000 {
  35                         compatible = "nvidia,tegra20-mpe";
  36                         reg = <0x54040000 0x00040000>;
  37                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  38                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
  39                         resets = <&tegra_car 60>;
  40                         reset-names = "mpe";
  41                 };
  42
  43                 vi@54080000 {
  44                         compatible = "nvidia,tegra20-vi";
  45                         reg = <0x54080000 0x00040000>;
  46                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  47                         clocks = <&tegra_car TEGRA20_CLK_VI>;
  48                         resets = <&tegra_car 20>;
  49                         reset-names = "vi";
  50                 };
  51
  52                 epp@540c0000 {
  53                         compatible = "nvidia,tegra20-epp";
  54                         reg = <0x540c0000 0x00040000>;
  55                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  56                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  57                         resets = <&tegra_car 19>;
  58                         reset-names = "epp";
  59                 };
  60
  61                 isp@54100000 {
  62                         compatible = "nvidia,tegra20-isp";
  63                         reg = <0x54100000 0x00040000>;
  64                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  65                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
  66                         resets = <&tegra_car 23>;
  67                         reset-names = "isp";
  68                 };
  69
  70                 gr2d@54140000 {
  71                         compatible = "nvidia,tegra20-gr2d";
  72                         reg = <0x54140000 0x00040000>;
  73                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  74                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
  75                         resets = <&tegra_car 21>;
  76                         reset-names = "2d";
  77                 };
  78
  79                 gr3d@54140000 {
  80                         compatible = "nvidia,tegra20-gr3d";
  81                         reg = <0x54140000 0x00040000>;
  82                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
  83                         resets = <&tegra_car 24>;
  84                         reset-names = "3d";
  85                 };
  86
  87                 dc@54200000 {
  88                         compatible = "nvidia,tegra20-dc";
  89                         reg = <0x54200000 0x00040000>;
  90                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  91                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
  92                                  <&tegra_car TEGRA20_CLK_PLL_P>;
  93                         clock-names = "dc", "parent";
  94                         resets = <&tegra_car 27>;
  95                         reset-names = "dc";
  96
  97                         nvidia,head = <0>;
  98
  99                         rgb {
 100                                 status = "disabled";
 101                         };
 102                 };
 103
 104                 dc@54240000 {
 105                         compatible = "nvidia,tegra20-dc";
 106                         reg = <0x54240000 0x00040000>;
 107                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 108                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 109                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 110                         clock-names = "dc", "parent";
 111                         resets = <&tegra_car 26>;
 112                         reset-names = "dc";
 113
 114                         nvidia,head = <1>;
 115
 116                         rgb {
 117                                 status = "disabled";
 118                         };
 119                 };
 120
 121                 hdmi@54280000 {
 122                         compatible = "nvidia,tegra20-hdmi";
 123                         reg = <0x54280000 0x00040000>;
 124                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 125                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 126                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 127                         clock-names = "hdmi", "parent";
 128                         resets = <&tegra_car 51>;
 129                         reset-names = "hdmi";
 130                         status = "disabled";
 131                 };
 132
 133                 tvo@542c0000 {
 134                         compatible = "nvidia,tegra20-tvo";
 135                         reg = <0x542c0000 0x00040000>;
 136                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 137                         clocks = <&tegra_car TEGRA20_CLK_TVO>;
 138                         status = "disabled";
 139                 };
 140
 141                 dsi@542c0000 {
 142                         compatible = "nvidia,tegra20-dsi";
 143                         reg = <0x542c0000 0x00040000>;
 144                         clocks = <&tegra_car TEGRA20_CLK_DSI>;
 145                         resets = <&tegra_car 48>;
 146                         reset-names = "dsi";
 147                         status = "disabled";
 148                 };
 149         };
 150
 151         timer@50004600 {
 152                 compatible = "arm,cortex-a9-twd-timer";
 153                 reg = <0x50040600 0x20>;
 154                 interrupts = <GIC_PPI 13
 155                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 156                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
 157         };
 158
 159         intc: interrupt-controller@50041000 {
 160                 compatible = "arm,cortex-a9-gic";
 161                 reg = <0x50041000 0x1000
 162                        0x50040100 0x0100>;
 163                 interrupt-controller;
 164                 #interrupt-cells = <3>;
 165         };
 166
 167         cache-controller@50043000 {
 168                 compatible = "arm,pl310-cache";
 169                 reg = <0x50043000 0x1000>;
 170                 arm,data-latency = <5 5 2>;
 171                 arm,tag-latency = <4 4 2>;
 172                 cache-unified;
 173                 cache-level = <2>;
 174         };
 175
 176         timer@60005000 {
 177                 compatible = "nvidia,tegra20-timer";
 178                 reg = <0x60005000 0x60>;
 179                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 181                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 183                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 184         };
 185
 186         tegra_car: clock@60006000 {
 187                 compatible = "nvidia,tegra20-car";
 188                 reg = <0x60006000 0x1000>;
 189                 #clock-cells = <1>;
 190                 #reset-cells = <1>;
 191         };
 192
 193         apbdma: dma@6000a000 {
 194                 compatible = "nvidia,tegra20-apbdma";
 195                 reg = <0x6000a000 0x1200>;
 196                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 202                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 203                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 204                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 213                 resets = <&tegra_car 34>;
 214                 reset-names = "dma";
 215                 #dma-cells = <1>;
 216         };
 217
 218         ahb@6000c004 {
 219                 compatible = "nvidia,tegra20-ahb";
 220                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 221         };
 222
 223         gpio: gpio@6000d000 {
 224                 compatible = "nvidia,tegra20-gpio";
 225                 reg = <0x6000d000 0x1000>;
 226                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 228                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 229                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 230                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 231                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 232                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 233                 #gpio-cells = <2>;
 234                 gpio-controller;
 235                 #interrupt-cells = <2>;
 236                 interrupt-controller;
 237         };
 238
 239         pinmux: pinmux@70000014 {
 240                 compatible = "nvidia,tegra20-pinmux";
 241                 reg = <0x70000014 0x10   /* Tri-state registers */
 242                        0x70000080 0x20   /* Mux registers */
 243                        0x700000a0 0x14   /* Pull-up/down registers */
 244                        0x70000868 0xa8>; /* Pad control registers */
 245         };
 246
 247         das@70000c00 {
 248                 compatible = "nvidia,tegra20-das";
 249                 reg = <0x70000c00 0x80>;
 250         };
 251
 252         tegra_ac97: ac97@70002000 {
 253                 compatible = "nvidia,tegra20-ac97";
 254                 reg = <0x70002000 0x200>;
 255                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 256                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
 257                 resets = <&tegra_car 3>;
 258                 reset-names = "ac97";
 259                 dmas = <&apbdma 12>, <&apbdma 12>;
 260                 dma-names = "rx", "tx";
 261                 status = "disabled";
 262         };
 263
 264         tegra_i2s1: i2s@70002800 {
 265                 compatible = "nvidia,tegra20-i2s";
 266                 reg = <0x70002800 0x200>;
 267                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 268                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 269                 resets = <&tegra_car 11>;
 270                 reset-names = "i2s";
 271                 dmas = <&apbdma 2>, <&apbdma 2>;
 272                 dma-names = "rx", "tx";
 273                 status = "disabled";
 274         };
 275
 276         tegra_i2s2: i2s@70002a00 {
 277                 compatible = "nvidia,tegra20-i2s";
 278                 reg = <0x70002a00 0x200>;
 279                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 281                 resets = <&tegra_car 18>;
 282                 reset-names = "i2s";
 283                 dmas = <&apbdma 1>, <&apbdma 1>;
 284                 dma-names = "rx", "tx";
 285                 status = "disabled";
 286         };
 287
 288         /*
 289          * There are two serial driver i.e. 8250 based simple serial
 290          * driver and APB DMA based serial driver for higher baudrate
 291          * and performace. To enable the 8250 based driver, the compatible
 292          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 293          * driver, the comptible is "nvidia,tegra20-hsuart".
 294          */
 295         uarta: serial@70006000 {
 296                 compatible = "nvidia,tegra20-uart";
 297                 reg = <0x70006000 0x40>;
 298                 reg-shift = <2>;
 299                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 300                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 301                 resets = <&tegra_car 6>;
 302                 reset-names = "serial";
 303                 dmas = <&apbdma 8>, <&apbdma 8>;
 304                 dma-names = "rx", "tx";
 305                 status = "disabled";
 306         };
 307
 308         uartb: serial@70006040 {
 309                 compatible = "nvidia,tegra20-uart";
 310                 reg = <0x70006040 0x40>;
 311                 reg-shift = <2>;
 312                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 314                 resets = <&tegra_car 7>;
 315                 reset-names = "serial";
 316                 dmas = <&apbdma 9>, <&apbdma 9>;
 317                 dma-names = "rx", "tx";
 318                 status = "disabled";
 319         };
 320
 321         uartc: serial@70006200 {
 322                 compatible = "nvidia,tegra20-uart";
 323                 reg = <0x70006200 0x100>;
 324                 reg-shift = <2>;
 325                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 326                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 327                 resets = <&tegra_car 55>;
 328                 reset-names = "serial";
 329                 dmas = <&apbdma 10>, <&apbdma 10>;
 330                 dma-names = "rx", "tx";
 331                 status = "disabled";
 332         };
 333
 334         uartd: serial@70006300 {
 335                 compatible = "nvidia,tegra20-uart";
 336                 reg = <0x70006300 0x100>;
 337                 reg-shift = <2>;
 338                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 339                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 340                 resets = <&tegra_car 65>;
 341                 reset-names = "serial";
 342                 dmas = <&apbdma 19>, <&apbdma 19>;
 343                 dma-names = "rx", "tx";
 344                 status = "disabled";
 345         };
 346
 347         uarte: serial@70006400 {
 348                 compatible = "nvidia,tegra20-uart";
 349                 reg = <0x70006400 0x100>;
 350                 reg-shift = <2>;
 351                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 352                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 353                 resets = <&tegra_car 66>;
 354                 reset-names = "serial";
 355                 dmas = <&apbdma 20>, <&apbdma 20>;
 356                 dma-names = "rx", "tx";
 357                 status = "disabled";
 358         };
 359
 360         pwm: pwm@7000a000 {
 361                 compatible = "nvidia,tegra20-pwm";
 362                 reg = <0x7000a000 0x100>;
 363                 #pwm-cells = <2>;
 364                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
 365                 resets = <&tegra_car 17>;
 366                 reset-names = "pwm";
 367                 status = "disabled";
 368         };
 369
 370         rtc@7000e000 {
 371                 compatible = "nvidia,tegra20-rtc";
 372                 reg = <0x7000e000 0x100>;
 373                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&tegra_car TEGRA20_CLK_RTC>;
 375         };
 376
 377         i2c@7000c000 {
 378                 compatible = "nvidia,tegra20-i2c";
 379                 reg = <0x7000c000 0x100>;
 380                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 384                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 385                 clock-names = "div-clk", "fast-clk";
 386                 resets = <&tegra_car 12>;
 387                 reset-names = "i2c";
 388                 dmas = <&apbdma 21>, <&apbdma 21>;
 389                 dma-names = "rx", "tx";
 390                 status = "disabled";
 391         };
 392
 393         spi@7000c380 {
 394                 compatible = "nvidia,tegra20-sflash";
 395                 reg = <0x7000c380 0x80>;
 396                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
 400                 resets = <&tegra_car 43>;
 401                 reset-names = "spi";
 402                 dmas = <&apbdma 11>, <&apbdma 11>;
 403                 dma-names = "rx", "tx";
 404                 status = "disabled";
 405         };
 406
 407         i2c@7000c400 {
 408                 compatible = "nvidia,tegra20-i2c";
 409                 reg = <0x7000c400 0x100>;
 410                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 414                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 415                 clock-names = "div-clk", "fast-clk";
 416                 resets = <&tegra_car 54>;
 417                 reset-names = "i2c";
 418                 dmas = <&apbdma 22>, <&apbdma 22>;
 419                 dma-names = "rx", "tx";
 420                 status = "disabled";
 421         };
 422
 423         i2c@7000c500 {
 424                 compatible = "nvidia,tegra20-i2c";
 425                 reg = <0x7000c500 0x100>;
 426                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 430                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 431                 clock-names = "div-clk", "fast-clk";
 432                 resets = <&tegra_car 67>;
 433                 reset-names = "i2c";
 434                 dmas = <&apbdma 23>, <&apbdma 23>;
 435                 dma-names = "rx", "tx";
 436                 status = "disabled";
 437         };
 438
 439         i2c@7000d000 {
 440                 compatible = "nvidia,tegra20-i2c-dvc";
 441                 reg = <0x7000d000 0x200>;
 442                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
 446                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 447                 clock-names = "div-clk", "fast-clk";
 448                 resets = <&tegra_car 47>;
 449                 reset-names = "i2c";
 450                 dmas = <&apbdma 24>, <&apbdma 24>;
 451                 dma-names = "rx", "tx";
 452                 status = "disabled";
 453         };
 454
 455         spi@7000d400 {
 456                 compatible = "nvidia,tegra20-slink";
 457                 reg = <0x7000d400 0x200>;
 458                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 462                 resets = <&tegra_car 41>;
 463                 reset-names = "spi";
 464                 dmas = <&apbdma 15>, <&apbdma 15>;
 465                 dma-names = "rx", "tx";
 466                 status = "disabled";
 467         };
 468
 469         spi@7000d600 {
 470                 compatible = "nvidia,tegra20-slink";
 471                 reg = <0x7000d600 0x200>;
 472                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 476                 resets = <&tegra_car 44>;
 477                 reset-names = "spi";
 478                 dmas = <&apbdma 16>, <&apbdma 16>;
 479                 dma-names = "rx", "tx";
 480                 status = "disabled";
 481         };
 482
 483         spi@7000d800 {
 484                 compatible = "nvidia,tegra20-slink";
 485                 reg = <0x7000d800 0x200>;
 486                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 487                 #address-cells = <1>;
 488                 #size-cells = <0>;
 489                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 490                 resets = <&tegra_car 46>;
 491                 reset-names = "spi";
 492                 dmas = <&apbdma 17>, <&apbdma 17>;
 493                 dma-names = "rx", "tx";
 494                 status = "disabled";
 495         };
 496
 497         spi@7000da00 {
 498                 compatible = "nvidia,tegra20-slink";
 499                 reg = <0x7000da00 0x200>;
 500                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 504                 resets = <&tegra_car 68>;
 505                 reset-names = "spi";
 506                 dmas = <&apbdma 18>, <&apbdma 18>;
 507                 dma-names = "rx", "tx";
 508                 status = "disabled";
 509         };
 510
 511         kbc@7000e200 {
 512                 compatible = "nvidia,tegra20-kbc";
 513                 reg = <0x7000e200 0x100>;
 514                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 515                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
 516                 resets = <&tegra_car 36>;
 517                 reset-names = "kbc";
 518                 status = "disabled";
 519         };
 520
 521         pmc@7000e400 {
 522                 compatible = "nvidia,tegra20-pmc";
 523                 reg = <0x7000e400 0x400>;
 524                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 525                 clock-names = "pclk", "clk32k_in";
 526         };
 527
 528         memory-controller@7000f000 {
 529                 compatible = "nvidia,tegra20-mc";
 530                 reg = <0x7000f000 0x024
 531                        0x7000f03c 0x3c4>;
 532                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 533         };
 534
 535         iommu@7000f024 {
 536                 compatible = "nvidia,tegra20-gart";
 537                 reg = <0x7000f024 0x00000018    /* controller registers */
 538                        0x58000000 0x02000000>;  /* GART aperture */
 539         };
 540
 541         memory-controller@7000f400 {
 542                 compatible = "nvidia,tegra20-emc";
 543                 reg = <0x7000f400 0x200>;
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546         };
 547
 548         pcie-controller@80003000 {
 549                 compatible = "nvidia,tegra20-pcie";
 550                 device_type = "pci";
 551                 reg = <0x80003000 0x00000800   /* PADS registers */
 552                        0x80003800 0x00000200   /* AFI registers */
 553                        0x90000000 0x10000000>; /* configuration space */
 554                 reg-names = "pads", "afi", "cs";
 555                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
 556                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 557                 interrupt-names = "intr", "msi";
 558
 559                 #interrupt-cells = <1>;
 560                 interrupt-map-mask = <0 0 0 0>;
 561                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 562
 563                 bus-range = <0x00 0xff>;
 564                 #address-cells = <3>;
 565                 #size-cells = <2>;
 566
 567                 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
 568                           0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
 569                           0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
 570                           0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
 571                           0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
 572
 573                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
 574                          <&tegra_car TEGRA20_CLK_AFI>,
 575                          <&tegra_car TEGRA20_CLK_PLL_E>;
 576                 clock-names = "pex", "afi", "pll_e";
 577                 resets = <&tegra_car 70>,
 578                          <&tegra_car 72>,
 579                          <&tegra_car 74>;
 580                 reset-names = "pex", "afi", "pcie_x";
 581                 status = "disabled";
 582
 583                 pci@1,0 {
 584                         device_type = "pci";
 585                         assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
 586                         reg = <0x000800 0 0 0 0>;
 587                         status = "disabled";
 588
 589                         #address-cells = <3>;
 590                         #size-cells = <2>;
 591                         ranges;
 592
 593                         nvidia,num-lanes = <2>;
 594                 };
 595
 596                 pci@2,0 {
 597                         device_type = "pci";
 598                         assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
 599                         reg = <0x001000 0 0 0 0>;
 600                         status = "disabled";
 601
 602                         #address-cells = <3>;
 603                         #size-cells = <2>;
 604                         ranges;
 605
 606                         nvidia,num-lanes = <2>;
 607                 };
 608         };
 609
 610         usb@c5000000 {
 611                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 612                 reg = <0xc5000000 0x4000>;
 613                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 614                 phy_type = "utmi";
 615                 nvidia,has-legacy-mode;
 616                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
 617                 resets = <&tegra_car 22>;
 618                 reset-names = "usb";
 619                 nvidia,needs-double-reset;
 620                 nvidia,phy = <&phy1>;
 621                 status = "disabled";
 622         };
 623
 624         phy1: usb-phy@c5000000 {
 625                 compatible = "nvidia,tegra20-usb-phy";
 626                 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
 627                 phy_type = "utmi";
 628                 clocks = <&tegra_car TEGRA20_CLK_USBD>,
 629                          <&tegra_car TEGRA20_CLK_PLL_U>,
 630                          <&tegra_car TEGRA20_CLK_CLK_M>,
 631                          <&tegra_car TEGRA20_CLK_USBD>;
 632                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 633                 nvidia,has-legacy-mode;
 634                 nvidia,hssync-start-delay = <9>;
 635                 nvidia,idle-wait-delay = <17>;
 636                 nvidia,elastic-limit = <16>;
 637                 nvidia,term-range-adj = <6>;
 638                 nvidia,xcvr-setup = <9>;
 639                 nvidia,xcvr-lsfslew = <1>;
 640                 nvidia,xcvr-lsrslew = <1>;
 641                 status = "disabled";
 642         };
 643
 644         usb@c5004000 {
 645                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 646                 reg = <0xc5004000 0x4000>;
 647                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 648                 phy_type = "ulpi";
 649                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
 650                 resets = <&tegra_car 58>;
 651                 reset-names = "usb";
 652                 nvidia,phy = <&phy2>;
 653                 status = "disabled";
 654         };
 655
 656         phy2: usb-phy@c5004000 {
 657                 compatible = "nvidia,tegra20-usb-phy";
 658                 reg = <0xc5004000 0x4000>;
 659                 phy_type = "ulpi";
 660                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
 661                          <&tegra_car TEGRA20_CLK_PLL_U>,
 662                          <&tegra_car TEGRA20_CLK_CDEV2>;
 663                 clock-names = "reg", "pll_u", "ulpi-link";
 664                 status = "disabled";
 665         };
 666
 667         usb@c5008000 {
 668                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 669                 reg = <0xc5008000 0x4000>;
 670                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 671                 phy_type = "utmi";
 672                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
 673                 resets = <&tegra_car 59>;
 674                 reset-names = "usb";
 675                 nvidia,phy = <&phy3>;
 676                 status = "disabled";
 677         };
 678
 679         phy3: usb-phy@c5008000 {
 680                 compatible = "nvidia,tegra20-usb-phy";
 681                 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
 682                 phy_type = "utmi";
 683                 clocks = <&tegra_car TEGRA20_CLK_USB3>,
 684                          <&tegra_car TEGRA20_CLK_PLL_U>,
 685                          <&tegra_car TEGRA20_CLK_CLK_M>,
 686                          <&tegra_car TEGRA20_CLK_USBD>;
 687                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 688                 nvidia,hssync-start-delay = <9>;
 689                 nvidia,idle-wait-delay = <17>;
 690                 nvidia,elastic-limit = <16>;
 691                 nvidia,term-range-adj = <6>;
 692                 nvidia,xcvr-setup = <9>;
 693                 nvidia,xcvr-lsfslew = <2>;
 694                 nvidia,xcvr-lsrslew = <2>;
 695                 status = "disabled";
 696         };
 697
 698         sdhci@c8000000 {
 699                 compatible = "nvidia,tegra20-sdhci";
 700                 reg = <0xc8000000 0x200>;
 701                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 702                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 703                 resets = <&tegra_car 14>;
 704                 reset-names = "sdhci";
 705                 status = "disabled";
 706         };
 707
 708         sdhci@c8000200 {
 709                 compatible = "nvidia,tegra20-sdhci";
 710                 reg = <0xc8000200 0x200>;
 711                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 712                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 713                 resets = <&tegra_car 9>;
 714                 reset-names = "sdhci";
 715                 status = "disabled";
 716         };
 717
 718         sdhci@c8000400 {
 719                 compatible = "nvidia,tegra20-sdhci";
 720                 reg = <0xc8000400 0x200>;
 721                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 722                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 723                 resets = <&tegra_car 69>;
 724                 reset-names = "sdhci";
 725                 status = "disabled";
 726         };
 727
 728         sdhci@c8000600 {
 729                 compatible = "nvidia,tegra20-sdhci";
 730                 reg = <0xc8000600 0x200>;
 731                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 732                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
 733                 resets = <&tegra_car 15>;
 734                 reset-names = "sdhci";
 735                 status = "disabled";
 736         };
 737
 738         cpus {
 739                 #address-cells = <1>;
 740                 #size-cells = <0>;
 741
 742                 cpu@0 {
 743                         device_type = "cpu";
 744                         compatible = "arm,cortex-a9";
 745                         reg = <0>;
 746                 };
 747
 748                 cpu@1 {
 749                         device_type = "cpu";
 750                         compatible = "arm,cortex-a9";
 751                         reg = <1>;
 752                 };
 753         };
 754
 755         pmu {
 756                 compatible = "arm,cortex-a9-pmu";
 757                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 758                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 759         };
 760 };