arch/arm/boot/dts/tegra20.dtsi

   1 #include <dt-bindings/gpio/tegra-gpio.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3
   4 #include "skeleton.dtsi"
   5
   6 / {
   7         compatible = "nvidia,tegra20";
   8         interrupt-parent = <&intc>;
   9
  10         aliases {
  11                 serial0 = &uarta;
  12                 serial1 = &uartb;
  13                 serial2 = &uartc;
  14                 serial3 = &uartd;
  15                 serial4 = &uarte;
  16         };
  17
  18         host1x {
  19                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  20                 reg = <0x50000000 0x00024000>;
  21                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  22                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  23                 clocks = <&tegra_car 28>;
  24
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27
  28                 ranges = <0x54000000 0x54000000 0x04000000>;
  29
  30                 mpe {
  31                         compatible = "nvidia,tegra20-mpe";
  32                         reg = <0x54040000 0x00040000>;
  33                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  34                         clocks = <&tegra_car 60>;
  35                 };
  36
  37                 vi {
  38                         compatible = "nvidia,tegra20-vi";
  39                         reg = <0x54080000 0x00040000>;
  40                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  41                         clocks = <&tegra_car 100>;
  42                 };
  43
  44                 epp {
  45                         compatible = "nvidia,tegra20-epp";
  46                         reg = <0x540c0000 0x00040000>;
  47                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  48                         clocks = <&tegra_car 19>;
  49                 };
  50
  51                 isp {
  52                         compatible = "nvidia,tegra20-isp";
  53                         reg = <0x54100000 0x00040000>;
  54                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  55                         clocks = <&tegra_car 23>;
  56                 };
  57
  58                 gr2d {
  59                         compatible = "nvidia,tegra20-gr2d";
  60                         reg = <0x54140000 0x00040000>;
  61                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  62                         clocks = <&tegra_car 21>;
  63                 };
  64
  65                 gr3d {
  66                         compatible = "nvidia,tegra20-gr3d";
  67                         reg = <0x54180000 0x00040000>;
  68                         clocks = <&tegra_car 24>;
  69                 };
  70
  71                 dc@54200000 {
  72                         compatible = "nvidia,tegra20-dc";
  73                         reg = <0x54200000 0x00040000>;
  74                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  75                         clocks = <&tegra_car 27>, <&tegra_car 121>;
  76                         clock-names = "disp1", "parent";
  77
  78                         rgb {
  79                                 status = "disabled";
  80                         };
  81                 };
  82
  83                 dc@54240000 {
  84                         compatible = "nvidia,tegra20-dc";
  85                         reg = <0x54240000 0x00040000>;
  86                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  87                         clocks = <&tegra_car 26>, <&tegra_car 121>;
  88                         clock-names = "disp2", "parent";
  89
  90                         rgb {
  91                                 status = "disabled";
  92                         };
  93                 };
  94
  95                 hdmi {
  96                         compatible = "nvidia,tegra20-hdmi";
  97                         reg = <0x54280000 0x00040000>;
  98                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  99                         clocks = <&tegra_car 51>, <&tegra_car 117>;
 100                         clock-names = "hdmi", "parent";
 101                         status = "disabled";
 102                 };
 103
 104                 tvo {
 105                         compatible = "nvidia,tegra20-tvo";
 106                         reg = <0x542c0000 0x00040000>;
 107                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 108                         clocks = <&tegra_car 102>;
 109                         status = "disabled";
 110                 };
 111
 112                 dsi {
 113                         compatible = "nvidia,tegra20-dsi";
 114                         reg = <0x54300000 0x00040000>;
 115                         clocks = <&tegra_car 48>;
 116                         status = "disabled";
 117                 };
 118         };
 119
 120         timer@50004600 {
 121                 compatible = "arm,cortex-a9-twd-timer";
 122                 reg = <0x50040600 0x20>;
 123                 interrupts = <GIC_PPI 13
 124                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 125                 clocks = <&tegra_car 132>;
 126         };
 127
 128         intc: interrupt-controller {
 129                 compatible = "arm,cortex-a9-gic";
 130                 reg = <0x50041000 0x1000
 131                        0x50040100 0x0100>;
 132                 interrupt-controller;
 133                 #interrupt-cells = <3>;
 134         };
 135
 136         cache-controller {
 137                 compatible = "arm,pl310-cache";
 138                 reg = <0x50043000 0x1000>;
 139                 arm,data-latency = <5 5 2>;
 140                 arm,tag-latency = <4 4 2>;
 141                 cache-unified;
 142                 cache-level = <2>;
 143         };
 144
 145         timer@60005000 {
 146                 compatible = "nvidia,tegra20-timer";
 147                 reg = <0x60005000 0x60>;
 148                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 151                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 152                 clocks = <&tegra_car 5>;
 153         };
 154
 155         tegra_car: clock {
 156                 compatible = "nvidia,tegra20-car";
 157                 reg = <0x60006000 0x1000>;
 158                 #clock-cells = <1>;
 159         };
 160
 161         apbdma: dma {
 162                 compatible = "nvidia,tegra20-apbdma";
 163                 reg = <0x6000a000 0x1200>;
 164                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 180                 clocks = <&tegra_car 34>;
 181         };
 182
 183         ahb {
 184                 compatible = "nvidia,tegra20-ahb";
 185                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 186         };
 187
 188         gpio: gpio {
 189                 compatible = "nvidia,tegra20-gpio";
 190                 reg = <0x6000d000 0x1000>;
 191                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 198                 #gpio-cells = <2>;
 199                 gpio-controller;
 200                 #interrupt-cells = <2>;
 201                 interrupt-controller;
 202         };
 203
 204         pinmux: pinmux {
 205                 compatible = "nvidia,tegra20-pinmux";
 206                 reg = <0x70000014 0x10   /* Tri-state registers */
 207                        0x70000080 0x20   /* Mux registers */
 208                        0x700000a0 0x14   /* Pull-up/down registers */
 209                        0x70000868 0xa8>; /* Pad control registers */
 210         };
 211
 212         das {
 213                 compatible = "nvidia,tegra20-das";
 214                 reg = <0x70000c00 0x80>;
 215         };
 216
 217         tegra_ac97: ac97 {
 218                 compatible = "nvidia,tegra20-ac97";
 219                 reg = <0x70002000 0x200>;
 220                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 221                 nvidia,dma-request-selector = <&apbdma 12>;
 222                 clocks = <&tegra_car 3>;
 223                 status = "disabled";
 224         };
 225
 226         tegra_i2s1: i2s@70002800 {
 227                 compatible = "nvidia,tegra20-i2s";
 228                 reg = <0x70002800 0x200>;
 229                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 230                 nvidia,dma-request-selector = <&apbdma 2>;
 231                 clocks = <&tegra_car 11>;
 232                 status = "disabled";
 233         };
 234
 235         tegra_i2s2: i2s@70002a00 {
 236                 compatible = "nvidia,tegra20-i2s";
 237                 reg = <0x70002a00 0x200>;
 238                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 239                 nvidia,dma-request-selector = <&apbdma 1>;
 240                 clocks = <&tegra_car 18>;
 241                 status = "disabled";
 242         };
 243
 244         /*
 245          * There are two serial driver i.e. 8250 based simple serial
 246          * driver and APB DMA based serial driver for higher baudrate
 247          * and performace. To enable the 8250 based driver, the compatible
 248          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 249          * driver, the comptible is "nvidia,tegra20-hsuart".
 250          */
 251         uarta: serial@70006000 {
 252                 compatible = "nvidia,tegra20-uart";
 253                 reg = <0x70006000 0x40>;
 254                 reg-shift = <2>;
 255                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 256                 nvidia,dma-request-selector = <&apbdma 8>;
 257                 clocks = <&tegra_car 6>;
 258                 status = "disabled";
 259         };
 260
 261         uartb: serial@70006040 {
 262                 compatible = "nvidia,tegra20-uart";
 263                 reg = <0x70006040 0x40>;
 264                 reg-shift = <2>;
 265                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 266                 nvidia,dma-request-selector = <&apbdma 9>;
 267                 clocks = <&tegra_car 96>;
 268                 status = "disabled";
 269         };
 270
 271         uartc: serial@70006200 {
 272                 compatible = "nvidia,tegra20-uart";
 273                 reg = <0x70006200 0x100>;
 274                 reg-shift = <2>;
 275                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 276                 nvidia,dma-request-selector = <&apbdma 10>;
 277                 clocks = <&tegra_car 55>;
 278                 status = "disabled";
 279         };
 280
 281         uartd: serial@70006300 {
 282                 compatible = "nvidia,tegra20-uart";
 283                 reg = <0x70006300 0x100>;
 284                 reg-shift = <2>;
 285                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 286                 nvidia,dma-request-selector = <&apbdma 19>;
 287                 clocks = <&tegra_car 65>;
 288                 status = "disabled";
 289         };
 290
 291         uarte: serial@70006400 {
 292                 compatible = "nvidia,tegra20-uart";
 293                 reg = <0x70006400 0x100>;
 294                 reg-shift = <2>;
 295                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 296                 nvidia,dma-request-selector = <&apbdma 20>;
 297                 clocks = <&tegra_car 66>;
 298                 status = "disabled";
 299         };
 300
 301         pwm: pwm {
 302                 compatible = "nvidia,tegra20-pwm";
 303                 reg = <0x7000a000 0x100>;
 304                 #pwm-cells = <2>;
 305                 clocks = <&tegra_car 17>;
 306                 status = "disabled";
 307         };
 308
 309         rtc {
 310                 compatible = "nvidia,tegra20-rtc";
 311                 reg = <0x7000e000 0x100>;
 312                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&tegra_car 4>;
 314         };
 315
 316         i2c@7000c000 {
 317                 compatible = "nvidia,tegra20-i2c";
 318                 reg = <0x7000c000 0x100>;
 319                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322                 clocks = <&tegra_car 12>, <&tegra_car 124>;
 323                 clock-names = "div-clk", "fast-clk";
 324                 status = "disabled";
 325         };
 326
 327         spi@7000c380 {
 328                 compatible = "nvidia,tegra20-sflash";
 329                 reg = <0x7000c380 0x80>;
 330                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 331                 nvidia,dma-request-selector = <&apbdma 11>;
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334                 clocks = <&tegra_car 43>;
 335                 status = "disabled";
 336         };
 337
 338         i2c@7000c400 {
 339                 compatible = "nvidia,tegra20-i2c";
 340                 reg = <0x7000c400 0x100>;
 341                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 clocks = <&tegra_car 54>, <&tegra_car 124>;
 345                 clock-names = "div-clk", "fast-clk";
 346                 status = "disabled";
 347         };
 348
 349         i2c@7000c500 {
 350                 compatible = "nvidia,tegra20-i2c";
 351                 reg = <0x7000c500 0x100>;
 352                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 clocks = <&tegra_car 67>, <&tegra_car 124>;
 356                 clock-names = "div-clk", "fast-clk";
 357                 status = "disabled";
 358         };
 359
 360         i2c@7000d000 {
 361                 compatible = "nvidia,tegra20-i2c-dvc";
 362                 reg = <0x7000d000 0x200>;
 363                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 clocks = <&tegra_car 47>, <&tegra_car 124>;
 367                 clock-names = "div-clk", "fast-clk";
 368                 status = "disabled";
 369         };
 370
 371         spi@7000d400 {
 372                 compatible = "nvidia,tegra20-slink";
 373                 reg = <0x7000d400 0x200>;
 374                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 375                 nvidia,dma-request-selector = <&apbdma 15>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 clocks = <&tegra_car 41>;
 379                 status = "disabled";
 380         };
 381
 382         spi@7000d600 {
 383                 compatible = "nvidia,tegra20-slink";
 384                 reg = <0x7000d600 0x200>;
 385                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 386                 nvidia,dma-request-selector = <&apbdma 16>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 clocks = <&tegra_car 44>;
 390                 status = "disabled";
 391         };
 392
 393         spi@7000d800 {
 394                 compatible = "nvidia,tegra20-slink";
 395                 reg = <0x7000d800 0x200>;
 396                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 397                 nvidia,dma-request-selector = <&apbdma 17>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 clocks = <&tegra_car 46>;
 401                 status = "disabled";
 402         };
 403
 404         spi@7000da00 {
 405                 compatible = "nvidia,tegra20-slink";
 406                 reg = <0x7000da00 0x200>;
 407                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 408                 nvidia,dma-request-selector = <&apbdma 18>;
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 clocks = <&tegra_car 68>;
 412                 status = "disabled";
 413         };
 414
 415         kbc {
 416                 compatible = "nvidia,tegra20-kbc";
 417                 reg = <0x7000e200 0x100>;
 418                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 419                 clocks = <&tegra_car 36>;
 420                 status = "disabled";
 421         };
 422
 423         pmc {
 424                 compatible = "nvidia,tegra20-pmc";
 425                 reg = <0x7000e400 0x400>;
 426                 clocks = <&tegra_car 110>, <&clk32k_in>;
 427                 clock-names = "pclk", "clk32k_in";
 428         };
 429
 430         memory-controller@7000f000 {
 431                 compatible = "nvidia,tegra20-mc";
 432                 reg = <0x7000f000 0x024
 433                        0x7000f03c 0x3c4>;
 434                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 435         };
 436
 437         iommu {
 438                 compatible = "nvidia,tegra20-gart";
 439                 reg = <0x7000f024 0x00000018    /* controller registers */
 440                        0x58000000 0x02000000>;  /* GART aperture */
 441         };
 442
 443         memory-controller@7000f400 {
 444                 compatible = "nvidia,tegra20-emc";
 445                 reg = <0x7000f400 0x200>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448         };
 449
 450         usb@c5000000 {
 451                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 452                 reg = <0xc5000000 0x4000>;
 453                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 454                 phy_type = "utmi";
 455                 nvidia,has-legacy-mode;
 456                 clocks = <&tegra_car 22>;
 457                 nvidia,needs-double-reset;
 458                 nvidia,phy = <&phy1>;
 459                 status = "disabled";
 460         };
 461
 462         phy1: usb-phy@c5000000 {
 463                 compatible = "nvidia,tegra20-usb-phy";
 464                 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
 465                 phy_type = "utmi";
 466                 clocks = <&tegra_car 22>,
 467                          <&tegra_car 127>,
 468                          <&tegra_car 106>,
 469                          <&tegra_car 22>;
 470                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 471                 nvidia,has-legacy-mode;
 472                 hssync_start_delay = <9>;
 473                 idle_wait_delay = <17>;
 474                 elastic_limit = <16>;
 475                 term_range_adj = <6>;
 476                 xcvr_setup = <9>;
 477                 xcvr_lsfslew = <1>;
 478                 xcvr_lsrslew = <1>;
 479                 status = "disabled";
 480         };
 481
 482         usb@c5004000 {
 483                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 484                 reg = <0xc5004000 0x4000>;
 485                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 486                 phy_type = "ulpi";
 487                 clocks = <&tegra_car 58>;
 488                 nvidia,phy = <&phy2>;
 489                 status = "disabled";
 490         };
 491
 492         phy2: usb-phy@c5004000 {
 493                 compatible = "nvidia,tegra20-usb-phy";
 494                 reg = <0xc5004000 0x4000>;
 495                 phy_type = "ulpi";
 496                 clocks = <&tegra_car 58>,
 497                          <&tegra_car 127>,
 498                          <&tegra_car 93>;
 499                 clock-names = "reg", "pll_u", "ulpi-link";
 500                 status = "disabled";
 501         };
 502
 503         usb@c5008000 {
 504                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 505                 reg = <0xc5008000 0x4000>;
 506                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 507                 phy_type = "utmi";
 508                 clocks = <&tegra_car 59>;
 509                 nvidia,phy = <&phy3>;
 510                 status = "disabled";
 511         };
 512
 513         phy3: usb-phy@c5008000 {
 514                 compatible = "nvidia,tegra20-usb-phy";
 515                 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
 516                 phy_type = "utmi";
 517                 clocks = <&tegra_car 59>,
 518                          <&tegra_car 127>,
 519                          <&tegra_car 106>,
 520                          <&tegra_car 22>;
 521                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 522                 hssync_start_delay = <9>;
 523                 idle_wait_delay = <17>;
 524                 elastic_limit = <16>;
 525                 term_range_adj = <6>;
 526                 xcvr_setup = <9>;
 527                 xcvr_lsfslew = <2>;
 528                 xcvr_lsrslew = <2>;
 529                 status = "disabled";
 530         };
 531
 532         sdhci@c8000000 {
 533                 compatible = "nvidia,tegra20-sdhci";
 534                 reg = <0xc8000000 0x200>;
 535                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 536                 clocks = <&tegra_car 14>;
 537                 status = "disabled";
 538         };
 539
 540         sdhci@c8000200 {
 541                 compatible = "nvidia,tegra20-sdhci";
 542                 reg = <0xc8000200 0x200>;
 543                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 544                 clocks = <&tegra_car 9>;
 545                 status = "disabled";
 546         };
 547
 548         sdhci@c8000400 {
 549                 compatible = "nvidia,tegra20-sdhci";
 550                 reg = <0xc8000400 0x200>;
 551                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 552                 clocks = <&tegra_car 69>;
 553                 status = "disabled";
 554         };
 555
 556         sdhci@c8000600 {
 557                 compatible = "nvidia,tegra20-sdhci";
 558                 reg = <0xc8000600 0x200>;
 559                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 560                 clocks = <&tegra_car 15>;
 561                 status = "disabled";
 562         };
 563
 564         cpus {
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567
 568                 cpu@0 {
 569                         device_type = "cpu";
 570                         compatible = "arm,cortex-a9";
 571                         reg = <0>;
 572                 };
 573
 574                 cpu@1 {
 575                         device_type = "cpu";
 576                         compatible = "arm,cortex-a9";
 577                         reg = <1>;
 578                 };
 579         };
 580
 581         pmu {
 582                 compatible = "arm,cortex-a9-pmu";
 583                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 584                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 585         };
 586 };