1 /include/ "skeleton.dtsi"
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
8 compatible = "nvidia,tegra30-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
16 ranges = <0x54000000 0x54000000 0x04000000>;
19 compatible = "nvidia,tegra30-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
25 compatible = "nvidia,tegra30-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
31 compatible = "nvidia,tegra30-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
37 compatible = "nvidia,tegra30-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
43 compatible = "nvidia,tegra30-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
49 compatible = "nvidia,tegra30-gr3d";
50 reg = <0x54180000 0x00040000>;
54 compatible = "nvidia,tegra30-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
64 compatible = "nvidia,tegra30-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
74 compatible = "nvidia,tegra30-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
81 compatible = "nvidia,tegra30-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
88 compatible = "nvidia,tegra30-dsi";
89 reg = <0x54300000 0x00040000>;
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0xf04>;
100 cache-controller@50043000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x50043000 0x1000>;
103 arm,data-latency = <6 6 2>;
104 arm,tag-latency = <5 5 2>;
109 intc: interrupt-controller {
110 compatible = "arm,cortex-a9-gic";
111 reg = <0x50041000 0x1000
113 interrupt-controller;
114 #interrupt-cells = <3>;
118 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
119 reg = <0x60005000 0x400>;
120 interrupts = <0 0 0x04
129 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
130 reg = <0x6000a000 0x1400>;
131 interrupts = <0 104 0x04
166 compatible = "nvidia,tegra30-ahb";
167 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
171 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
172 reg = <0x6000d000 0x1000>;
173 interrupts = <0 32 0x04
183 #interrupt-cells = <2>;
184 interrupt-controller;
188 compatible = "nvidia,tegra30-pinmux";
189 reg = <0x70000868 0xd4 /* Pad control registers */
190 0x70003000 0x3e4>; /* Mux registers */
194 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
195 reg = <0x70006000 0x40>;
197 interrupts = <0 36 0x04>;
202 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
203 reg = <0x70006040 0x40>;
205 interrupts = <0 37 0x04>;
210 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
211 reg = <0x70006200 0x100>;
213 interrupts = <0 46 0x04>;
218 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
219 reg = <0x70006300 0x100>;
221 interrupts = <0 90 0x04>;
226 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
227 reg = <0x70006400 0x100>;
229 interrupts = <0 91 0x04>;
234 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
235 reg = <0x7000a000 0x100>;
240 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
241 reg = <0x7000e000 0x100>;
242 interrupts = <0 2 0x04>;
246 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
247 reg = <0x7000c000 0x100>;
248 interrupts = <0 38 0x04>;
249 #address-cells = <1>;
255 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
256 reg = <0x7000c400 0x100>;
257 interrupts = <0 84 0x04>;
258 #address-cells = <1>;
264 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
265 reg = <0x7000c500 0x100>;
266 interrupts = <0 92 0x04>;
267 #address-cells = <1>;
273 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
274 reg = <0x7000c700 0x100>;
275 interrupts = <0 120 0x04>;
276 #address-cells = <1>;
282 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
283 reg = <0x7000d000 0x100>;
284 interrupts = <0 53 0x04>;
285 #address-cells = <1>;
291 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
292 reg = <0x7000d400 0x200>;
293 interrupts = <0 59 0x04>;
294 nvidia,dma-request-selector = <&apbdma 15>;
295 #address-cells = <1>;
301 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
302 reg = <0x7000d600 0x200>;
303 interrupts = <0 82 0x04>;
304 nvidia,dma-request-selector = <&apbdma 16>;
305 #address-cells = <1>;
311 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
312 reg = <0x7000d480 0x200>;
313 interrupts = <0 83 0x04>;
314 nvidia,dma-request-selector = <&apbdma 17>;
315 #address-cells = <1>;
321 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
322 reg = <0x7000da00 0x200>;
323 interrupts = <0 93 0x04>;
324 nvidia,dma-request-selector = <&apbdma 18>;
325 #address-cells = <1>;
331 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
332 reg = <0x7000dc00 0x200>;
333 interrupts = <0 94 0x04>;
334 nvidia,dma-request-selector = <&apbdma 27>;
335 #address-cells = <1>;
341 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
342 reg = <0x7000de00 0x200>;
343 interrupts = <0 79 0x04>;
344 nvidia,dma-request-selector = <&apbdma 28>;
345 #address-cells = <1>;
351 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
352 reg = <0x7000e400 0x400>;
356 compatible = "nvidia,tegra30-mc";
357 reg = <0x7000f000 0x010
361 interrupts = <0 77 0x04>;
365 compatible = "nvidia,tegra30-smmu";
366 reg = <0x7000f010 0x02c
369 nvidia,#asids = <4>; /* # of ASIDs */
370 dma-window = <0 0x40000000>; /* IOVA start & length */
375 compatible = "nvidia,tegra30-ahub";
376 reg = <0x70080000 0x200
378 interrupts = <0 103 0x04>;
379 nvidia,dma-request-selector = <&apbdma 1>;
382 #address-cells = <1>;
385 tegra_i2s0: i2s@70080300 {
386 compatible = "nvidia,tegra30-i2s";
387 reg = <0x70080300 0x100>;
388 nvidia,ahub-cif-ids = <4 4>;
392 tegra_i2s1: i2s@70080400 {
393 compatible = "nvidia,tegra30-i2s";
394 reg = <0x70080400 0x100>;
395 nvidia,ahub-cif-ids = <5 5>;
399 tegra_i2s2: i2s@70080500 {
400 compatible = "nvidia,tegra30-i2s";
401 reg = <0x70080500 0x100>;
402 nvidia,ahub-cif-ids = <6 6>;
406 tegra_i2s3: i2s@70080600 {
407 compatible = "nvidia,tegra30-i2s";
408 reg = <0x70080600 0x100>;
409 nvidia,ahub-cif-ids = <7 7>;
413 tegra_i2s4: i2s@70080700 {
414 compatible = "nvidia,tegra30-i2s";
415 reg = <0x70080700 0x100>;
416 nvidia,ahub-cif-ids = <8 8>;
422 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
423 reg = <0x78000000 0x200>;
424 interrupts = <0 14 0x04>;
429 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
430 reg = <0x78000200 0x200>;
431 interrupts = <0 15 0x04>;
436 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
437 reg = <0x78000400 0x200>;
438 interrupts = <0 19 0x04>;
443 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
444 reg = <0x78000600 0x200>;
445 interrupts = <0 31 0x04>;
450 compatible = "arm,cortex-a9-pmu";
451 interrupts = <0 144 0x04