arch/arm/boot/dts/tegra30.dtsi

   1 #include <dt-bindings/clock/tegra30-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra30";
  10         interrupt-parent = <&intc>;
  11
  12         aliases {
  13                 serial0 = &uarta;
  14                 serial1 = &uartb;
  15                 serial2 = &uartc;
  16                 serial3 = &uartd;
  17                 serial4 = &uarte;
  18         };
  19
  20         pcie-controller@00003000 {
  21                 compatible = "nvidia,tegra30-pcie";
  22                 device_type = "pci";
  23                 reg = <0x00003000 0x00000800   /* PADS registers */
  24                        0x00003800 0x00000200   /* AFI registers */
  25                        0x10000000 0x10000000>; /* configuration space */
  26                 reg-names = "pads", "afi", "cs";
  27                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
  28                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  29                 interrupt-names = "intr", "msi";
  30
  31                 #interrupt-cells = <1>;
  32                 interrupt-map-mask = <0 0 0 0>;
  33                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  34
  35                 bus-range = <0x00 0xff>;
  36                 #address-cells = <3>;
  37                 #size-cells = <2>;
  38
  39                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
  40                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
  41                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
  42                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
  43                           0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
  44                           0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  45
  46                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  47                          <&tegra_car TEGRA30_CLK_AFI>,
  48                          <&tegra_car TEGRA30_CLK_PLL_E>,
  49                          <&tegra_car TEGRA30_CLK_CML0>;
  50                 clock-names = "pex", "afi", "pll_e", "cml";
  51                 resets = <&tegra_car 70>,
  52                          <&tegra_car 72>,
  53                          <&tegra_car 74>;
  54                 reset-names = "pex", "afi", "pcie_x";
  55                 status = "disabled";
  56
  57                 pci@1,0 {
  58                         device_type = "pci";
  59                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  60                         reg = <0x000800 0 0 0 0>;
  61                         status = "disabled";
  62
  63                         #address-cells = <3>;
  64                         #size-cells = <2>;
  65                         ranges;
  66
  67                         nvidia,num-lanes = <2>;
  68                 };
  69
  70                 pci@2,0 {
  71                         device_type = "pci";
  72                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  73                         reg = <0x001000 0 0 0 0>;
  74                         status = "disabled";
  75
  76                         #address-cells = <3>;
  77                         #size-cells = <2>;
  78                         ranges;
  79
  80                         nvidia,num-lanes = <2>;
  81                 };
  82
  83                 pci@3,0 {
  84                         device_type = "pci";
  85                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  86                         reg = <0x001800 0 0 0 0>;
  87                         status = "disabled";
  88
  89                         #address-cells = <3>;
  90                         #size-cells = <2>;
  91                         ranges;
  92
  93                         nvidia,num-lanes = <2>;
  94                 };
  95         };
  96
  97         host1x@50000000 {
  98                 compatible = "nvidia,tegra30-host1x", "simple-bus";
  99                 reg = <0x50000000 0x00024000>;
 100                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 101                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 102                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 103                 resets = <&tegra_car 28>;
 104                 reset-names = "host1x";
 105
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108
 109                 ranges = <0x54000000 0x54000000 0x04000000>;
 110
 111                 mpe@54040000 {
 112                         compatible = "nvidia,tegra30-mpe";
 113                         reg = <0x54040000 0x00040000>;
 114                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 115                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 116                         resets = <&tegra_car 60>;
 117                         reset-names = "mpe";
 118                 };
 119
 120                 vi@54080000 {
 121                         compatible = "nvidia,tegra30-vi";
 122                         reg = <0x54080000 0x00040000>;
 123                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 124                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 125                         resets = <&tegra_car 20>;
 126                         reset-names = "vi";
 127                 };
 128
 129                 epp@540c0000 {
 130                         compatible = "nvidia,tegra30-epp";
 131                         reg = <0x540c0000 0x00040000>;
 132                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 133                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 134                         resets = <&tegra_car 19>;
 135                         reset-names = "epp";
 136                 };
 137
 138                 isp@54100000 {
 139                         compatible = "nvidia,tegra30-isp";
 140                         reg = <0x54100000 0x00040000>;
 141                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 142                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 143                         resets = <&tegra_car 23>;
 144                         reset-names = "isp";
 145                 };
 146
 147                 gr2d@54140000 {
 148                         compatible = "nvidia,tegra30-gr2d";
 149                         reg = <0x54140000 0x00040000>;
 150                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 151                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 152                         resets = <&tegra_car 21>;
 153                         reset-names = "2d";
 154                 };
 155
 156                 gr3d@54180000 {
 157                         compatible = "nvidia,tegra30-gr3d";
 158                         reg = <0x54180000 0x00040000>;
 159                         clocks = <&tegra_car TEGRA30_CLK_GR3D
 160                                   &tegra_car TEGRA30_CLK_GR3D2>;
 161                         clock-names = "3d", "3d2";
 162                         resets = <&tegra_car 24>,
 163                                  <&tegra_car 98>;
 164                         reset-names = "3d", "3d2";
 165                 };
 166
 167                 dc@54200000 {
 168                         compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
 169                         reg = <0x54200000 0x00040000>;
 170                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 171                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 172                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 173                         clock-names = "dc", "parent";
 174                         resets = <&tegra_car 27>;
 175                         reset-names = "dc";
 176
 177                         nvidia,head = <0>;
 178
 179                         rgb {
 180                                 status = "disabled";
 181                         };
 182                 };
 183
 184                 dc@54240000 {
 185                         compatible = "nvidia,tegra30-dc";
 186                         reg = <0x54240000 0x00040000>;
 187                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 188                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 189                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 190                         clock-names = "dc", "parent";
 191                         resets = <&tegra_car 26>;
 192                         reset-names = "dc";
 193
 194                         nvidia,head = <1>;
 195
 196                         rgb {
 197                                 status = "disabled";
 198                         };
 199                 };
 200
 201                 hdmi@54280000 {
 202                         compatible = "nvidia,tegra30-hdmi";
 203                         reg = <0x54280000 0x00040000>;
 204                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 205                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 206                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 207                         clock-names = "hdmi", "parent";
 208                         resets = <&tegra_car 51>;
 209                         reset-names = "hdmi";
 210                         status = "disabled";
 211                 };
 212
 213                 tvo@542c0000 {
 214                         compatible = "nvidia,tegra30-tvo";
 215                         reg = <0x542c0000 0x00040000>;
 216                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 217                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 218                         status = "disabled";
 219                 };
 220
 221                 dsi@54300000 {
 222                         compatible = "nvidia,tegra30-dsi";
 223                         reg = <0x54300000 0x00040000>;
 224                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 225                         resets = <&tegra_car 48>;
 226                         reset-names = "dsi";
 227                         status = "disabled";
 228                 };
 229         };
 230
 231         timer@50004600 {
 232                 compatible = "arm,cortex-a9-twd-timer";
 233                 reg = <0x50040600 0x20>;
 234                 interrupts = <GIC_PPI 13
 235                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 236                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 237         };
 238
 239         intc: interrupt-controller@50041000 {
 240                 compatible = "arm,cortex-a9-gic";
 241                 reg = <0x50041000 0x1000
 242                        0x50040100 0x0100>;
 243                 interrupt-controller;
 244                 #interrupt-cells = <3>;
 245         };
 246
 247         cache-controller@50043000 {
 248                 compatible = "arm,pl310-cache";
 249                 reg = <0x50043000 0x1000>;
 250                 arm,data-latency = <6 6 2>;
 251                 arm,tag-latency = <5 5 2>;
 252                 cache-unified;
 253                 cache-level = <2>;
 254         };
 255
 256         timer@60005000 {
 257                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 258                 reg = <0x60005000 0x400>;
 259                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 265                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 266         };
 267
 268         tegra_car: clock@60006000 {
 269                 compatible = "nvidia,tegra30-car";
 270                 reg = <0x60006000 0x1000>;
 271                 #clock-cells = <1>;
 272                 #reset-cells = <1>;
 273         };
 274
 275         apbdma: dma@6000a000 {
 276                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 277                 reg = <0x6000a000 0x1400>;
 278                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 306                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 307                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 310                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 311                 resets = <&tegra_car 34>;
 312                 reset-names = "dma";
 313                 #dma-cells = <1>;
 314         };
 315
 316         ahb: ahb@6000c004 {
 317                 compatible = "nvidia,tegra30-ahb";
 318                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
 319         };
 320
 321         gpio: gpio@6000d000 {
 322                 compatible = "nvidia,tegra30-gpio";
 323                 reg = <0x6000d000 0x1000>;
 324                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 325                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 327                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 328                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 329                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 330                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 331                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 332                 #gpio-cells = <2>;
 333                 gpio-controller;
 334                 #interrupt-cells = <2>;
 335                 interrupt-controller;
 336         };
 337
 338         pinmux: pinmux@70000868 {
 339                 compatible = "nvidia,tegra30-pinmux";
 340                 reg = <0x70000868 0xd4    /* Pad control registers */
 341                        0x70003000 0x3e4>; /* Mux registers */
 342         };
 343
 344         /*
 345          * There are two serial driver i.e. 8250 based simple serial
 346          * driver and APB DMA based serial driver for higher baudrate
 347          * and performace. To enable the 8250 based driver, the compatible
 348          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 349          * the APB DMA based serial driver, the comptible is
 350          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 351          */
 352         uarta: serial@70006000 {
 353                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 354                 reg = <0x70006000 0x40>;
 355                 reg-shift = <2>;
 356                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 357                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 358                 resets = <&tegra_car 6>;
 359                 reset-names = "serial";
 360                 dmas = <&apbdma 8>, <&apbdma 8>;
 361                 dma-names = "rx", "tx";
 362                 status = "disabled";
 363         };
 364
 365         uartb: serial@70006040 {
 366                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 367                 reg = <0x70006040 0x40>;
 368                 reg-shift = <2>;
 369                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 370                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 371                 resets = <&tegra_car 7>;
 372                 reset-names = "serial";
 373                 dmas = <&apbdma 9>, <&apbdma 9>;
 374                 dma-names = "rx", "tx";
 375                 status = "disabled";
 376         };
 377
 378         uartc: serial@70006200 {
 379                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 380                 reg = <0x70006200 0x100>;
 381                 reg-shift = <2>;
 382                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 384                 resets = <&tegra_car 55>;
 385                 reset-names = "serial";
 386                 dmas = <&apbdma 10>, <&apbdma 10>;
 387                 dma-names = "rx", "tx";
 388                 status = "disabled";
 389         };
 390
 391         uartd: serial@70006300 {
 392                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 393                 reg = <0x70006300 0x100>;
 394                 reg-shift = <2>;
 395                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 397                 resets = <&tegra_car 65>;
 398                 reset-names = "serial";
 399                 dmas = <&apbdma 19>, <&apbdma 19>;
 400                 dma-names = "rx", "tx";
 401                 status = "disabled";
 402         };
 403
 404         uarte: serial@70006400 {
 405                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 406                 reg = <0x70006400 0x100>;
 407                 reg-shift = <2>;
 408                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 409                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 410                 resets = <&tegra_car 66>;
 411                 reset-names = "serial";
 412                 dmas = <&apbdma 20>, <&apbdma 20>;
 413                 dma-names = "rx", "tx";
 414                 status = "disabled";
 415         };
 416
 417         pwm: pwm@7000a000 {
 418                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 419                 reg = <0x7000a000 0x100>;
 420                 #pwm-cells = <2>;
 421                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 422                 resets = <&tegra_car 17>;
 423                 reset-names = "pwm";
 424                 status = "disabled";
 425         };
 426
 427         rtc@7000e000 {
 428                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 429                 reg = <0x7000e000 0x100>;
 430                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 431                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 432         };
 433
 434         i2c@7000c000 {
 435                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 436                 reg = <0x7000c000 0x100>;
 437                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 441                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 442                 clock-names = "div-clk", "fast-clk";
 443                 resets = <&tegra_car 12>;
 444                 reset-names = "i2c";
 445                 dmas = <&apbdma 21>, <&apbdma 21>;
 446                 dma-names = "rx", "tx";
 447                 status = "disabled";
 448         };
 449
 450         i2c@7000c400 {
 451                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 452                 reg = <0x7000c400 0x100>;
 453                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 457                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 458                 clock-names = "div-clk", "fast-clk";
 459                 resets = <&tegra_car 54>;
 460                 reset-names = "i2c";
 461                 dmas = <&apbdma 22>, <&apbdma 22>;
 462                 dma-names = "rx", "tx";
 463                 status = "disabled";
 464         };
 465
 466         i2c@7000c500 {
 467                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 468                 reg = <0x7000c500 0x100>;
 469                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 473                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 474                 clock-names = "div-clk", "fast-clk";
 475                 resets = <&tegra_car 67>;
 476                 reset-names = "i2c";
 477                 dmas = <&apbdma 23>, <&apbdma 23>;
 478                 dma-names = "rx", "tx";
 479                 status = "disabled";
 480         };
 481
 482         i2c@7000c700 {
 483                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 484                 reg = <0x7000c700 0x100>;
 485                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 489                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 490                 resets = <&tegra_car 103>;
 491                 reset-names = "i2c";
 492                 clock-names = "div-clk", "fast-clk";
 493                 dmas = <&apbdma 26>, <&apbdma 26>;
 494                 dma-names = "rx", "tx";
 495                 status = "disabled";
 496         };
 497
 498         i2c@7000d000 {
 499                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 500                 reg = <0x7000d000 0x100>;
 501                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 502                 #address-cells = <1>;
 503                 #size-cells = <0>;
 504                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 505                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 506                 clock-names = "div-clk", "fast-clk";
 507                 resets = <&tegra_car 47>;
 508                 reset-names = "i2c";
 509                 dmas = <&apbdma 24>, <&apbdma 24>;
 510                 dma-names = "rx", "tx";
 511                 status = "disabled";
 512         };
 513
 514         spi@7000d400 {
 515                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 516                 reg = <0x7000d400 0x200>;
 517                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 521                 resets = <&tegra_car 41>;
 522                 reset-names = "spi";
 523                 dmas = <&apbdma 15>, <&apbdma 15>;
 524                 dma-names = "rx", "tx";
 525                 status = "disabled";
 526         };
 527
 528         spi@7000d600 {
 529                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 530                 reg = <0x7000d600 0x200>;
 531                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 532                 #address-cells = <1>;
 533                 #size-cells = <0>;
 534                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 535                 resets = <&tegra_car 44>;
 536                 reset-names = "spi";
 537                 dmas = <&apbdma 16>, <&apbdma 16>;
 538                 dma-names = "rx", "tx";
 539                 status = "disabled";
 540         };
 541
 542         spi@7000d800 {
 543                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 544                 reg = <0x7000d800 0x200>;
 545                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 549                 resets = <&tegra_car 46>;
 550                 reset-names = "spi";
 551                 dmas = <&apbdma 17>, <&apbdma 17>;
 552                 dma-names = "rx", "tx";
 553                 status = "disabled";
 554         };
 555
 556         spi@7000da00 {
 557                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 558                 reg = <0x7000da00 0x200>;
 559                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 563                 resets = <&tegra_car 68>;
 564                 reset-names = "spi";
 565                 dmas = <&apbdma 18>, <&apbdma 18>;
 566                 dma-names = "rx", "tx";
 567                 status = "disabled";
 568         };
 569
 570         spi@7000dc00 {
 571                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 572                 reg = <0x7000dc00 0x200>;
 573                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 577                 resets = <&tegra_car 104>;
 578                 reset-names = "spi";
 579                 dmas = <&apbdma 27>, <&apbdma 27>;
 580                 dma-names = "rx", "tx";
 581                 status = "disabled";
 582         };
 583
 584         spi@7000de00 {
 585                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 586                 reg = <0x7000de00 0x200>;
 587                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 591                 resets = <&tegra_car 106>;
 592                 reset-names = "spi";
 593                 dmas = <&apbdma 28>, <&apbdma 28>;
 594                 dma-names = "rx", "tx";
 595                 status = "disabled";
 596         };
 597
 598         kbc@7000e200 {
 599                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 600                 reg = <0x7000e200 0x100>;
 601                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 602                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 603                 resets = <&tegra_car 36>;
 604                 reset-names = "kbc";
 605                 status = "disabled";
 606         };
 607
 608         pmc@7000e400 {
 609                 compatible = "nvidia,tegra30-pmc";
 610                 reg = <0x7000e400 0x400>;
 611                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 612                 clock-names = "pclk", "clk32k_in";
 613         };
 614
 615         memory-controller@7000f000 {
 616                 compatible = "nvidia,tegra30-mc";
 617                 reg = <0x7000f000 0x010
 618                        0x7000f03c 0x1b4
 619                        0x7000f200 0x028
 620                        0x7000f284 0x17c>;
 621                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 622         };
 623
 624         iommu@7000f010 {
 625                 compatible = "nvidia,tegra30-smmu";
 626                 reg = <0x7000f010 0x02c
 627                        0x7000f1f0 0x010
 628                        0x7000f228 0x05c>;
 629                 nvidia,#asids = <4>;            /* # of ASIDs */
 630                 dma-window = <0 0x40000000>;    /* IOVA start & length */
 631                 nvidia,ahb = <&ahb>;
 632         };
 633
 634         ahub@70080000 {
 635                 compatible = "nvidia,tegra30-ahub";
 636                 reg = <0x70080000 0x200
 637                        0x70080200 0x100>;
 638                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 639                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 640                          <&tegra_car TEGRA30_CLK_APBIF>;
 641                 clock-names = "d_audio", "apbif";
 642                 resets = <&tegra_car 106>, /* d_audio */
 643                          <&tegra_car 107>, /* apbif */
 644                          <&tegra_car 30>,  /* i2s0 */
 645                          <&tegra_car 11>,  /* i2s1 */
 646                          <&tegra_car 18>,  /* i2s2 */
 647                          <&tegra_car 101>, /* i2s3 */
 648                          <&tegra_car 102>, /* i2s4 */
 649                          <&tegra_car 108>, /* dam0 */
 650                          <&tegra_car 109>, /* dam1 */
 651                          <&tegra_car 110>, /* dam2 */
 652                          <&tegra_car 10>;  /* spdif */
 653                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 654                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 655                               "spdif";
 656                 dmas = <&apbdma 1>, <&apbdma 1>,
 657                        <&apbdma 2>, <&apbdma 2>,
 658                        <&apbdma 3>, <&apbdma 3>,
 659                        <&apbdma 4>, <&apbdma 4>;
 660                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 661                             "rx3", "tx3";
 662                 ranges;
 663                 #address-cells = <1>;
 664                 #size-cells = <1>;
 665
 666                 tegra_i2s0: i2s@70080300 {
 667                         compatible = "nvidia,tegra30-i2s";
 668                         reg = <0x70080300 0x100>;
 669                         nvidia,ahub-cif-ids = <4 4>;
 670                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 671                         resets = <&tegra_car 30>;
 672                         reset-names = "i2s";
 673                         status = "disabled";
 674                 };
 675
 676                 tegra_i2s1: i2s@70080400 {
 677                         compatible = "nvidia,tegra30-i2s";
 678                         reg = <0x70080400 0x100>;
 679                         nvidia,ahub-cif-ids = <5 5>;
 680                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 681                         resets = <&tegra_car 11>;
 682                         reset-names = "i2s";
 683                         status = "disabled";
 684                 };
 685
 686                 tegra_i2s2: i2s@70080500 {
 687                         compatible = "nvidia,tegra30-i2s";
 688                         reg = <0x70080500 0x100>;
 689                         nvidia,ahub-cif-ids = <6 6>;
 690                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 691                         resets = <&tegra_car 18>;
 692                         reset-names = "i2s";
 693                         status = "disabled";
 694                 };
 695
 696                 tegra_i2s3: i2s@70080600 {
 697                         compatible = "nvidia,tegra30-i2s";
 698                         reg = <0x70080600 0x100>;
 699                         nvidia,ahub-cif-ids = <7 7>;
 700                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 701                         resets = <&tegra_car 101>;
 702                         reset-names = "i2s";
 703                         status = "disabled";
 704                 };
 705
 706                 tegra_i2s4: i2s@70080700 {
 707                         compatible = "nvidia,tegra30-i2s";
 708                         reg = <0x70080700 0x100>;
 709                         nvidia,ahub-cif-ids = <8 8>;
 710                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 711                         resets = <&tegra_car 102>;
 712                         reset-names = "i2s";
 713                         status = "disabled";
 714                 };
 715         };
 716
 717         sdhci@78000000 {
 718                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 719                 reg = <0x78000000 0x200>;
 720                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 721                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 722                 resets = <&tegra_car 14>;
 723                 reset-names = "sdhci";
 724                 status = "disabled";
 725         };
 726
 727         sdhci@78000200 {
 728                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 729                 reg = <0x78000200 0x200>;
 730                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 731                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 732                 resets = <&tegra_car 9>;
 733                 reset-names = "sdhci";
 734                 status = "disabled";
 735         };
 736
 737         sdhci@78000400 {
 738                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 739                 reg = <0x78000400 0x200>;
 740                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 742                 resets = <&tegra_car 69>;
 743                 reset-names = "sdhci";
 744                 status = "disabled";
 745         };
 746
 747         sdhci@78000600 {
 748                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 749                 reg = <0x78000600 0x200>;
 750                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 751                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 752                 resets = <&tegra_car 15>;
 753                 reset-names = "sdhci";
 754                 status = "disabled";
 755         };
 756
 757         usb@7d000000 {
 758                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 759                 reg = <0x7d000000 0x4000>;
 760                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 761                 phy_type = "utmi";
 762                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 763                 resets = <&tegra_car 22>;
 764                 reset-names = "usb";
 765                 nvidia,needs-double-reset;
 766                 nvidia,phy = <&phy1>;
 767                 status = "disabled";
 768         };
 769
 770         phy1: usb-phy@7d000000 {
 771                 compatible = "nvidia,tegra30-usb-phy";
 772                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 773                 phy_type = "utmi";
 774                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 775                          <&tegra_car TEGRA30_CLK_PLL_U>,
 776                          <&tegra_car TEGRA30_CLK_USBD>;
 777                 clock-names = "reg", "pll_u", "utmi-pads";
 778                 nvidia,hssync-start-delay = <9>;
 779                 nvidia,idle-wait-delay = <17>;
 780                 nvidia,elastic-limit = <16>;
 781                 nvidia,term-range-adj = <6>;
 782                 nvidia,xcvr-setup = <51>;
 783                 nvidia.xcvr-setup-use-fuses;
 784                 nvidia,xcvr-lsfslew = <1>;
 785                 nvidia,xcvr-lsrslew = <1>;
 786                 nvidia,xcvr-hsslew = <32>;
 787                 nvidia,hssquelch-level = <2>;
 788                 nvidia,hsdiscon-level = <5>;
 789                 status = "disabled";
 790         };
 791
 792         usb@7d004000 {
 793                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 794                 reg = <0x7d004000 0x4000>;
 795                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 796                 phy_type = "utmi";
 797                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 798                 resets = <&tegra_car 58>;
 799                 reset-names = "usb";
 800                 nvidia,phy = <&phy2>;
 801                 status = "disabled";
 802         };
 803
 804         phy2: usb-phy@7d004000 {
 805                 compatible = "nvidia,tegra30-usb-phy";
 806                 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
 807                 phy_type = "utmi";
 808                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 809                          <&tegra_car TEGRA30_CLK_PLL_U>,
 810                          <&tegra_car TEGRA30_CLK_USBD>;
 811                 clock-names = "reg", "pll_u", "utmi-pads";
 812                 nvidia,hssync-start-delay = <9>;
 813                 nvidia,idle-wait-delay = <17>;
 814                 nvidia,elastic-limit = <16>;
 815                 nvidia,term-range-adj = <6>;
 816                 nvidia,xcvr-setup = <51>;
 817                 nvidia.xcvr-setup-use-fuses;
 818                 nvidia,xcvr-lsfslew = <2>;
 819                 nvidia,xcvr-lsrslew = <2>;
 820                 nvidia,xcvr-hsslew = <32>;
 821                 nvidia,hssquelch-level = <2>;
 822                 nvidia,hsdiscon-level = <5>;
 823                 status = "disabled";
 824         };
 825
 826         usb@7d008000 {
 827                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 828                 reg = <0x7d008000 0x4000>;
 829                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 830                 phy_type = "utmi";
 831                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 832                 resets = <&tegra_car 59>;
 833                 reset-names = "usb";
 834                 nvidia,phy = <&phy3>;
 835                 status = "disabled";
 836         };
 837
 838         phy3: usb-phy@7d008000 {
 839                 compatible = "nvidia,tegra30-usb-phy";
 840                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 841                 phy_type = "utmi";
 842                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 843                          <&tegra_car TEGRA30_CLK_PLL_U>,
 844                          <&tegra_car TEGRA30_CLK_USBD>;
 845                 clock-names = "reg", "pll_u", "utmi-pads";
 846                 nvidia,hssync-start-delay = <0>;
 847                 nvidia,idle-wait-delay = <17>;
 848                 nvidia,elastic-limit = <16>;
 849                 nvidia,term-range-adj = <6>;
 850                 nvidia,xcvr-setup = <51>;
 851                 nvidia.xcvr-setup-use-fuses;
 852                 nvidia,xcvr-lsfslew = <2>;
 853                 nvidia,xcvr-lsrslew = <2>;
 854                 nvidia,xcvr-hsslew = <32>;
 855                 nvidia,hssquelch-level = <2>;
 856                 nvidia,hsdiscon-level = <5>;
 857                 status = "disabled";
 858         };
 859
 860         cpus {
 861                 #address-cells = <1>;
 862                 #size-cells = <0>;
 863
 864                 cpu@0 {
 865                         device_type = "cpu";
 866                         compatible = "arm,cortex-a9";
 867                         reg = <0>;
 868                 };
 869
 870                 cpu@1 {
 871                         device_type = "cpu";
 872                         compatible = "arm,cortex-a9";
 873                         reg = <1>;
 874                 };
 875
 876                 cpu@2 {
 877                         device_type = "cpu";
 878                         compatible = "arm,cortex-a9";
 879                         reg = <2>;
 880                 };
 881
 882                 cpu@3 {
 883                         device_type = "cpu";
 884                         compatible = "arm,cortex-a9";
 885                         reg = <3>;
 886                 };
 887         };
 888
 889         pmu {
 890                 compatible = "arm,cortex-a9-pmu";
 891                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 892                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 893                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 894                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 895         };
 896 };