arch/arm/boot/dts/uniphier-pro5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier Pro5 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 / {
   9         compatible = "socionext,uniphier-pro5";
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16
  17                 cpu@0 {
  18                         device_type = "cpu";
  19                         compatible = "arm,cortex-a9";
  20                         reg = <0>;
  21                         clocks = <&sys_clk 32>;
  22                         enable-method = "psci";
  23                         next-level-cache = <&l2>;
  24                         operating-points-v2 = <&cpu_opp>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <1>;
  31                         clocks = <&sys_clk 32>;
  32                         enable-method = "psci";
  33                         next-level-cache = <&l2>;
  34                         operating-points-v2 = <&cpu_opp>;
  35                 };
  36         };
  37
  38         cpu_opp: opp-table {
  39                 compatible = "operating-points-v2";
  40                 opp-shared;
  41
  42                 opp-100000000 {
  43                         opp-hz = /bits/ 64 <100000000>;
  44                         clock-latency-ns = <300>;
  45                 };
  46                 opp-116667000 {
  47                         opp-hz = /bits/ 64 <116667000>;
  48                         clock-latency-ns = <300>;
  49                 };
  50                 opp-150000000 {
  51                         opp-hz = /bits/ 64 <150000000>;
  52                         clock-latency-ns = <300>;
  53                 };
  54                 opp-175000000 {
  55                         opp-hz = /bits/ 64 <175000000>;
  56                         clock-latency-ns = <300>;
  57                 };
  58                 opp-200000000 {
  59                         opp-hz = /bits/ 64 <200000000>;
  60                         clock-latency-ns = <300>;
  61                 };
  62                 opp-233334000 {
  63                         opp-hz = /bits/ 64 <233334000>;
  64                         clock-latency-ns = <300>;
  65                 };
  66                 opp-300000000 {
  67                         opp-hz = /bits/ 64 <300000000>;
  68                         clock-latency-ns = <300>;
  69                 };
  70                 opp-350000000 {
  71                         opp-hz = /bits/ 64 <350000000>;
  72                         clock-latency-ns = <300>;
  73                 };
  74                 opp-400000000 {
  75                         opp-hz = /bits/ 64 <400000000>;
  76                         clock-latency-ns = <300>;
  77                 };
  78                 opp-466667000 {
  79                         opp-hz = /bits/ 64 <466667000>;
  80                         clock-latency-ns = <300>;
  81                 };
  82                 opp-600000000 {
  83                         opp-hz = /bits/ 64 <600000000>;
  84                         clock-latency-ns = <300>;
  85                 };
  86                 opp-700000000 {
  87                         opp-hz = /bits/ 64 <700000000>;
  88                         clock-latency-ns = <300>;
  89                 };
  90                 opp-800000000 {
  91                         opp-hz = /bits/ 64 <800000000>;
  92                         clock-latency-ns = <300>;
  93                 };
  94                 opp-933334000 {
  95                         opp-hz = /bits/ 64 <933334000>;
  96                         clock-latency-ns = <300>;
  97                 };
  98                 opp-1200000000 {
  99                         opp-hz = /bits/ 64 <1200000000>;
 100                         clock-latency-ns = <300>;
 101                 };
 102                 opp-1400000000 {
 103                         opp-hz = /bits/ 64 <1400000000>;
 104                         clock-latency-ns = <300>;
 105                 };
 106         };
 107
 108         psci {
 109                 compatible = "arm,psci-0.2";
 110                 method = "smc";
 111         };
 112
 113         clocks {
 114                 refclk: ref {
 115                         compatible = "fixed-clock";
 116                         #clock-cells = <0>;
 117                         clock-frequency = <20000000>;
 118                 };
 119
 120                 arm_timer_clk: arm-timer {
 121                         #clock-cells = <0>;
 122                         compatible = "fixed-clock";
 123                         clock-frequency = <50000000>;
 124                 };
 125         };
 126
 127         soc {
 128                 compatible = "simple-bus";
 129                 #address-cells = <1>;
 130                 #size-cells = <1>;
 131                 ranges;
 132                 interrupt-parent = <&intc>;
 133
 134                 l2: l2-cache@500c0000 {
 135                         compatible = "socionext,uniphier-system-cache";
 136                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 137                               <0x506c0000 0x400>;
 138                         interrupts = <0 190 4>, <0 191 4>;
 139                         cache-unified;
 140                         cache-size = <(2 * 1024 * 1024)>;
 141                         cache-sets = <512>;
 142                         cache-line-size = <128>;
 143                         cache-level = <2>;
 144                         next-level-cache = <&l3>;
 145                 };
 146
 147                 l3: l3-cache@500c8000 {
 148                         compatible = "socionext,uniphier-system-cache";
 149                         reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
 150                               <0x506c8000 0x400>;
 151                         interrupts = <0 174 4>, <0 175 4>;
 152                         cache-unified;
 153                         cache-size = <(2 * 1024 * 1024)>;
 154                         cache-sets = <512>;
 155                         cache-line-size = <256>;
 156                         cache-level = <3>;
 157                 };
 158
 159                 serial0: serial@54006800 {
 160                         compatible = "socionext,uniphier-uart";
 161                         status = "disabled";
 162                         reg = <0x54006800 0x40>;
 163                         interrupts = <0 33 4>;
 164                         pinctrl-names = "default";
 165                         pinctrl-0 = <&pinctrl_uart0>;
 166                         clocks = <&peri_clk 0>;
 167                         resets = <&peri_rst 0>;
 168                 };
 169
 170                 serial1: serial@54006900 {
 171                         compatible = "socionext,uniphier-uart";
 172                         status = "disabled";
 173                         reg = <0x54006900 0x40>;
 174                         interrupts = <0 35 4>;
 175                         pinctrl-names = "default";
 176                         pinctrl-0 = <&pinctrl_uart1>;
 177                         clocks = <&peri_clk 1>;
 178                         resets = <&peri_rst 1>;
 179                 };
 180
 181                 serial2: serial@54006a00 {
 182                         compatible = "socionext,uniphier-uart";
 183                         status = "disabled";
 184                         reg = <0x54006a00 0x40>;
 185                         interrupts = <0 37 4>;
 186                         pinctrl-names = "default";
 187                         pinctrl-0 = <&pinctrl_uart2>;
 188                         clocks = <&peri_clk 2>;
 189                         resets = <&peri_rst 2>;
 190                 };
 191
 192                 serial3: serial@54006b00 {
 193                         compatible = "socionext,uniphier-uart";
 194                         status = "disabled";
 195                         reg = <0x54006b00 0x40>;
 196                         interrupts = <0 177 4>;
 197                         pinctrl-names = "default";
 198                         pinctrl-0 = <&pinctrl_uart3>;
 199                         clocks = <&peri_clk 3>;
 200                         resets = <&peri_rst 3>;
 201                 };
 202
 203                 gpio: gpio@55000000 {
 204                         compatible = "socionext,uniphier-gpio";
 205                         reg = <0x55000000 0x200>;
 206                         interrupt-parent = <&aidet>;
 207                         interrupt-controller;
 208                         #interrupt-cells = <2>;
 209                         gpio-controller;
 210                         #gpio-cells = <2>;
 211                         gpio-ranges = <&pinctrl 0 0 0>;
 212                         gpio-ranges-group-names = "gpio_range";
 213                         ngpios = <248>;
 214                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
 215                 };
 216
 217                 i2c0: i2c@58780000 {
 218                         compatible = "socionext,uniphier-fi2c";
 219                         status = "disabled";
 220                         reg = <0x58780000 0x80>;
 221                         #address-cells = <1>;
 222                         #size-cells = <0>;
 223                         interrupts = <0 41 4>;
 224                         pinctrl-names = "default";
 225                         pinctrl-0 = <&pinctrl_i2c0>;
 226                         clocks = <&peri_clk 4>;
 227                         resets = <&peri_rst 4>;
 228                         clock-frequency = <100000>;
 229                 };
 230
 231                 i2c1: i2c@58781000 {
 232                         compatible = "socionext,uniphier-fi2c";
 233                         status = "disabled";
 234                         reg = <0x58781000 0x80>;
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237                         interrupts = <0 42 4>;
 238                         pinctrl-names = "default";
 239                         pinctrl-0 = <&pinctrl_i2c1>;
 240                         clocks = <&peri_clk 5>;
 241                         resets = <&peri_rst 5>;
 242                         clock-frequency = <100000>;
 243                 };
 244
 245                 i2c2: i2c@58782000 {
 246                         compatible = "socionext,uniphier-fi2c";
 247                         status = "disabled";
 248                         reg = <0x58782000 0x80>;
 249                         #address-cells = <1>;
 250                         #size-cells = <0>;
 251                         interrupts = <0 43 4>;
 252                         pinctrl-names = "default";
 253                         pinctrl-0 = <&pinctrl_i2c2>;
 254                         clocks = <&peri_clk 6>;
 255                         resets = <&peri_rst 6>;
 256                         clock-frequency = <100000>;
 257                 };
 258
 259                 i2c3: i2c@58783000 {
 260                         compatible = "socionext,uniphier-fi2c";
 261                         status = "disabled";
 262                         reg = <0x58783000 0x80>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         interrupts = <0 44 4>;
 266                         pinctrl-names = "default";
 267                         pinctrl-0 = <&pinctrl_i2c3>;
 268                         clocks = <&peri_clk 7>;
 269                         resets = <&peri_rst 7>;
 270                         clock-frequency = <100000>;
 271                 };
 272
 273                 /* i2c4 does not exist */
 274
 275                 /* chip-internal connection for DMD */
 276                 i2c5: i2c@58785000 {
 277                         compatible = "socionext,uniphier-fi2c";
 278                         reg = <0x58785000 0x80>;
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                         interrupts = <0 25 4>;
 282                         clocks = <&peri_clk 9>;
 283                         resets = <&peri_rst 9>;
 284                         clock-frequency = <400000>;
 285                 };
 286
 287                 /* chip-internal connection for HDMI */
 288                 i2c6: i2c@58786000 {
 289                         compatible = "socionext,uniphier-fi2c";
 290                         reg = <0x58786000 0x80>;
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293                         interrupts = <0 26 4>;
 294                         clocks = <&peri_clk 10>;
 295                         resets = <&peri_rst 10>;
 296                         clock-frequency = <400000>;
 297                 };
 298
 299                 system_bus: system-bus@58c00000 {
 300                         compatible = "socionext,uniphier-system-bus";
 301                         status = "disabled";
 302                         reg = <0x58c00000 0x400>;
 303                         #address-cells = <2>;
 304                         #size-cells = <1>;
 305                         pinctrl-names = "default";
 306                         pinctrl-0 = <&pinctrl_system_bus>;
 307                 };
 308
 309                 smpctrl@59801000 {
 310                         compatible = "socionext,uniphier-smpctrl";
 311                         reg = <0x59801000 0x400>;
 312                 };
 313
 314                 sdctrl@59810000 {
 315                         compatible = "socionext,uniphier-pro5-sdctrl",
 316                                      "simple-mfd", "syscon";
 317                         reg = <0x59810000 0x400>;
 318
 319                         sd_clk: clock {
 320                                 compatible = "socionext,uniphier-pro5-sd-clock";
 321                                 #clock-cells = <1>;
 322                         };
 323
 324                         sd_rst: reset {
 325                                 compatible = "socionext,uniphier-pro5-sd-reset";
 326                                 #reset-cells = <1>;
 327                         };
 328                 };
 329
 330                 perictrl@59820000 {
 331                         compatible = "socionext,uniphier-pro5-perictrl",
 332                                      "simple-mfd", "syscon";
 333                         reg = <0x59820000 0x200>;
 334
 335                         peri_clk: clock {
 336                                 compatible = "socionext,uniphier-pro5-peri-clock";
 337                                 #clock-cells = <1>;
 338                         };
 339
 340                         peri_rst: reset {
 341                                 compatible = "socionext,uniphier-pro5-peri-reset";
 342                                 #reset-cells = <1>;
 343                         };
 344                 };
 345
 346                 soc-glue@5f800000 {
 347                         compatible = "socionext,uniphier-pro5-soc-glue",
 348                                      "simple-mfd", "syscon";
 349                         reg = <0x5f800000 0x2000>;
 350
 351                         pinctrl: pinctrl {
 352                                 compatible = "socionext,uniphier-pro5-pinctrl";
 353                         };
 354                 };
 355
 356                 soc-glue@5f900000 {
 357                         compatible = "socionext,uniphier-pro5-soc-glue-debug",
 358                                      "simple-mfd";
 359                         #address-cells = <1>;
 360                         #size-cells = <1>;
 361                         ranges = <0 0x5f900000 0x2000>;
 362
 363                         efuse@100 {
 364                                 compatible = "socionext,uniphier-efuse";
 365                                 reg = <0x100 0x28>;
 366                         };
 367
 368                         efuse@130 {
 369                                 compatible = "socionext,uniphier-efuse";
 370                                 reg = <0x130 0x8>;
 371                         };
 372
 373                         efuse@200 {
 374                                 compatible = "socionext,uniphier-efuse";
 375                                 reg = <0x200 0x28>;
 376                         };
 377
 378                         efuse@300 {
 379                                 compatible = "socionext,uniphier-efuse";
 380                                 reg = <0x300 0x14>;
 381                         };
 382
 383                         efuse@400 {
 384                                 compatible = "socionext,uniphier-efuse";
 385                                 reg = <0x400 0x8>;
 386                         };
 387                 };
 388
 389                 aidet: aidet@5fc20000 {
 390                         compatible = "socionext,uniphier-pro5-aidet";
 391                         reg = <0x5fc20000 0x200>;
 392                         interrupt-controller;
 393                         #interrupt-cells = <2>;
 394                 };
 395
 396                 timer@60000200 {
 397                         compatible = "arm,cortex-a9-global-timer";
 398                         reg = <0x60000200 0x20>;
 399                         interrupts = <1 11 0x304>;
 400                         clocks = <&arm_timer_clk>;
 401                 };
 402
 403                 timer@60000600 {
 404                         compatible = "arm,cortex-a9-twd-timer";
 405                         reg = <0x60000600 0x20>;
 406                         interrupts = <1 13 0x304>;
 407                         clocks = <&arm_timer_clk>;
 408                 };
 409
 410                 intc: interrupt-controller@60001000 {
 411                         compatible = "arm,cortex-a9-gic";
 412                         reg = <0x60001000 0x1000>,
 413                               <0x60000100 0x100>;
 414                         #interrupt-cells = <3>;
 415                         interrupt-controller;
 416                 };
 417
 418                 sysctrl@61840000 {
 419                         compatible = "socionext,uniphier-pro5-sysctrl",
 420                                      "simple-mfd", "syscon";
 421                         reg = <0x61840000 0x10000>;
 422
 423                         sys_clk: clock {
 424                                 compatible = "socionext,uniphier-pro5-clock";
 425                                 #clock-cells = <1>;
 426                         };
 427
 428                         sys_rst: reset {
 429                                 compatible = "socionext,uniphier-pro5-reset";
 430                                 #reset-cells = <1>;
 431                         };
 432                 };
 433
 434                 nand: nand@68000000 {
 435                         compatible = "socionext,uniphier-denali-nand-v5b";
 436                         status = "disabled";
 437                         reg-names = "nand_data", "denali_reg";
 438                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 439                         interrupts = <0 65 4>;
 440                         pinctrl-names = "default";
 441                         pinctrl-0 = <&pinctrl_nand2cs>;
 442                         clocks = <&sys_clk 2>;
 443                         resets = <&sys_rst 2>;
 444                 };
 445         };
 446 };
 447
 448 #include "uniphier-pinctrl.dtsi"