arch/arm/boot/dts/versatile-pb.dts

   1 #include <versatile-ab.dts>
   2
   3 / {
   4         model = "ARM Versatile PB";
   5         compatible = "arm,versatile-pb";
   6
   7         amba {
   8                 gpio2: gpio@101e6000 {
   9                         compatible = "arm,pl061", "arm,primecell";
  10                         reg = <0x101e6000 0x1000>;
  11                         interrupts = <8>;
  12                         gpio-controller;
  13                         #gpio-cells = <2>;
  14                         interrupt-controller;
  15                         #interrupt-cells = <2>;
  16                         clocks = <&pclk>;
  17                         clock-names = "apb_pclk";
  18                 };
  19
  20                 gpio3: gpio@101e7000 {
  21                         compatible = "arm,pl061", "arm,primecell";
  22                         reg = <0x101e7000 0x1000>;
  23                         interrupts = <9>;
  24                         gpio-controller;
  25                         #gpio-cells = <2>;
  26                         interrupt-controller;
  27                         #interrupt-cells = <2>;
  28                         clocks = <&pclk>;
  29                         clock-names = "apb_pclk";
  30                 };
  31
  32                 pci-controller@10001000 {
  33                         compatible = "arm,versatile-pci";
  34                         device_type = "pci";
  35                         reg = <0x10001000 0x1000
  36                                0x41000000 0x10000
  37                                0x42000000 0x100000>;
  38                         bus-range = <0 0xff>;
  39                         #address-cells = <3>;
  40                         #size-cells = <2>;
  41                         #interrupt-cells = <1>;
  42
  43                         ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000   /* downstream I/O */
  44                                   0x02000000 0 0x50000000 0x50000000 0 0x10000000   /* non-prefetchable memory */
  45                                   0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
  46
  47                         interrupt-map-mask = <0x1800 0 0 7>;
  48                         interrupt-map = <0x1800 0 0 1 &sic 28
  49                                          0x1800 0 0 2 &sic 29
  50                                          0x1800 0 0 3 &sic 30
  51                                          0x1800 0 0 4 &sic 27
  52
  53                                          0x1000 0 0 1 &sic 27
  54                                          0x1000 0 0 2 &sic 28
  55                                          0x1000 0 0 3 &sic 29
  56                                          0x1000 0 0 4 &sic 30
  57
  58                                          0x0800 0 0 1 &sic 30
  59                                          0x0800 0 0 2 &sic 27
  60                                          0x0800 0 0 3 &sic 28
  61                                          0x0800 0 0 4 &sic 29
  62
  63                                          0x0000 0 0 1 &sic 29
  64                                          0x0000 0 0 2 &sic 30
  65                                          0x0000 0 0 3 &sic 27
  66                                          0x0000 0 0 4 &sic 28>;
  67                 };
  68
  69                 fpga {
  70                         uart@9000 {
  71                                 compatible = "arm,pl011", "arm,primecell";
  72                                 reg = <0x9000 0x1000>;
  73                                 interrupt-parent = <&sic>;
  74                                 interrupts = <6>;
  75                                 clocks = <&xtal24mhz>, <&pclk>;
  76                                 clock-names = "uartclk", "apb_pclk";
  77                         };
  78                         sci@a000 {
  79                                 compatible = "arm,primecell";
  80                                 reg = <0xa000 0x1000>;
  81                                 interrupt-parent = <&sic>;
  82                                 interrupts = <5>;
  83                                 clocks = <&xtal24mhz>;
  84                                 clock-names = "apb_pclk";
  85                         };
  86                         mmc@b000 {
  87                                 compatible = "arm,pl180", "arm,primecell";
  88                                 reg = <0xb000 0x1000>;
  89                                 interrupts-extended = <&vic 23 &sic 2>;
  90                                 clocks = <&xtal24mhz>, <&pclk>;
  91                                 clock-names = "mclk", "apb_pclk";
  92                         };
  93                 };
  94         };
  95 };