arch/arm/boot/dts/vf610-twr.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 /dts-v1/;
   6 #include "vf610.dtsi"
   7
   8 / {
   9         model = "VF610 Tower Board";
  10         compatible = "fsl,vf610-twr", "fsl,vf610";
  11
  12         chosen {
  13                 bootargs = "console=ttyLP1,115200";
  14         };
  15
  16         memory@80000000 {
  17                 reg = <0x80000000 0x8000000>;
  18         };
  19
  20         audio_ext: mclk_osc {
  21                 compatible = "fixed-clock";
  22                 #clock-cells = <0>;
  23                 clock-frequency = <24576000>;
  24         };
  25
  26         enet_ext: eth_osc {
  27                 compatible = "fixed-clock";
  28                 #clock-cells = <0>;
  29                 clock-frequency = <50000000>;
  30         };
  31
  32         regulators {
  33                 compatible = "simple-bus";
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 reg_3p3v: regulator@0 {
  38                         compatible = "regulator-fixed";
  39                         reg = <0>;
  40                         regulator-name = "3P3V";
  41                         regulator-min-microvolt = <3300000>;
  42                         regulator-max-microvolt = <3300000>;
  43                         regulator-always-on;
  44                 };
  45
  46                 reg_vcc_3v3_mcu: regulator@1 {
  47                         compatible = "regulator-fixed";
  48                         reg = <1>;
  49                         regulator-name = "vcc_3v3_mcu";
  50                         regulator-min-microvolt = <3300000>;
  51                         regulator-max-microvolt = <3300000>;
  52                 };
  53         };
  54
  55         sound {
  56                 compatible = "simple-audio-card";
  57                 simple-audio-card,format = "i2s";
  58                 simple-audio-card,widgets =
  59                         "Microphone", "Microphone Jack",
  60                         "Headphone", "Headphone Jack",
  61                         "Speaker", "Speaker Ext",
  62                         "Line", "Line In Jack";
  63                 simple-audio-card,routing =
  64                         "MIC_IN", "Microphone Jack",
  65                         "Microphone Jack", "Mic Bias",
  66                         "LINE_IN", "Line In Jack",
  67                         "Headphone Jack", "HP_OUT",
  68                         "Speaker Ext", "LINE_OUT";
  69
  70                 simple-audio-card,cpu {
  71                         sound-dai = <&sai2>;
  72                         frame-master;
  73                         bitclock-master;
  74                 };
  75
  76                 simple-audio-card,codec {
  77                         sound-dai = <&codec>;
  78                         frame-master;
  79                         bitclock-master;
  80                 };
  81         };
  82 };
  83
  84 &adc0 {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_adc0_ad5>;
  87         vref-supply = <&reg_vcc_3v3_mcu>;
  88         status = "okay";
  89 };
  90
  91 &clks {
  92         clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
  93         clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
  94         assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
  95                           <&clks VF610_CLK_ENET_TS_SEL>;
  96         assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>,
  97                                  <&clks VF610_CLK_ENET_EXT>;
  98 };
  99
 100 &dspi0 {
 101         bus-num = <0>;
 102         pinctrl-names = "default";
 103         pinctrl-0 = <&pinctrl_dspi0>;
 104         status = "okay";
 105
 106         sflash: at26df081a@0 {
 107                 #address-cells = <1>;
 108                 #size-cells = <1>;
 109                 compatible = "atmel,at26df081a";
 110                 spi-max-frequency = <16000000>;
 111                 spi-cpol;
 112                 spi-cpha;
 113                 reg = <0>;
 114         };
 115 };
 116
 117 &edma0 {
 118         status = "okay";
 119 };
 120
 121 &esdhc1 {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&pinctrl_esdhc1>;
 124         bus-width = <4>;
 125         cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
 126         status = "okay";
 127 };
 128
 129 &fec0 {
 130         phy-mode = "rmii";
 131         phy-handle = <&ethphy0>;
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&pinctrl_fec0>;
 134         status = "okay";
 135
 136         mdio {
 137                 #address-cells = <1>;
 138                 #size-cells = <0>;
 139
 140                 ethphy0: ethernet-phy@0 {
 141                         reg = <0>;
 142                 };
 143
 144                 ethphy1: ethernet-phy@1 {
 145                         reg = <1>;
 146                 };
 147         };
 148 };
 149
 150 &fec1 {
 151         phy-mode = "rmii";
 152         phy-handle = <&ethphy1>;
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&pinctrl_fec1>;
 155         status = "okay";
 156 };
 157
 158 &i2c0 {
 159         clock-frequency = <100000>;
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_i2c0>;
 162         status = "okay";
 163
 164         codec: sgtl5000@a {
 165                #sound-dai-cells = <0>;
 166                compatible = "fsl,sgtl5000";
 167                reg = <0x0a>;
 168                VDDA-supply = <&reg_3p3v>;
 169                VDDIO-supply = <&reg_3p3v>;
 170                clocks = <&clks VF610_CLK_SAI2>;
 171        };
 172 };
 173
 174 &iomuxc {
 175         vf610-twr {
 176                 pinctrl_adc0_ad5: adc0ad5grp {
 177                         fsl,pins = <
 178                                 VF610_PAD_PTC30__ADC0_SE5               0xa1
 179                         >;
 180                 };
 181
 182                 pinctrl_dspi0: dspi0grp {
 183                         fsl,pins = <
 184                                 VF610_PAD_PTB19__DSPI0_CS0              0x1182
 185                                 VF610_PAD_PTB20__DSPI0_SIN              0x1181
 186                                 VF610_PAD_PTB21__DSPI0_SOUT             0x1182
 187                                 VF610_PAD_PTB22__DSPI0_SCK              0x1182
 188                         >;
 189                 };
 190
 191                 pinctrl_esdhc1: esdhc1grp {
 192                         fsl,pins = <
 193                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
 194                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
 195                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
 196                                 VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
 197                                 VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
 198                                 VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
 199                                 VF610_PAD_PTA7__GPIO_134        0x219d
 200                         >;
 201                 };
 202
 203                 pinctrl_fec0: fec0grp {
 204                         fsl,pins = <
 205                                 VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 206                                 VF610_PAD_PTC0__ENET_RMII0_MDC          0x30d3
 207                                 VF610_PAD_PTC1__ENET_RMII0_MDIO         0x30d1
 208                                 VF610_PAD_PTC2__ENET_RMII0_CRS          0x30d1
 209                                 VF610_PAD_PTC3__ENET_RMII0_RXD1         0x30d1
 210                                 VF610_PAD_PTC4__ENET_RMII0_RXD0         0x30d1
 211                                 VF610_PAD_PTC5__ENET_RMII0_RXER         0x30d1
 212                                 VF610_PAD_PTC6__ENET_RMII0_TXD1         0x30d2
 213                                 VF610_PAD_PTC7__ENET_RMII0_TXD0         0x30d2
 214                                 VF610_PAD_PTC8__ENET_RMII0_TXEN         0x30d2
 215                         >;
 216                 };
 217
 218                 pinctrl_fec1: fec1grp {
 219                         fsl,pins = <
 220                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 221                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 222                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 223                                 VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 224                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 225                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 226                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 227                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 228                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 229                         >;
 230                 };
 231
 232                 pinctrl_i2c0: i2c0grp {
 233                         fsl,pins = <
 234                                 VF610_PAD_PTB14__I2C0_SCL               0x30d3
 235                                 VF610_PAD_PTB15__I2C0_SDA               0x30d3
 236                         >;
 237                 };
 238
 239                 pinctrl_nfc: nfcgrp {
 240                         fsl,pins = <
 241                                 VF610_PAD_PTD31__NF_IO15        0x28df
 242                                 VF610_PAD_PTD30__NF_IO14        0x28df
 243                                 VF610_PAD_PTD29__NF_IO13        0x28df
 244                                 VF610_PAD_PTD28__NF_IO12        0x28df
 245                                 VF610_PAD_PTD27__NF_IO11        0x28df
 246                                 VF610_PAD_PTD26__NF_IO10        0x28df
 247                                 VF610_PAD_PTD25__NF_IO9         0x28df
 248                                 VF610_PAD_PTD24__NF_IO8         0x28df
 249                                 VF610_PAD_PTD23__NF_IO7         0x28df
 250                                 VF610_PAD_PTD22__NF_IO6         0x28df
 251                                 VF610_PAD_PTD21__NF_IO5         0x28df
 252                                 VF610_PAD_PTD20__NF_IO4         0x28df
 253                                 VF610_PAD_PTD19__NF_IO3         0x28df
 254                                 VF610_PAD_PTD18__NF_IO2         0x28df
 255                                 VF610_PAD_PTD17__NF_IO1         0x28df
 256                                 VF610_PAD_PTD16__NF_IO0         0x28df
 257                                 VF610_PAD_PTB24__NF_WE_B        0x28c2
 258                                 VF610_PAD_PTB25__NF_CE0_B       0x28c2
 259                                 VF610_PAD_PTB27__NF_RE_B        0x28c2
 260                                 VF610_PAD_PTC26__NF_RB_B        0x283d
 261                                 VF610_PAD_PTC27__NF_ALE         0x28c2
 262                                 VF610_PAD_PTC28__NF_CLE         0x28c2
 263                         >;
 264                 };
 265
 266                 pinctrl_pwm0: pwm0grp {
 267                         fsl,pins = <
 268                                 VF610_PAD_PTB0__FTM0_CH0                0x1582
 269                                 VF610_PAD_PTB1__FTM0_CH1                0x1582
 270                                 VF610_PAD_PTB2__FTM0_CH2                0x1582
 271                                 VF610_PAD_PTB3__FTM0_CH3                0x1582
 272                         >;
 273                 };
 274
 275                 pinctrl_sai2: sai2grp {
 276                         fsl,pins = <
 277                                 VF610_PAD_PTA16__SAI2_TX_BCLK           0x02ed
 278                                 VF610_PAD_PTA18__SAI2_TX_DATA           0x02ee
 279                                 VF610_PAD_PTA19__SAI2_TX_SYNC           0x02ed
 280                                 VF610_PAD_PTA21__SAI2_RX_BCLK           0x02ed
 281                                 VF610_PAD_PTA22__SAI2_RX_DATA           0x02ed
 282                                 VF610_PAD_PTA23__SAI2_RX_SYNC           0x02ed
 283                                 VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x02ed
 284                         >;
 285                 };
 286
 287                 pinctrl_uart1: uart1grp {
 288                         fsl,pins = <
 289                                 VF610_PAD_PTB4__UART1_TX                0x21a2
 290                                 VF610_PAD_PTB5__UART1_RX                0x21a1
 291                         >;
 292                 };
 293
 294                 pinctrl_uart2: uart2grp {
 295                         fsl,pins = <
 296                                 VF610_PAD_PTB6__UART2_TX                0x21a2
 297                                 VF610_PAD_PTB7__UART2_RX                0x21a1
 298                         >;
 299                 };
 300         };
 301 };
 302
 303 &nfc {
 304         assigned-clocks = <&clks VF610_CLK_NFC>;
 305         assigned-clock-rates = <33000000>;
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_nfc>;
 308         status = "okay";
 309
 310         nand@0 {
 311                 compatible = "fsl,vf610-nfc-nandcs";
 312                 reg = <0>;
 313                 #address-cells = <1>;
 314                 #size-cells = <1>;
 315                 nand-bus-width = <16>;
 316                 nand-ecc-mode = "hw";
 317                 nand-ecc-strength = <24>;
 318                 nand-ecc-step-size = <2048>;
 319                 nand-on-flash-bbt;
 320         };
 321 };
 322
 323 &pwm0 {
 324         pinctrl-names = "default";
 325         pinctrl-0 = <&pinctrl_pwm0>;
 326         status = "okay";
 327 };
 328
 329 &sai2 {
 330         #sound-dai-cells = <0>;
 331         pinctrl-names = "default";
 332         pinctrl-0 = <&pinctrl_sai2>;
 333         status = "okay";
 334 };
 335
 336 &uart1 {
 337         pinctrl-names = "default";
 338         pinctrl-0 = <&pinctrl_uart1>;
 339         status = "okay";
 340 };
 341
 342 &uart2 {
 343         pinctrl-names = "default";
 344         pinctrl-0 = <&pinctrl_uart2>;
 345         status = "okay";
 346 };
 347
 348 &usbdev0 {
 349         disable-over-current;
 350         status = "okay";
 351 };
 352
 353 &usbh1 {
 354         disable-over-current;
 355         status = "okay";
 356 };
 357
 358 &usbmisc0 {
 359         status = "okay";
 360 };
 361
 362 &usbmisc1 {
 363         status = "okay";
 364 };
 365
 366 &usbphy0 {
 367         status = "okay";
 368 };
 369
 370 &usbphy1 {
 371         status = "okay";
 372 };