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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / vf610-zii-dev-rev-b.dts
1 /*
2 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
3 *
4 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
5 * Freescale Semiconductor, Inc.
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 as published by the Free Software Foundation.
15 *
16 * This file is distributed in the hope that it will be useful
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 /dts-v1/;
46 #include "vf610.dtsi"
47
48 / {
49 model = "ZII VF610 Development Board, Rev B";
50 compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
51
52 chosen {
53 stdout-path = "serial0:115200n8";
54 };
55
56 memory {
57 reg = <0x80000000 0x20000000>;
58 };
59
60 gpio-leds {
61 compatible = "gpio-leds";
62 pinctrl-0 = <&pinctrl_leds_debug>;
63 pinctrl-names = "default";
64
65 debug {
66 label = "zii:green:debug1";
67 gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
68 linux,default-trigger = "heartbeat";
69 };
70 };
71
72 mdio-mux {
73 compatible = "mdio-mux-gpio";
74 pinctrl-0 = <&pinctrl_mdio_mux>;
75 pinctrl-names = "default";
76 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
77 &gpio0 9 GPIO_ACTIVE_HIGH
78 &gpio0 24 GPIO_ACTIVE_HIGH
79 &gpio0 25 GPIO_ACTIVE_HIGH>;
80 mdio-parent-bus = <&mdio1>;
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 mdio_mux_1: mdio@1 {
85 reg = <1>;
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 switch0: switch0@0 {
90 compatible = "marvell,mv88e6085";
91 pinctrl-0 = <&pinctrl_gpio_switch0>;
92 pinctrl-names = "default";
93 #address-cells = <1>;
94 #size-cells = <0>;
95 reg = <0>;
96 dsa,member = <0 0>;
97 interrupt-parent = <&gpio0>;
98 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
99 interrupt-controller;
100 #interrupt-cells = <2>;
101
102 ports {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 port@0 {
106 reg = <0>;
107 label = "lan0";
108 phy-handle = <&switch0phy0>;
109 };
110
111 port@1 {
112 reg = <1>;
113 label = "lan1";
114 phy-handle = <&switch0phy1>;
115 };
116
117 port@2 {
118 reg = <2>;
119 label = "lan2";
120 phy-handle = <&switch0phy2>;
121 };
122
123 switch0port5: port@5 {
124 reg = <5>;
125 label = "dsa";
126 phy-mode = "rgmii-txid";
127 link = <&switch1port6
128 &switch2port9>;
129 fixed-link {
130 speed = <1000>;
131 full-duplex;
132 };
133 };
134
135 port@6 {
136 reg = <6>;
137 label = "cpu";
138 ethernet = <&fec1>;
139 fixed-link {
140 speed = <100>;
141 full-duplex;
142 };
143 };
144 };
145 mdio {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 switch0phy0: switch0phy0@0 {
149 reg = <0>;
150 interrupt-parent = <&switch0>;
151 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
152 };
153 switch0phy1: switch1phy0@1 {
154 reg = <1>;
155 interrupt-parent = <&switch0>;
156 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; };
157 switch0phy2: switch1phy0@2 {
158 reg = <2>;
159 interrupt-parent = <&switch0>;
160 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
161 };
162 };
163 };
164 };
165
166 mdio_mux_2: mdio@2 {
167 reg = <2>;
168 #address-cells = <1>;
169 #size-cells = <0>;
170
171 switch1: switch1@0 {
172 compatible = "marvell,mv88e6085";
173 pinctrl-0 = <&pinctrl_gpio_switch1>;
174 pinctrl-names = "default";
175 #address-cells = <1>;
176 #size-cells = <0>;
177 reg = <0>;
178 dsa,member = <0 1>;
179 interrupt-parent = <&gpio0>;
180 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
183
184 ports {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 port@0 {
188 reg = <0>;
189 label = "lan3";
190 phy-handle = <&switch1phy0>;
191 };
192
193 port@1 {
194 reg = <1>;
195 label = "lan4";
196 phy-handle = <&switch1phy1>;
197 };
198
199 port@2 {
200 reg = <2>;
201 label = "lan5";
202 phy-handle = <&switch1phy2>;
203 };
204
205 switch1port5: port@5 {
206 reg = <5>;
207 label = "dsa";
208 link = <&switch2port9>;
209 phy-mode = "rgmii-txid";
210 fixed-link {
211 speed = <1000>;
212 full-duplex;
213 };
214 };
215
216 switch1port6: port@6 {
217 reg = <6>;
218 label = "dsa";
219 phy-mode = "rgmii-txid";
220 link = <&switch0port5>;
221 fixed-link {
222 speed = <1000>;
223 full-duplex;
224 };
225 };
226 };
227 mdio {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 switch1phy0: switch1phy0@0 {
231 reg = <0>;
232 interrupt-parent = <&switch1>;
233 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
234 };
235 switch1phy1: switch1phy0@1 {
236 reg = <1>;
237 interrupt-parent = <&switch1>;
238 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
239 };
240 switch1phy2: switch1phy0@2 {
241 reg = <2>;
242 interrupt-parent = <&switch1>;
243 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
244 };
245 };
246 };
247 };
248
249 mdio_mux_4: mdio@4 {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 reg = <4>;
253
254 switch2: switch2@0 {
255 compatible = "marvell,mv88e6085";
256 #address-cells = <1>;
257 #size-cells = <0>;
258 reg = <0>;
259 dsa,member = <0 2>;
260
261 ports {
262 #address-cells = <1>;
263 #size-cells = <0>;
264 port@0 {
265 reg = <0>;
266 label = "lan6";
267 };
268
269 port@1 {
270 reg = <1>;
271 label = "lan7";
272 };
273
274 port@2 {
275 reg = <2>;
276 label = "lan8";
277 };
278
279 port@3 {
280 reg = <3>;
281 label = "optical3";
282 fixed-link {
283 speed = <1000>;
284 full-duplex;
285 link-gpios = <&gpio6 2
286 GPIO_ACTIVE_HIGH>;
287 };
288 };
289
290 port@4 {
291 reg = <4>;
292 label = "optical4";
293 fixed-link {
294 speed = <1000>;
295 full-duplex;
296 link-gpios = <&gpio6 3
297 GPIO_ACTIVE_HIGH>;
298 };
299 };
300
301 switch2port9: port@9 {
302 reg = <9>;
303 label = "dsa";
304 phy-mode = "rgmii-txid";
305 link = <&switch1port5
306 &switch0port5>;
307 fixed-link {
308 speed = <1000>;
309 full-duplex;
310 };
311 };
312 };
313 };
314 };
315
316 mdio_mux_8: mdio@8 {
317 reg = <8>;
318 #address-cells = <1>;
319 #size-cells = <0>;
320 };
321 };
322
323 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
324 compatible = "regulator-fixed";
325 regulator-name = "vcc_3v3_mcu";
326 regulator-min-microvolt = <3300000>;
327 regulator-max-microvolt = <3300000>;
328 };
329
330 usb0_vbus: regulator-usb0-vbus {
331 compatible = "regulator-fixed";
332 pinctrl-0 = <&pinctrl_usb_vbus>;
333 regulator-name = "usb_vbus";
334 regulator-min-microvolt = <5000000>;
335 regulator-max-microvolt = <5000000>;
336 enable-active-high;
337 regulator-always-on;
338 regulator-boot-on;
339 gpio = <&gpio0 6 0>;
340 };
341
342 spi0 {
343 compatible = "spi-gpio";
344 pinctrl-0 = <&pinctrl_gpio_spi0>;
345 pinctrl-names = "default";
346 #address-cells = <1>;
347 #size-cells = <0>;
348 gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
349 gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
350 gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
351 cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
352 &gpio1 8 GPIO_ACTIVE_HIGH>;
353 num-chipselects = <2>;
354
355 m25p128@0 {
356 compatible = "m25p128", "jedec,spi-nor";
357 #address-cells = <1>;
358 #size-cells = <1>;
359 reg = <0>;
360 spi-max-frequency = <1000000>;
361 };
362
363 at93c46d@1 {
364 compatible = "atmel,at93c46d";
365 pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
366 pinctrl-names = "default";
367 #address-cells = <0>;
368 #size-cells = <0>;
369 reg = <1>;
370 spi-max-frequency = <500000>;
371 spi-cs-high;
372 data-size = <16>;
373 select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
374 };
375 };
376 };
377
378 &adc0 {
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_adc0_ad5>;
381 vref-supply = <&reg_vcc_3v3_mcu>;
382 status = "okay";
383 };
384
385 &edma0 {
386 status = "okay";
387 };
388
389 &esdhc1 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_esdhc1>;
392 bus-width = <4>;
393 status = "okay";
394 };
395
396 &fec0 {
397 phy-mode = "rmii";
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_fec0>;
400 status = "okay";
401 };
402
403 &fec1 {
404 phy-mode = "rmii";
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_fec1>;
407 status = "okay";
408
409 fixed-link {
410 speed = <100>;
411 full-duplex;
412 };
413
414 mdio1: mdio {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 status = "okay";
418 };
419 };
420
421 &i2c0 {
422 clock-frequency = <100000>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_i2c0>;
425 status = "okay";
426
427 gpio5: pca9554@20 {
428 compatible = "nxp,pca9554";
429 reg = <0x20>;
430 gpio-controller;
431 #gpio-cells = <2>;
432
433 };
434
435 gpio6: pca9554@22 {
436 compatible = "nxp,pca9554";
437 pinctrl-names = "default";
438 pinctrl-0 = <&pinctrl_pca9554_22>;
439 reg = <0x22>;
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-parent = <&gpio2>;
443 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
444 };
445
446 lm75@48 {
447 compatible = "national,lm75";
448 reg = <0x48>;
449 };
450
451 at24c04@50 {
452 compatible = "atmel,24c04";
453 reg = <0x50>;
454 };
455
456 at24c04@52 {
457 compatible = "atmel,24c04";
458 reg = <0x52>;
459 };
460
461 ds1682@6b {
462 compatible = "dallas,ds1682";
463 reg = <0x6b>;
464 };
465 };
466
467 &i2c1 {
468 clock-frequency = <100000>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_i2c1>;
471 status = "okay";
472 };
473
474 &i2c2 {
475 clock-frequency = <100000>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_i2c2>;
478 status = "okay";
479
480 tca9548@70 {
481 compatible = "nxp,pca9548";
482 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
483 pinctrl-names = "default";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 reg = <0x70>;
487 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
488
489 i2c@0 {
490 #address-cells = <1>;
491 #size-cells = <0>;
492 reg = <0>;
493
494 sfp1: at24c04@50 {
495 compatible = "atmel,24c02";
496 reg = <0x50>;
497 };
498 };
499
500 i2c@1 {
501 #address-cells = <1>;
502 #size-cells = <0>;
503 reg = <1>;
504
505 sfp2: at24c04@50 {
506 compatible = "atmel,24c02";
507 reg = <0x50>;
508 };
509 };
510
511 i2c@2 {
512 #address-cells = <1>;
513 #size-cells = <0>;
514 reg = <2>;
515
516 sfp3: at24c04@50 {
517 compatible = "atmel,24c02";
518 reg = <0x50>;
519 };
520 };
521
522 i2c@3 {
523 #address-cells = <1>;
524 #size-cells = <0>;
525 reg = <3>;
526
527 sfp4: at24c04@50 {
528 compatible = "atmel,24c02";
529 reg = <0x50>;
530 };
531 };
532
533 i2c@4 {
534 #address-cells = <1>;
535 #size-cells = <0>;
536 reg = <4>;
537 };
538 };
539 };
540
541 &uart0 {
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_uart0>;
544 status = "okay";
545 };
546
547 &uart1 {
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_uart1>;
550 status = "okay";
551 };
552
553 &uart2 {
554 pinctrl-names = "default";
555 pinctrl-0 = <&pinctrl_uart2>;
556 status = "okay";
557 };
558
559 &usbdev0 {
560 disable-over-current;
561 vbus-supply = <&usb0_vbus>;
562 dr_mode = "host";
563 status = "okay";
564 };
565
566 &usbh1 {
567 disable-over-current;
568 status = "okay";
569 };
570
571 &usbmisc0 {
572 status = "okay";
573 };
574
575 &usbmisc1 {
576 status = "okay";
577 };
578
579 &usbphy0 {
580 status = "okay";
581 };
582
583 &usbphy1 {
584 status = "okay";
585 };
586
587 &iomuxc {
588 pinctrl_adc0_ad5: adc0ad5grp {
589 fsl,pins = <
590 VF610_PAD_PTC30__ADC0_SE5 0x00a1
591 >;
592 };
593
594 pinctrl_dspi0: dspi0grp {
595 fsl,pins = <
596 VF610_PAD_PTB18__DSPI0_CS1 0x1182
597 VF610_PAD_PTB19__DSPI0_CS0 0x1182
598 VF610_PAD_PTB20__DSPI0_SIN 0x1181
599 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
600 VF610_PAD_PTB22__DSPI0_SCK 0x1182
601 >;
602 };
603
604 pinctrl_dspi2: dspi2grp {
605 fsl,pins = <
606 VF610_PAD_PTD31__DSPI2_CS1 0x1182
607 VF610_PAD_PTD30__DSPI2_CS0 0x1182
608 VF610_PAD_PTD29__DSPI2_SIN 0x1181
609 VF610_PAD_PTD28__DSPI2_SOUT 0x1182
610 VF610_PAD_PTD27__DSPI2_SCK 0x1182
611 >;
612 };
613
614 pinctrl_esdhc1: esdhc1grp {
615 fsl,pins = <
616 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
617 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
618 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
619 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
620 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
621 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
622 VF610_PAD_PTA7__GPIO_134 0x219d
623 >;
624 };
625
626 pinctrl_fec0: fec0grp {
627 fsl,pins = <
628 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2
629 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3
630 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
631 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
632 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
633 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
634 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
635 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
636 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
637 >;
638 };
639
640 pinctrl_fec1: fec1grp {
641 fsl,pins = <
642 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
643 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
644 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
645 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
646 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
647 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
648 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
649 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
650 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
651 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
652 >;
653 };
654
655 pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
656 fsl,pins = <
657 VF610_PAD_PTE27__GPIO_132 0x33e2
658 >;
659 };
660
661 pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
662 fsl,pins = <
663 VF610_PAD_PTB22__GPIO_44 0x33e2
664 VF610_PAD_PTB21__GPIO_43 0x33e2
665 VF610_PAD_PTB20__GPIO_42 0x33e1
666 VF610_PAD_PTB19__GPIO_41 0x33e2
667 VF610_PAD_PTB18__GPIO_40 0x33e2
668 >;
669 };
670
671 pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
672 fsl,pins = <
673 VF610_PAD_PTB5__GPIO_27 0x219d
674 >;
675 };
676
677 pinctrl_gpio_switch1: pinctrl-gpio-switch1 {
678 fsl,pins = <
679 VF610_PAD_PTB4__GPIO_26 0x219d
680 >;
681 };
682
683 pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
684 fsl,pins = <
685 VF610_PAD_PTE14__GPIO_119 0x31c2
686 >;
687 };
688
689 pinctrl_i2c0: i2c0grp {
690 fsl,pins = <
691 VF610_PAD_PTB14__I2C0_SCL 0x37ff
692 VF610_PAD_PTB15__I2C0_SDA 0x37ff
693 >;
694 };
695
696 pinctrl_i2c1: i2c1grp {
697 fsl,pins = <
698 VF610_PAD_PTB16__I2C1_SCL 0x37ff
699 VF610_PAD_PTB17__I2C1_SDA 0x37ff
700 >;
701 };
702
703 pinctrl_i2c2: i2c2grp {
704 fsl,pins = <
705 VF610_PAD_PTA22__I2C2_SCL 0x37ff
706 VF610_PAD_PTA23__I2C2_SDA 0x37ff
707 >;
708 };
709
710 pinctrl_leds_debug: pinctrl-leds-debug {
711 fsl,pins = <
712 VF610_PAD_PTD20__GPIO_74 0x31c2
713 >;
714 };
715
716 pinctrl_mdio_mux: pinctrl-mdio-mux {
717 fsl,pins = <
718 VF610_PAD_PTA18__GPIO_8 0x31c2
719 VF610_PAD_PTA19__GPIO_9 0x31c2
720 VF610_PAD_PTB2__GPIO_24 0x31c2
721 VF610_PAD_PTB3__GPIO_25 0x31c2
722 >;
723 };
724
725 pinctrl_pca9554_22: pinctrl-pca95540-22 {
726 fsl,pins = <
727 VF610_PAD_PTB28__GPIO_98 0x219d
728 >;
729 };
730
731 pinctrl_pwm0: pwm0grp {
732 fsl,pins = <
733 VF610_PAD_PTB0__FTM0_CH0 0x1582
734 VF610_PAD_PTB1__FTM0_CH1 0x1582
735 VF610_PAD_PTB2__FTM0_CH2 0x1582
736 VF610_PAD_PTB3__FTM0_CH3 0x1582
737 >;
738 };
739
740 pinctrl_qspi0: qspi0grp {
741 fsl,pins = <
742 VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3
743 VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff
744 VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3
745 VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3
746 VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3
747 VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3
748 >;
749 };
750
751 pinctrl_uart0: uart0grp {
752 fsl,pins = <
753 VF610_PAD_PTB10__UART0_TX 0x21a2
754 VF610_PAD_PTB11__UART0_RX 0x21a1
755 >;
756 };
757
758 pinctrl_uart1: uart1grp {
759 fsl,pins = <
760 VF610_PAD_PTB23__UART1_TX 0x21a2
761 VF610_PAD_PTB24__UART1_RX 0x21a1
762 >;
763 };
764
765 pinctrl_uart2: uart2grp {
766 fsl,pins = <
767 VF610_PAD_PTD0__UART2_TX 0x21a2
768 VF610_PAD_PTD1__UART2_RX 0x21a1
769 >;
770 };
771
772 pinctrl_usb_vbus: pinctrl-usb-vbus {
773 fsl,pins = <
774 VF610_PAD_PTA16__GPIO_6 0x31c2
775 >;
776 };
777
778 pinctrl_usb0_host: usb0-host-grp {
779 fsl,pins = <
780 VF610_PAD_PTD6__GPIO_85 0x0062
781 >;
782 };
783 };
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