arch/arm/boot/dts/vf610-zii-dev-rev-c.dts

   1 /*
   2  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   3  *
   4  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
   5  * Freescale Semiconductor, Inc.
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License
  14  *     version 2 as published by the Free Software Foundation.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "vf610-zii-dev.dtsi"
  47
  48 / {
  49         model = "ZII VF610 Development Board, Rev C";
  50         compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
  51
  52         mdio-mux {
  53                 compatible = "mdio-mux-gpio";
  54                 pinctrl-0 = <&pinctrl_mdio_mux>;
  55                 pinctrl-names = "default";
  56                 gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
  57                          &gpio0 9  GPIO_ACTIVE_HIGH
  58                          &gpio0 25 GPIO_ACTIVE_HIGH>;
  59                 mdio-parent-bus = <&mdio1>;
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 mdio_mux_1: mdio@1 {
  64                         reg = <1>;
  65                         #address-cells = <1>;
  66                         #size-cells = <0>;
  67
  68                         switch0: switch@0 {
  69                                 compatible = "marvell,mv88e6190";
  70                                 #address-cells = <1>;
  71                                 #size-cells = <0>;
  72                                 reg = <0>;
  73                                 dsa,member = <0 0>;
  74                                 eeprom-length = <512>;
  75
  76                                 ports {
  77                                         #address-cells = <1>;
  78                                         #size-cells = <0>;
  79
  80                                         port@0 {
  81                                                 reg = <0>;
  82                                                 label = "cpu";
  83                                                 ethernet = <&fec1>;
  84
  85                                                 fixed-link {
  86                                                         speed = <100>;
  87                                                         full-duplex;
  88                                                 };
  89                                         };
  90
  91                                         port@1 {
  92                                                 reg = <1>;
  93                                                 label = "lan1";
  94                                         };
  95
  96                                         port@2 {
  97                                                 reg = <2>;
  98                                                 label = "lan2";
  99                                         };
 100
 101                                         port@3 {
 102                                                 reg = <3>;
 103                                                 label = "lan3";
 104                                         };
 105
 106                                         port@4 {
 107                                                 reg = <4>;
 108                                                 label = "lan4";
 109                                         };
 110
 111                                         switch0port10: port@10 {
 112                                                 reg = <10>;
 113                                                 label = "dsa";
 114                                                 phy-mode = "xgmii";
 115                                                 link = <&switch1port10>;
 116                                         };
 117                                 };
 118                         };
 119                 };
 120
 121                 mdio_mux_2: mdio@2 {
 122                         reg = <2>;
 123                         #address-cells = <1>;
 124                         #size-cells = <0>;
 125
 126                         switch1: switch@0 {
 127                                 compatible = "marvell,mv88e6190";
 128                                 #address-cells = <1>;
 129                                 #size-cells = <0>;
 130                                 reg = <0>;
 131                                 dsa,member = <0 1>;
 132                                 eeprom-length = <512>;
 133
 134                                 ports {
 135                                         #address-cells = <1>;
 136                                         #size-cells = <0>;
 137
 138                                         port@1 {
 139                                                 reg = <1>;
 140                                                 label = "lan5";
 141                                         };
 142
 143                                         port@2 {
 144                                                 reg = <2>;
 145                                                 label = "lan6";
 146                                         };
 147
 148                                         port@3 {
 149                                                 reg = <3>;
 150                                                 label = "lan7";
 151                                         };
 152
 153                                         port@4 {
 154                                                 reg = <4>;
 155                                                 label = "lan8";
 156                                         };
 157
 158
 159                                         switch1port10: port@10 {
 160                                                 reg = <10>;
 161                                                 label = "dsa";
 162                                                 phy-mode = "xgmii";
 163                                                 link = <&switch0port10>;
 164                                         };
 165                                 };
 166                         };
 167                 };
 168
 169                 mdio_mux_4: mdio@4 {
 170                         reg = <4>;
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                 };
 174         };
 175 };
 176
 177 &dspi0 {
 178         bus-num = <0>;
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_dspi0>;
 181         status = "okay";
 182         spi-num-chipselects = <2>;
 183
 184         m25p128@0 {
 185                 compatible = "m25p128", "jedec,spi-nor";
 186                 #address-cells = <1>;
 187                 #size-cells = <1>;
 188                 reg = <0>;
 189                 spi-max-frequency = <1000000>;
 190         };
 191
 192         atzb-rf-233@1 {
 193                 compatible = "atmel,at86rf233";
 194
 195                 pinctrl-names = "default";
 196                 pinctrl-0 = <&pinctr_atzb_rf_233>;
 197
 198                 spi-max-frequency = <7500000>;
 199                 reg = <1>;
 200                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 201                 interrupt-parent = <&gpio3>;
 202                 xtal-trim = /bits/ 8 <0x06>;
 203
 204                 sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
 205                 reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
 206
 207                 fsl,spi-cs-sck-delay = <180>;
 208                 fsl,spi-sck-cs-delay = <250>;
 209         };
 210 };
 211
 212 &i2c0 {
 213         /*
 214          * U712
 215          *
 216          * Exposed signals:
 217          *    P1 - WE2_CMD
 218          *    P2 - WE2_CLK
 219          */
 220         gpio5: pca9557@18 {
 221                 compatible = "nxp,pca9557";
 222                 reg = <0x18>;
 223                 gpio-controller;
 224                 #gpio-cells = <2>;
 225         };
 226
 227         /*
 228          * U121
 229          *
 230          * Exposed signals:
 231          *    I/O0  - ENET_SWR_EN
 232          *    I/O1  - ESW1_RESETn
 233          *    I/O2  - ARINC_RESET
 234          *    I/O3  - DD1_IO_RESET
 235          *    I/O4  - ESW2_RESETn
 236          *    I/O5  - ESW3_RESETn
 237          *    I/O6  - ESW4_RESETn
 238          *    I/O8  - TP909
 239          *    I/O9  - FEM_SEL
 240          *    I/O10 - WIFI_RESETn
 241          *    I/O11 - PHY_RSTn
 242          *    I/O12 - OPT1_SD
 243          *    I/O13 - OPT2_SD
 244          *    I/O14 - OPT1_TX_DIS
 245          *    I/O15 - OPT2_TX_DIS
 246          */
 247         gpio6: sx1503@20 {
 248                 compatible = "semtech,sx1503q";
 249
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&pinctrl_sx1503_20>;
 252                 #gpio-cells = <2>;
 253                 #interrupt-cells = <2>;
 254                 reg = <0x20>;
 255                 interrupt-parent = <&gpio0>;
 256                 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
 257                 gpio-controller;
 258                 interrupt-controller;
 259
 260                 enet_swr_en {
 261                         gpio-hog;
 262                         gpios = <0 GPIO_ACTIVE_HIGH>;
 263                         output-high;
 264                         line-name = "enet-swr-en";
 265                 };
 266         };
 267
 268         /*
 269          * U715
 270          *
 271          * Exposed signals:
 272          *     IO0 - WE1_CLK
 273          *     IO1 - WE1_CMD
 274          */
 275         gpio7: pca9554@22 {
 276                 compatible = "nxp,pca9554";
 277                 reg = <0x22>;
 278                 gpio-controller;
 279                 #gpio-cells = <2>;
 280
 281         };
 282 };
 283
 284 &i2c1 {
 285         at24mac602@00 {
 286                 compatible = "atmel,24c02";
 287                 reg = <0x50>;
 288                 read-only;
 289         };
 290 };
 291
 292 &i2c2 {
 293         tca9548@70 {
 294                 compatible = "nxp,pca9548";
 295                 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
 296                 pinctrl-names = "default";
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299                 reg = <0x70>;
 300                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 301
 302                 i2c@0 {
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         reg = <0>;
 306                 };
 307
 308                 i2c@1 {
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                         reg = <1>;
 312
 313                         sfp2: at24c04@50 {
 314                                 compatible = "atmel,24c02";
 315                                 reg = <0x50>;
 316                         };
 317                 };
 318
 319                 i2c@2 {
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         reg = <2>;
 323
 324                         sfp3: at24c04@50 {
 325                                 compatible = "atmel,24c02";
 326                                 reg = <0x50>;
 327                         };
 328                 };
 329
 330                 i2c@3 {
 331                         #address-cells = <1>;
 332                         #size-cells = <0>;
 333                         reg = <3>;
 334                 };
 335         };
 336 };
 337
 338 &uart3 {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_uart3>;
 341         status = "okay";
 342 };
 343
 344 &gpio0 {
 345         eth0_intrp {
 346                 gpio-hog;
 347                 gpios = <23 GPIO_ACTIVE_HIGH>;
 348                 input;
 349                 line-name = "sx1503-irq";
 350         };
 351 };
 352
 353 &gpio3 {
 354         eth0_intrp {
 355                 gpio-hog;
 356                 gpios = <2 GPIO_ACTIVE_HIGH>;
 357                 input;
 358                 line-name = "eth0-intrp";
 359         };
 360 };
 361
 362 &fec0 {
 363         mdio {
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 status = "okay";
 367
 368                 ethernet-phy@0 {
 369                         compatible = "ethernet-phy-ieee802.3-c22";
 370
 371                         pinctrl-names = "default";
 372                         pinctrl-0 = <&pinctrl_fec0_phy_int>;
 373
 374                         interrupt-parent = <&gpio3>;
 375                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 376                         reg = <0>;
 377                 };
 378         };
 379 };
 380
 381 &iomuxc {
 382         pinctr_atzb_rf_233: pinctrl-atzb-rf-233 {
 383                 fsl,pins = <
 384                         VF610_PAD_PTB2__GPIO_24         0x31c2
 385                         VF610_PAD_PTE27__GPIO_132       0x33e2
 386                 >;
 387         };
 388
 389
 390         pinctrl_sx1503_20: pinctrl-sx1503-20 {
 391                 fsl,pins = <
 392                         VF610_PAD_PTB1__GPIO_23         0x219d
 393                 >;
 394         };
 395
 396         pinctrl_uart3: uart3grp {
 397                 fsl,pins = <
 398                         VF610_PAD_PTA20__UART3_TX       0x21a2
 399                         VF610_PAD_PTA21__UART3_RX       0x21a1
 400                 >;
 401         };
 402
 403         pinctrl_mdio_mux: pinctrl-mdio-mux {
 404                 fsl,pins = <
 405                         VF610_PAD_PTA18__GPIO_8         0x31c2
 406                         VF610_PAD_PTA19__GPIO_9         0x31c2
 407                         VF610_PAD_PTB3__GPIO_25         0x31c2
 408                 >;
 409         };
 410
 411         pinctrl_fec0_phy_int: pinctrl-fec0-phy-int {
 412                 fsl,pins = <
 413                         VF610_PAD_PTB28__GPIO_98        0x219d
 414                 >;
 415         };
 416 };