arch/arm/boot/dts/zx296702.dtsi

   1
   2 #include "skeleton.dtsi"
   3 #include <dt-bindings/clock/zx296702-clock.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 / {
   7         cpus {
   8                 #address-cells = <1>;
   9                 #size-cells = <0>;
  10                 enable-method = "zte,zx296702-smp";
  11
  12                 cpu@0 {
  13                         compatible = "arm,cortex-a9";
  14                         device_type = "cpu";
  15                         next-level-cache = <&l2cc>;
  16                         reg = <0>;
  17                 };
  18
  19                 cpu@1 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         next-level-cache = <&l2cc>;
  23                         reg = <1>;
  24                 };
  25         };
  26
  27
  28         soc {
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31                 compatible = "simple-bus";
  32                 interrupt-parent = <&intc>;
  33                 ranges;
  34
  35                 matrix: bus-matrix@400000 {
  36                         compatible = "zte,zx-bus-matrix";
  37                         reg = <0x00400000 0x1000>;
  38                 };
  39
  40                 intc: interrupt-controller@00801000 {
  41                         compatible = "arm,cortex-a9-gic";
  42                         #interrupt-cells = <3>;
  43                         #address-cells = <1>;
  44                         #size-cells = <1>;
  45                         interrupt-controller;
  46                         reg = <0x00801000 0x1000>,
  47                               <0x00800100 0x100>;
  48                 };
  49
  50                 global_timer: timer@008000200 {
  51                         compatible = "arm,cortex-a9-global-timer";
  52                         reg = <0x00800200 0x20>;
  53                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  54                         interrupt-parent = <&intc>;
  55                         clocks = <&topclk ZX296702_A9_PERIPHCLK>;
  56                 };
  57
  58                 l2cc: l2-cache-controller@0x00c00000 {
  59                         compatible = "arm,pl310-cache";
  60                         reg = <0x00c00000 0x1000>;
  61                         cache-unified;
  62                         cache-level = <2>;
  63                         arm,data-latency = <1 1 1>;
  64                         arm,tag-latency = <1 1 1>;
  65                         arm,double-linefill = <1>;
  66                         arm,double-linefill-incr = <0>;
  67                 };
  68
  69                 pcu: pcu@0xa0008000 {
  70                         compatible = "zte,zx296702-pcu";
  71                         reg = <0xa0008000 0x1000>;
  72                 };
  73
  74                 topclk: topclk@0x09800000 {
  75                         compatible = "zte,zx296702-topcrm-clk";
  76                         reg = <0x09800000 0x1000>;
  77                         #clock-cells = <1>;
  78                 };
  79
  80                 lsp1clk: lsp1clk@0x09400000 {
  81                         compatible = "zte,zx296702-lsp1crpm-clk";
  82                         reg = <0x09400000 0x1000>;
  83                         #clock-cells = <1>;
  84                 };
  85
  86                 lsp0clk: lsp0clk@0x0b000000 {
  87                         compatible = "zte,zx296702-lsp0crpm-clk";
  88                         reg = <0x0b000000 0x1000>;
  89                         #clock-cells = <1>;
  90                 };
  91
  92                 uart0: serial@0x09405000 {
  93                         compatible = "zte,zx296702-uart";
  94                         reg = <0x09405000 0x1000>;
  95                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  96                         clocks = <&lsp1clk ZX296702_UART0_WCLK>;
  97                         status = "disabled";
  98                 };
  99
 100                 uart1: serial@0x09406000 {
 101                         compatible = "zte,zx296702-uart";
 102                         reg = <0x09406000 0x1000>;
 103                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 104                         clocks = <&lsp1clk ZX296702_UART1_WCLK>;
 105                         status = "disabled";
 106                 };
 107
 108                 mmc0: mmc@0x09408000 {
 109                         compatible = "snps,dw-mshc";
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112                         reg = <0x09408000 0x1000>;
 113                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 114                         fifo-depth = <32>;
 115                         clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>,
 116                                  <&lsp1clk ZX296702_SDMMC0_WCLK>;
 117                         clock-names = "biu", "ciu";
 118                         status = "disabled";
 119                 };
 120
 121                 mmc1: mmc@0x0b003000 {
 122                         compatible = "snps,dw-mshc";
 123                         #address-cells = <1>;
 124                         #size-cells = <0>;
 125                         reg = <0x0b003000 0x1000>;
 126                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 127                         fifo-depth = <32>;
 128                         clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>,
 129                                  <&lsp0clk ZX296702_SDMMC1_WCLK>;
 130                         clock-names = "biu", "ciu";
 131                         status = "disabled";
 132                 };
 133
 134                 sysctrl: sysctrl@0xa0007000 {
 135                         compatible = "zte,sysctrl", "syscon";
 136                         reg = <0xa0007000 0x1000>;
 137                 };
 138         };
 139 };