2 * Copyright (C) 2011 - 2014 Xilinx
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 /include/ "skeleton.dtsi"
16 compatible = "xlnx,zynq-7000";
23 compatible = "arm,cortex-a9";
27 clock-latency = <1000>;
28 cpu0-supply = <®ulator_vccpint>;
37 compatible = "arm,cortex-a9";
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 5 4>, <0 6 4>;
47 interrupt-parent = <&intc>;
48 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
51 regulator_vccpint: fixedregulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "VCCPINT";
54 regulator-min-microvolt = <1000000>;
55 regulator-max-microvolt = <1000000>;
61 compatible = "simple-bus";
64 interrupt-parent = <&intc>;
68 compatible = "xlnx,zynq-xadc-1.00.a";
69 reg = <0xf8007100 0x20>;
71 interrupt-parent = <&intc>;
76 compatible = "xlnx,zynq-can-1.0";
78 clocks = <&clkc 19>, <&clkc 36>;
79 clock-names = "can_clk", "pclk";
80 reg = <0xe0008000 0x1000>;
81 interrupts = <0 28 4>;
82 interrupt-parent = <&intc>;
83 tx-fifo-depth = <0x40>;
84 rx-fifo-depth = <0x40>;
88 compatible = "xlnx,zynq-can-1.0";
90 clocks = <&clkc 20>, <&clkc 37>;
91 clock-names = "can_clk", "pclk";
92 reg = <0xe0009000 0x1000>;
93 interrupts = <0 51 4>;
94 interrupt-parent = <&intc>;
95 tx-fifo-depth = <0x40>;
96 rx-fifo-depth = <0x40>;
99 gpio0: gpio@e000a000 {
100 compatible = "xlnx,zynq-gpio-1.0";
104 interrupt-parent = <&intc>;
105 interrupts = <0 20 4>;
106 reg = <0xe000a000 0x1000>;
110 compatible = "cdns,i2c-r1p10";
113 interrupt-parent = <&intc>;
114 interrupts = <0 25 4>;
115 reg = <0xe0004000 0x1000>;
116 #address-cells = <1>;
121 compatible = "cdns,i2c-r1p10";
124 interrupt-parent = <&intc>;
125 interrupts = <0 48 4>;
126 reg = <0xe0005000 0x1000>;
127 #address-cells = <1>;
131 intc: interrupt-controller@f8f01000 {
132 compatible = "arm,cortex-a9-gic";
133 #interrupt-cells = <3>;
134 interrupt-controller;
135 reg = <0xF8F01000 0x1000>,
139 L2: cache-controller@f8f02000 {
140 compatible = "arm,pl310-cache";
141 reg = <0xF8F02000 0x1000>;
142 arm,data-latency = <3 2 2>;
143 arm,tag-latency = <2 2 2>;
148 memory-controller@f8006000 {
149 compatible = "xlnx,zynq-ddrc-a05";
150 reg = <0xf8006000 0x1000>;
153 uart0: serial@e0000000 {
154 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
156 clocks = <&clkc 23>, <&clkc 40>;
157 clock-names = "uart_clk", "pclk";
158 reg = <0xE0000000 0x1000>;
159 interrupts = <0 27 4>;
162 uart1: serial@e0001000 {
163 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
165 clocks = <&clkc 24>, <&clkc 41>;
166 clock-names = "uart_clk", "pclk";
167 reg = <0xE0001000 0x1000>;
168 interrupts = <0 50 4>;
172 compatible = "xlnx,zynq-spi-r1p6";
173 reg = <0xe0006000 0x1000>;
175 interrupt-parent = <&intc>;
176 interrupts = <0 26 4>;
177 clocks = <&clkc 25>, <&clkc 34>;
178 clock-names = "ref_clk", "pclk";
179 #address-cells = <1>;
184 compatible = "xlnx,zynq-spi-r1p6";
185 reg = <0xe0007000 0x1000>;
187 interrupt-parent = <&intc>;
188 interrupts = <0 49 4>;
189 clocks = <&clkc 26>, <&clkc 35>;
190 clock-names = "ref_clk", "pclk";
191 #address-cells = <1>;
195 gem0: ethernet@e000b000 {
196 compatible = "cdns,gem";
197 reg = <0xe000b000 0x1000>;
199 interrupts = <0 22 4>;
200 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
201 clock-names = "pclk", "hclk", "tx_clk";
202 #address-cells = <1>;
206 gem1: ethernet@e000c000 {
207 compatible = "cdns,gem";
208 reg = <0xe000c000 0x1000>;
210 interrupts = <0 45 4>;
211 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
212 clock-names = "pclk", "hclk", "tx_clk";
213 #address-cells = <1>;
217 sdhci0: sdhci@e0100000 {
218 compatible = "arasan,sdhci-8.9a";
220 clock-names = "clk_xin", "clk_ahb";
221 clocks = <&clkc 21>, <&clkc 32>;
222 interrupt-parent = <&intc>;
223 interrupts = <0 24 4>;
224 reg = <0xe0100000 0x1000>;
227 sdhci1: sdhci@e0101000 {
228 compatible = "arasan,sdhci-8.9a";
230 clock-names = "clk_xin", "clk_ahb";
231 clocks = <&clkc 22>, <&clkc 33>;
232 interrupt-parent = <&intc>;
233 interrupts = <0 47 4>;
234 reg = <0xe0101000 0x1000>;
237 slcr: slcr@f8000000 {
238 #address-cells = <1>;
240 compatible = "xlnx,zynq-slcr", "syscon";
241 reg = <0xF8000000 0x1000>;
245 compatible = "xlnx,ps7-clkc";
246 ps-clk-frequency = <33333333>;
248 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
249 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
250 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
251 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
252 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
253 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
254 "gem1_aper", "sdio0_aper", "sdio1_aper",
255 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
256 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
257 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
258 "dbg_trc", "dbg_apb";
263 dmac_s: dmac@f8003000 {
264 compatible = "arm,pl330", "arm,primecell";
265 reg = <0xf8003000 0x1000>;
266 interrupt-parent = <&intc>;
267 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
268 "dma4", "dma5", "dma6", "dma7";
269 interrupts = <0 13 4>,
278 clock-names = "apb_pclk";
281 devcfg: devcfg@f8007000 {
282 compatible = "xlnx,zynq-devcfg-1.0";
283 reg = <0xf8007000 0x100>;
286 global_timer: timer@f8f00200 {
287 compatible = "arm,cortex-a9-global-timer";
288 reg = <0xf8f00200 0x20>;
289 interrupts = <1 11 0x301>;
290 interrupt-parent = <&intc>;
294 ttc0: timer@f8001000 {
295 interrupt-parent = <&intc>;
296 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
297 compatible = "cdns,ttc";
299 reg = <0xF8001000 0x1000>;
302 ttc1: timer@f8002000 {
303 interrupt-parent = <&intc>;
304 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
305 compatible = "cdns,ttc";
307 reg = <0xF8002000 0x1000>;
310 scutimer: timer@f8f00600 {
311 interrupt-parent = <&intc>;
312 interrupts = <1 13 0x301>;
313 compatible = "arm,cortex-a9-twd-timer";
314 reg = <0xf8f00600 0x20>;