arch/arm/include/asm/io.h

   1 /*
   2  *  arch/arm/include/asm/io.h
   3  *
   4  *  Copyright (C) 1996-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Modifications:
  11  *  16-Sep-1996 RMK     Inlined the inx/outx functions & optimised for both
  12  *                      constant addresses and variable addresses.
  13  *  04-Dec-1997 RMK     Moved a lot of this stuff to the new architecture
  14  *                      specific IO header files.
  15  *  27-Mar-1999 PJB     Second parameter of memcpy_toio is const..
  16  *  04-Apr-1999 PJB     Added check_signature.
  17  *  12-Dec-1999 RMK     More cleanups
  18  *  18-Jun-2000 RMK     Removed virt_to_* and friends definitions
  19  *  05-Oct-2004 BJD     Moved memory string functions to use void __iomem
  20  */
  21 #ifndef __ASM_ARM_IO_H
  22 #define __ASM_ARM_IO_H
  23
  24 #ifdef __KERNEL__
  25
  26 #include <linux/types.h>
  27 #include <asm/byteorder.h>
  28 #include <asm/memory.h>
  29 #include <asm-generic/pci_iomap.h>
  30
  31 /*
  32  * ISA I/O bus memory addresses are 1:1 with the physical address.
  33  */
  34 #define isa_virt_to_bus virt_to_phys
  35 #define isa_page_to_bus page_to_phys
  36 #define isa_bus_to_virt phys_to_virt
  37
  38 /*
  39  * Generic IO read/write.  These perform native-endian accesses.  Note
  40  * that some architectures will want to re-define __raw_{read,write}w.
  41  */
  42 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
  43 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
  44 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
  45
  46 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
  47 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
  48 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
  49
  50 #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v))
  51 #define __raw_writew(v,a)       (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
  52 #define __raw_writel(v,a)       (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v))
  53
  54 #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
  55 #define __raw_readw(a)          (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
  56 #define __raw_readl(a)          (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
  57
  58 /*
  59  * Architecture ioremap implementation.
  60  */
  61 #define MT_DEVICE               0
  62 #define MT_DEVICE_NONSHARED     1
  63 #define MT_DEVICE_CACHED        2
  64 #define MT_DEVICE_WC            3
  65 /*
  66  * types 4 onwards can be found in asm/mach/map.h and are undefined
  67  * for ioremap
  68  */
  69
  70 /*
  71  * __arm_ioremap takes CPU physical address.
  72  * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
  73  * The _caller variety takes a __builtin_return_address(0) value for
  74  * /proc/vmalloc to use - and should only be used in non-inline functions.
  75  */
  76 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
  77         size_t, unsigned int, void *);
  78 extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
  79         void *);
  80
  81 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
  82 extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
  83 extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
  84 extern void __iounmap(volatile void __iomem *addr);
  85
  86 /*
  87  * Bad read/write accesses...
  88  */
  89 extern void __readwrite_bug(const char *fn);
  90
  91 /*
  92  * A typesafe __io() helper
  93  */
  94 static inline void __iomem *__typesafe_io(unsigned long addr)
  95 {
  96         return (void __iomem *)addr;
  97 }
  98
  99 /* IO barriers */
 100 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 101 #include <asm/barrier.h>
 102 #define __iormb()               rmb()
 103 #define __iowmb()               wmb()
 104 #else
 105 #define __iormb()               do { } while (0)
 106 #define __iowmb()               do { } while (0)
 107 #endif
 108
 109 /*
 110  * Now, pick up the machine-defined IO definitions
 111  */
 112 #include <mach/io.h>
 113
 114 /*
 115  * This is the limit of PC card/PCI/ISA IO space, which is by default
 116  * 64K if we have PC card, PCI or ISA support.  Otherwise, default to
 117  * zero to prevent ISA/PCI drivers claiming IO space (and potentially
 118  * oopsing.)
 119  *
 120  * Only set this larger if you really need inb() et.al. to operate over
 121  * a larger address space.  Note that SOC_COMMON ioremaps each sockets
 122  * IO space area, and so inb() et.al. must be defined to operate as per
 123  * readb() et.al. on such platforms.
 124  */
 125 #ifndef IO_SPACE_LIMIT
 126 #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
 127 #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
 128 #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
 129 #define IO_SPACE_LIMIT ((resource_size_t)0xffff)
 130 #else
 131 #define IO_SPACE_LIMIT ((resource_size_t)0)
 132 #endif
 133 #endif
 134
 135 /*
 136  *  IO port access primitives
 137  *  -------------------------
 138  *
 139  * The ARM doesn't have special IO access instructions; all IO is memory
 140  * mapped.  Note that these are defined to perform little endian accesses
 141  * only.  Their primary purpose is to access PCI and ISA peripherals.
 142  *
 143  * Note that for a big endian machine, this implies that the following
 144  * big endian mode connectivity is in place, as described by numerous
 145  * ARM documents:
 146  *
 147  *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
 148  *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
 149  *
 150  * The machine specific io.h include defines __io to translate an "IO"
 151  * address to a memory address.
 152  *
 153  * Note that we prevent GCC re-ordering or caching values in expressions
 154  * by introducing sequence points into the in*() definitions.  Note that
 155  * __raw_* do not guarantee this behaviour.
 156  *
 157  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
 158  */
 159 #ifdef __io
 160 #define outb(v,p)       ({ __iowmb(); __raw_writeb(v,__io(p)); })
 161 #define outw(v,p)       ({ __iowmb(); __raw_writew((__force __u16) \
 162                                         cpu_to_le16(v),__io(p)); })
 163 #define outl(v,p)       ({ __iowmb(); __raw_writel((__force __u32) \
 164                                         cpu_to_le32(v),__io(p)); })
 165
 166 #define inb(p)  ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
 167 #define inw(p)  ({ __u16 __v = le16_to_cpu((__force __le16) \
 168                         __raw_readw(__io(p))); __iormb(); __v; })
 169 #define inl(p)  ({ __u32 __v = le32_to_cpu((__force __le32) \
 170                         __raw_readl(__io(p))); __iormb(); __v; })
 171
 172 #define outsb(p,d,l)            __raw_writesb(__io(p),d,l)
 173 #define outsw(p,d,l)            __raw_writesw(__io(p),d,l)
 174 #define outsl(p,d,l)            __raw_writesl(__io(p),d,l)
 175
 176 #define insb(p,d,l)             __raw_readsb(__io(p),d,l)
 177 #define insw(p,d,l)             __raw_readsw(__io(p),d,l)
 178 #define insl(p,d,l)             __raw_readsl(__io(p),d,l)
 179 #endif
 180
 181 #define outb_p(val,port)        outb((val),(port))
 182 #define outw_p(val,port)        outw((val),(port))
 183 #define outl_p(val,port)        outl((val),(port))
 184 #define inb_p(port)             inb((port))
 185 #define inw_p(port)             inw((port))
 186 #define inl_p(port)             inl((port))
 187
 188 #define outsb_p(port,from,len)  outsb(port,from,len)
 189 #define outsw_p(port,from,len)  outsw(port,from,len)
 190 #define outsl_p(port,from,len)  outsl(port,from,len)
 191 #define insb_p(port,to,len)     insb(port,to,len)
 192 #define insw_p(port,to,len)     insw(port,to,len)
 193 #define insl_p(port,to,len)     insl(port,to,len)
 194
 195 /*
 196  * String version of IO memory access ops:
 197  */
 198 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
 199 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
 200 extern void _memset_io(volatile void __iomem *, int, size_t);
 201
 202 #define mmiowb()
 203
 204 /*
 205  *  Memory access primitives
 206  *  ------------------------
 207  *
 208  * These perform PCI memory accesses via an ioremap region.  They don't
 209  * take an address as such, but a cookie.
 210  *
 211  * Again, this are defined to perform little endian accesses.  See the
 212  * IO port primitives for more information.
 213  */
 214 #ifdef __mem_pci
 215 #define readb_relaxed(c) ({ u8  __r = __raw_readb(__mem_pci(c)); __r; })
 216 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
 217                                         __raw_readw(__mem_pci(c))); __r; })
 218 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
 219                                         __raw_readl(__mem_pci(c))); __r; })
 220
 221 #define writeb_relaxed(v,c)     ((void)__raw_writeb(v,__mem_pci(c)))
 222 #define writew_relaxed(v,c)     ((void)__raw_writew((__force u16) \
 223                                         cpu_to_le16(v),__mem_pci(c)))
 224 #define writel_relaxed(v,c)     ((void)__raw_writel((__force u32) \
 225                                         cpu_to_le32(v),__mem_pci(c)))
 226
 227 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 228 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 229 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 230
 231 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed(v,c); })
 232 #define writew(v,c)             ({ __iowmb(); writew_relaxed(v,c); })
 233 #define writel(v,c)             ({ __iowmb(); writel_relaxed(v,c); })
 234
 235 #define readsb(p,d,l)           __raw_readsb(__mem_pci(p),d,l)
 236 #define readsw(p,d,l)           __raw_readsw(__mem_pci(p),d,l)
 237 #define readsl(p,d,l)           __raw_readsl(__mem_pci(p),d,l)
 238
 239 #define writesb(p,d,l)          __raw_writesb(__mem_pci(p),d,l)
 240 #define writesw(p,d,l)          __raw_writesw(__mem_pci(p),d,l)
 241 #define writesl(p,d,l)          __raw_writesl(__mem_pci(p),d,l)
 242
 243 #define memset_io(c,v,l)        _memset_io(__mem_pci(c),(v),(l))
 244 #define memcpy_fromio(a,c,l)    _memcpy_fromio((a),__mem_pci(c),(l))
 245 #define memcpy_toio(c,a,l)      _memcpy_toio(__mem_pci(c),(a),(l))
 246
 247 #elif !defined(readb)
 248
 249 #define readb(c)                        (__readwrite_bug("readb"),0)
 250 #define readw(c)                        (__readwrite_bug("readw"),0)
 251 #define readl(c)                        (__readwrite_bug("readl"),0)
 252 #define writeb(v,c)                     __readwrite_bug("writeb")
 253 #define writew(v,c)                     __readwrite_bug("writew")
 254 #define writel(v,c)                     __readwrite_bug("writel")
 255
 256 #define check_signature(io,sig,len)     (0)
 257
 258 #endif  /* __mem_pci */
 259
 260 /*
 261  * ioremap and friends.
 262  *
 263  * ioremap takes a PCI memory address, as specified in
 264  * Documentation/io-mapping.txt.
 265  *
 266  */
 267 #ifndef __arch_ioremap
 268 #define __arch_ioremap                  __arm_ioremap
 269 #define __arch_iounmap                  __iounmap
 270 #endif
 271
 272 #define ioremap(cookie,size)            __arch_ioremap((cookie), (size), MT_DEVICE)
 273 #define ioremap_nocache(cookie,size)    __arch_ioremap((cookie), (size), MT_DEVICE)
 274 #define ioremap_cached(cookie,size)     __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
 275 #define ioremap_wc(cookie,size)         __arch_ioremap((cookie), (size), MT_DEVICE_WC)
 276 #define iounmap                         __arch_iounmap
 277
 278 /*
 279  * io{read,write}{8,16,32} macros
 280  */
 281 #ifndef ioread8
 282 #define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
 283 #define ioread16(p)     ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
 284 #define ioread32(p)     ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
 285
 286 #define ioread16be(p)   ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
 287 #define ioread32be(p)   ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
 288
 289 #define iowrite8(v,p)   ({ __iowmb(); (void)__raw_writeb(v, p); })
 290 #define iowrite16(v,p)  ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); })
 291 #define iowrite32(v,p)  ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); })
 292
 293 #define iowrite16be(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_be16(v), p); })
 294 #define iowrite32be(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_be32(v), p); })
 295
 296 #define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
 297 #define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
 298 #define ioread32_rep(p,d,c)     __raw_readsl(p,d,c)
 299
 300 #define iowrite8_rep(p,s,c)     __raw_writesb(p,s,c)
 301 #define iowrite16_rep(p,s,c)    __raw_writesw(p,s,c)
 302 #define iowrite32_rep(p,s,c)    __raw_writesl(p,s,c)
 303
 304 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 305 extern void ioport_unmap(void __iomem *addr);
 306 #endif
 307
 308 struct pci_dev;
 309
 310 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 311
 312 /*
 313  * can the hardware map this into one segment or not, given no other
 314  * constraints.
 315  */
 316 #define BIOVEC_MERGEABLE(vec1, vec2)    \
 317         ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
 318
 319 #ifdef CONFIG_MMU
 320 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 321 extern int valid_phys_addr_range(unsigned long addr, size_t size);
 322 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 323 extern int devmem_is_allowed(unsigned long pfn);
 324 #endif
 325
 326 /*
 327  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 328  * access
 329  */
 330 #define xlate_dev_mem_ptr(p)    __va(p)
 331
 332 /*
 333  * Convert a virtual cached pointer to an uncached pointer
 334  */
 335 #define xlate_dev_kmem_ptr(p)   p
 336
 337 /*
 338  * Register ISA memory and port locations for glibc iopl/inb/outb
 339  * emulation.
 340  */
 341 extern void register_isa_ports(unsigned int mmio, unsigned int io,
 342                                unsigned int io_shift);
 343
 344 #endif  /* __KERNEL__ */
 345 #endif  /* __ASM_ARM_IO_H */