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1 /*
2 * arch/arm/include/asm/io.h
3 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Modifications:
11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
12 * constant addresses and variable addresses.
13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
14 * specific IO header files.
15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
16 * 04-Apr-1999 PJB Added check_signature.
17 * 12-Dec-1999 RMK More cleanups
18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
20 */
21 #ifndef __ASM_ARM_IO_H
22 #define __ASM_ARM_IO_H
23
24 #ifdef __KERNEL__
25
26 #include <linux/types.h>
27 #include <linux/blk_types.h>
28 #include <asm/byteorder.h>
29 #include <asm/memory.h>
30 #include <asm-generic/pci_iomap.h>
31 #include <xen/xen.h>
32
33 /*
34 * ISA I/O bus memory addresses are 1:1 with the physical address.
35 */
36 #define isa_virt_to_bus virt_to_phys
37 #define isa_page_to_bus page_to_phys
38 #define isa_bus_to_virt phys_to_virt
39
40 /*
41 * Generic IO read/write. These perform native-endian accesses. Note
42 * that some architectures will want to re-define __raw_{read,write}w.
43 */
44 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
45 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
46 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
47
48 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
49 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
50 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
51
52 #if __LINUX_ARM_ARCH__ < 6
53 /*
54 * Half-word accesses are problematic with RiscPC due to limitations of
55 * the bus. Rather than special-case the machine, just let the compiler
56 * generate the access for CPUs prior to ARMv6.
57 */
58 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
59 #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
60 #else
61 /*
62 * When running under a hypervisor, we want to avoid I/O accesses with
63 * writeback addressing modes as these incur a significant performance
64 * overhead (the address generation must be emulated in software).
65 */
66 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
67 {
68 asm volatile("strh %1, %0"
69 : "+Q" (*(volatile u16 __force *)addr)
70 : "r" (val));
71 }
72
73 static inline u16 __raw_readw(const volatile void __iomem *addr)
74 {
75 u16 val;
76 asm volatile("ldrh %1, %0"
77 : "+Q" (*(volatile u16 __force *)addr),
78 "=r" (val));
79 return val;
80 }
81 #endif
82
83 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
84 {
85 asm volatile("strb %1, %0"
86 : "+Qo" (*(volatile u8 __force *)addr)
87 : "r" (val));
88 }
89
90 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
91 {
92 asm volatile("str %1, %0"
93 : "+Qo" (*(volatile u32 __force *)addr)
94 : "r" (val));
95 }
96
97 static inline u8 __raw_readb(const volatile void __iomem *addr)
98 {
99 u8 val;
100 asm volatile("ldrb %1, %0"
101 : "+Qo" (*(volatile u8 __force *)addr),
102 "=r" (val));
103 return val;
104 }
105
106 static inline u32 __raw_readl(const volatile void __iomem *addr)
107 {
108 u32 val;
109 asm volatile("ldr %1, %0"
110 : "+Qo" (*(volatile u32 __force *)addr),
111 "=r" (val));
112 return val;
113 }
114
115 /*
116 * Architecture ioremap implementation.
117 */
118 #define MT_DEVICE 0
119 #define MT_DEVICE_NONSHARED 1
120 #define MT_DEVICE_CACHED 2
121 #define MT_DEVICE_WC 3
122 /*
123 * types 4 onwards can be found in asm/mach/map.h and are undefined
124 * for ioremap
125 */
126
127 /*
128 * __arm_ioremap takes CPU physical address.
129 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
130 * The _caller variety takes a __builtin_return_address(0) value for
131 * /proc/vmalloc to use - and should only be used in non-inline functions.
132 */
133 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
134 size_t, unsigned int, void *);
135 extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
136 void *);
137
138 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
139 extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int);
140 extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
141 extern void __iounmap(volatile void __iomem *addr);
142 extern void __arm_iounmap(volatile void __iomem *addr);
143
144 extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
145 unsigned int, void *);
146 extern void (*arch_iounmap)(volatile void __iomem *);
147
148 /*
149 * Bad read/write accesses...
150 */
151 extern void __readwrite_bug(const char *fn);
152
153 /*
154 * A typesafe __io() helper
155 */
156 static inline void __iomem *__typesafe_io(unsigned long addr)
157 {
158 return (void __iomem *)addr;
159 }
160
161 #define IOMEM(x) ((void __force __iomem *)(x))
162
163 /* IO barriers */
164 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
165 #include <asm/barrier.h>
166 #define __iormb() rmb()
167 #define __iowmb() wmb()
168 #else
169 #define __iormb() do { } while (0)
170 #define __iowmb() do { } while (0)
171 #endif
172
173 /* PCI fixed i/o mapping */
174 #define PCI_IO_VIRT_BASE 0xfee00000
175
176 extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
177
178 /*
179 * Now, pick up the machine-defined IO definitions
180 */
181 #ifdef CONFIG_NEED_MACH_IO_H
182 #include <mach/io.h>
183 #elif defined(CONFIG_PCI)
184 #define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
185 #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
186 #else
187 #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
188 #endif
189
190 /*
191 * This is the limit of PC card/PCI/ISA IO space, which is by default
192 * 64K if we have PC card, PCI or ISA support. Otherwise, default to
193 * zero to prevent ISA/PCI drivers claiming IO space (and potentially
194 * oopsing.)
195 *
196 * Only set this larger if you really need inb() et.al. to operate over
197 * a larger address space. Note that SOC_COMMON ioremaps each sockets
198 * IO space area, and so inb() et.al. must be defined to operate as per
199 * readb() et.al. on such platforms.
200 */
201 #ifndef IO_SPACE_LIMIT
202 #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
203 #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
204 #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
205 #define IO_SPACE_LIMIT ((resource_size_t)0xffff)
206 #else
207 #define IO_SPACE_LIMIT ((resource_size_t)0)
208 #endif
209 #endif
210
211 /*
212 * IO port access primitives
213 * -------------------------
214 *
215 * The ARM doesn't have special IO access instructions; all IO is memory
216 * mapped. Note that these are defined to perform little endian accesses
217 * only. Their primary purpose is to access PCI and ISA peripherals.
218 *
219 * Note that for a big endian machine, this implies that the following
220 * big endian mode connectivity is in place, as described by numerous
221 * ARM documents:
222 *
223 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
224 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
225 *
226 * The machine specific io.h include defines __io to translate an "IO"
227 * address to a memory address.
228 *
229 * Note that we prevent GCC re-ordering or caching values in expressions
230 * by introducing sequence points into the in*() definitions. Note that
231 * __raw_* do not guarantee this behaviour.
232 *
233 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
234 */
235 #ifdef __io
236 #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
237 #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
238 cpu_to_le16(v),__io(p)); })
239 #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
240 cpu_to_le32(v),__io(p)); })
241
242 #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
243 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
244 __raw_readw(__io(p))); __iormb(); __v; })
245 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
246 __raw_readl(__io(p))); __iormb(); __v; })
247
248 #define outsb(p,d,l) __raw_writesb(__io(p),d,l)
249 #define outsw(p,d,l) __raw_writesw(__io(p),d,l)
250 #define outsl(p,d,l) __raw_writesl(__io(p),d,l)
251
252 #define insb(p,d,l) __raw_readsb(__io(p),d,l)
253 #define insw(p,d,l) __raw_readsw(__io(p),d,l)
254 #define insl(p,d,l) __raw_readsl(__io(p),d,l)
255 #endif
256
257 #define outb_p(val,port) outb((val),(port))
258 #define outw_p(val,port) outw((val),(port))
259 #define outl_p(val,port) outl((val),(port))
260 #define inb_p(port) inb((port))
261 #define inw_p(port) inw((port))
262 #define inl_p(port) inl((port))
263
264 #define outsb_p(port,from,len) outsb(port,from,len)
265 #define outsw_p(port,from,len) outsw(port,from,len)
266 #define outsl_p(port,from,len) outsl(port,from,len)
267 #define insb_p(port,to,len) insb(port,to,len)
268 #define insw_p(port,to,len) insw(port,to,len)
269 #define insl_p(port,to,len) insl(port,to,len)
270
271 /*
272 * String version of IO memory access ops:
273 */
274 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
275 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
276 extern void _memset_io(volatile void __iomem *, int, size_t);
277
278 #define mmiowb()
279
280 /*
281 * Memory access primitives
282 * ------------------------
283 *
284 * These perform PCI memory accesses via an ioremap region. They don't
285 * take an address as such, but a cookie.
286 *
287 * Again, this are defined to perform little endian accesses. See the
288 * IO port primitives for more information.
289 */
290 #ifndef readl
291 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
292 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
293 __raw_readw(c)); __r; })
294 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
295 __raw_readl(c)); __r; })
296
297 #define writeb_relaxed(v,c) __raw_writeb(v,c)
298 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
299 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
300
301 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
302 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
303 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
304
305 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
306 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
307 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
308
309 #define readsb(p,d,l) __raw_readsb(p,d,l)
310 #define readsw(p,d,l) __raw_readsw(p,d,l)
311 #define readsl(p,d,l) __raw_readsl(p,d,l)
312
313 #define writesb(p,d,l) __raw_writesb(p,d,l)
314 #define writesw(p,d,l) __raw_writesw(p,d,l)
315 #define writesl(p,d,l) __raw_writesl(p,d,l)
316
317 #define memset_io(c,v,l) _memset_io(c,(v),(l))
318 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
319 #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
320
321 #endif /* readl */
322
323 /*
324 * ioremap and friends.
325 *
326 * ioremap takes a PCI memory address, as specified in
327 * Documentation/io-mapping.txt.
328 *
329 */
330 #define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
331 #define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
332 #define ioremap_cached(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
333 #define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC)
334 #define iounmap __arm_iounmap
335
336 /*
337 * io{read,write}{8,16,32} macros
338 */
339 #ifndef ioread8
340 #define ioread8(p) ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
341 #define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
342 #define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
343
344 #define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
345 #define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
346
347 #define iowrite8(v,p) ({ __iowmb(); __raw_writeb(v, p); })
348 #define iowrite16(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_le16(v), p); })
349 #define iowrite32(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_le32(v), p); })
350
351 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
352 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
353
354 #define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
355 #define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
356 #define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
357
358 #define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
359 #define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
360 #define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
361
362 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
363 extern void ioport_unmap(void __iomem *addr);
364 #endif
365
366 struct pci_dev;
367
368 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
369
370 /*
371 * can the hardware map this into one segment or not, given no other
372 * constraints.
373 */
374 #define BIOVEC_MERGEABLE(vec1, vec2) \
375 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
376
377 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
378 const struct bio_vec *vec2);
379 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
380 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
381 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
382
383 #ifdef CONFIG_MMU
384 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
385 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
386 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
387 extern int devmem_is_allowed(unsigned long pfn);
388 #endif
389
390 /*
391 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
392 * access
393 */
394 #define xlate_dev_mem_ptr(p) __va(p)
395
396 /*
397 * Convert a virtual cached pointer to an uncached pointer
398 */
399 #define xlate_dev_kmem_ptr(p) p
400
401 /*
402 * Register ISA memory and port locations for glibc iopl/inb/outb
403 * emulation.
404 */
405 extern void register_isa_ports(unsigned int mmio, unsigned int io,
406 unsigned int io_shift);
407
408 #endif /* __KERNEL__ */
409 #endif /* __ASM_ARM_IO_H */