arch/arm/include/asm/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #if __LINUX_ARM_ARCH__ < 6
   5 #error SMP not supported on pre-ARMv6 CPUs
   6 #endif
   7
   8 #include <linux/prefetch.h>
   9 #include <asm/barrier.h>
  10 #include <asm/processor.h>
  11
  12 /*
  13  * sev and wfe are ARMv6K extensions.  Uniprocessor ARMv6 may not have the K
  14  * extensions, so when running on UP, we have to patch these instructions away.
  15  */
  16 #ifdef CONFIG_THUMB2_KERNEL
  17 /*
  18  * For Thumb-2, special care is needed to ensure that the conditional WFE
  19  * instruction really does assemble to exactly 4 bytes (as required by
  20  * the SMP_ON_UP fixup code).   By itself "wfene" might cause the
  21  * assembler to insert a extra (16-bit) IT instruction, depending on the
  22  * presence or absence of neighbouring conditional instructions.
  23  *
  24  * To avoid this unpredictableness, an approprite IT is inserted explicitly:
  25  * the assembler won't change IT instructions which are explicitly present
  26  * in the input.
  27  */
  28 #define WFE(cond)       __ALT_SMP_ASM(          \
  29         "it " cond "\n\t"                       \
  30         "wfe" cond ".n",                        \
  31                                                 \
  32         "nop.w"                                 \
  33 )
  34 #else
  35 #define WFE(cond)       __ALT_SMP_ASM("wfe" cond, "nop")
  36 #endif
  37
  38 #define SEV             __ALT_SMP_ASM(WASM(sev), WASM(nop))
  39
  40 static inline void dsb_sev(void)
  41 {
  42
  43         dsb(ishst);
  44         __asm__(SEV);
  45 }
  46
  47 /*
  48  * ARMv6 ticket-based spin-locking.
  49  *
  50  * A memory barrier is required after we get a lock, and before we
  51  * release it, because V6 CPUs are assumed to have weakly ordered
  52  * memory.
  53  */
  54
  55 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
  56
  57 static inline void arch_spin_lock(arch_spinlock_t *lock)
  58 {
  59         unsigned long tmp;
  60         u32 newval;
  61         arch_spinlock_t lockval;
  62
  63         prefetchw(&lock->slock);
  64         __asm__ __volatile__(
  65 "1:     ldrex   %0, [%3]\n"
  66 "       add     %1, %0, %4\n"
  67 "       strex   %2, %1, [%3]\n"
  68 "       teq     %2, #0\n"
  69 "       bne     1b"
  70         : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
  71         : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
  72         : "cc");
  73
  74         while (lockval.tickets.next != lockval.tickets.owner) {
  75                 wfe();
  76                 lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
  77         }
  78
  79         smp_mb();
  80 }
  81
  82 static inline int arch_spin_trylock(arch_spinlock_t *lock)
  83 {
  84         unsigned long contended, res;
  85         u32 slock;
  86
  87         prefetchw(&lock->slock);
  88         do {
  89                 __asm__ __volatile__(
  90                 "       ldrex   %0, [%3]\n"
  91                 "       mov     %2, #0\n"
  92                 "       subs    %1, %0, %0, ror #16\n"
  93                 "       addeq   %0, %0, %4\n"
  94                 "       strexeq %2, %0, [%3]"
  95                 : "=&r" (slock), "=&r" (contended), "=&r" (res)
  96                 : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
  97                 : "cc");
  98         } while (res);
  99
 100         if (!contended) {
 101                 smp_mb();
 102                 return 1;
 103         } else {
 104                 return 0;
 105         }
 106 }
 107
 108 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 109 {
 110         smp_mb();
 111         lock->tickets.owner++;
 112         dsb_sev();
 113 }
 114
 115 static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
 116 {
 117         return lock.tickets.owner == lock.tickets.next;
 118 }
 119
 120 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 121 {
 122         return !arch_spin_value_unlocked(READ_ONCE(*lock));
 123 }
 124
 125 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 126 {
 127         struct __raw_tickets tickets = READ_ONCE(lock->tickets);
 128         return (tickets.next - tickets.owner) > 1;
 129 }
 130 #define arch_spin_is_contended  arch_spin_is_contended
 131
 132 /*
 133  * RWLOCKS
 134  *
 135  *
 136  * Write locks are easy - we just set bit 31.  When unlocking, we can
 137  * just write zero since the lock is exclusively held.
 138  */
 139
 140 static inline void arch_write_lock(arch_rwlock_t *rw)
 141 {
 142         unsigned long tmp;
 143
 144         prefetchw(&rw->lock);
 145         __asm__ __volatile__(
 146 "1:     ldrex   %0, [%1]\n"
 147 "       teq     %0, #0\n"
 148         WFE("ne")
 149 "       strexeq %0, %2, [%1]\n"
 150 "       teq     %0, #0\n"
 151 "       bne     1b"
 152         : "=&r" (tmp)
 153         : "r" (&rw->lock), "r" (0x80000000)
 154         : "cc");
 155
 156         smp_mb();
 157 }
 158
 159 static inline int arch_write_trylock(arch_rwlock_t *rw)
 160 {
 161         unsigned long contended, res;
 162
 163         prefetchw(&rw->lock);
 164         do {
 165                 __asm__ __volatile__(
 166                 "       ldrex   %0, [%2]\n"
 167                 "       mov     %1, #0\n"
 168                 "       teq     %0, #0\n"
 169                 "       strexeq %1, %3, [%2]"
 170                 : "=&r" (contended), "=&r" (res)
 171                 : "r" (&rw->lock), "r" (0x80000000)
 172                 : "cc");
 173         } while (res);
 174
 175         if (!contended) {
 176                 smp_mb();
 177                 return 1;
 178         } else {
 179                 return 0;
 180         }
 181 }
 182
 183 static inline void arch_write_unlock(arch_rwlock_t *rw)
 184 {
 185         smp_mb();
 186
 187         __asm__ __volatile__(
 188         "str    %1, [%0]\n"
 189         :
 190         : "r" (&rw->lock), "r" (0)
 191         : "cc");
 192
 193         dsb_sev();
 194 }
 195
 196 /* write_can_lock - would write_trylock() succeed? */
 197 #define arch_write_can_lock(x)          (ACCESS_ONCE((x)->lock) == 0)
 198
 199 /*
 200  * Read locks are a bit more hairy:
 201  *  - Exclusively load the lock value.
 202  *  - Increment it.
 203  *  - Store new lock value if positive, and we still own this location.
 204  *    If the value is negative, we've already failed.
 205  *  - If we failed to store the value, we want a negative result.
 206  *  - If we failed, try again.
 207  * Unlocking is similarly hairy.  We may have multiple read locks
 208  * currently active.  However, we know we won't have any write
 209  * locks.
 210  */
 211 static inline void arch_read_lock(arch_rwlock_t *rw)
 212 {
 213         unsigned long tmp, tmp2;
 214
 215         prefetchw(&rw->lock);
 216         __asm__ __volatile__(
 217 "1:     ldrex   %0, [%2]\n"
 218 "       adds    %0, %0, #1\n"
 219 "       strexpl %1, %0, [%2]\n"
 220         WFE("mi")
 221 "       rsbpls  %0, %1, #0\n"
 222 "       bmi     1b"
 223         : "=&r" (tmp), "=&r" (tmp2)
 224         : "r" (&rw->lock)
 225         : "cc");
 226
 227         smp_mb();
 228 }
 229
 230 static inline void arch_read_unlock(arch_rwlock_t *rw)
 231 {
 232         unsigned long tmp, tmp2;
 233
 234         smp_mb();
 235
 236         prefetchw(&rw->lock);
 237         __asm__ __volatile__(
 238 "1:     ldrex   %0, [%2]\n"
 239 "       sub     %0, %0, #1\n"
 240 "       strex   %1, %0, [%2]\n"
 241 "       teq     %1, #0\n"
 242 "       bne     1b"
 243         : "=&r" (tmp), "=&r" (tmp2)
 244         : "r" (&rw->lock)
 245         : "cc");
 246
 247         if (tmp == 0)
 248                 dsb_sev();
 249 }
 250
 251 static inline int arch_read_trylock(arch_rwlock_t *rw)
 252 {
 253         unsigned long contended, res;
 254
 255         prefetchw(&rw->lock);
 256         do {
 257                 __asm__ __volatile__(
 258                 "       ldrex   %0, [%2]\n"
 259                 "       mov     %1, #0\n"
 260                 "       adds    %0, %0, #1\n"
 261                 "       strexpl %1, %0, [%2]"
 262                 : "=&r" (contended), "=&r" (res)
 263                 : "r" (&rw->lock)
 264                 : "cc");
 265         } while (res);
 266
 267         /* If the lock is negative, then it is already held for write. */
 268         if (contended < 0x80000000) {
 269                 smp_mb();
 270                 return 1;
 271         } else {
 272                 return 0;
 273         }
 274 }
 275
 276 /* read_can_lock - would read_trylock() succeed? */
 277 #define arch_read_can_lock(x)           (ACCESS_ONCE((x)->lock) < 0x80000000)
 278
 279 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
 280 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 281
 282 #define arch_spin_relax(lock)   cpu_relax()
 283 #define arch_read_relax(lock)   cpu_relax()
 284 #define arch_write_relax(lock)  cpu_relax()
 285
 286 #endif /* __ASM_SPINLOCK_H */