arch/arm/include/asm/system.h

   1 #ifndef __ASM_ARM_SYSTEM_H
   2 #define __ASM_ARM_SYSTEM_H
   3
   4 #ifdef __KERNEL__
   5
   6 #define CPU_ARCH_UNKNOWN        0
   7 #define CPU_ARCH_ARMv3          1
   8 #define CPU_ARCH_ARMv4          2
   9 #define CPU_ARCH_ARMv4T         3
  10 #define CPU_ARCH_ARMv5          4
  11 #define CPU_ARCH_ARMv5T         5
  12 #define CPU_ARCH_ARMv5TE        6
  13 #define CPU_ARCH_ARMv5TEJ       7
  14 #define CPU_ARCH_ARMv6          8
  15 #define CPU_ARCH_ARMv7          9
  16
  17 /*
  18  * CR1 bits (CP#15 CR1)
  19  */
  20 #define CR_M    (1 << 0)        /* MMU enable                           */
  21 #define CR_A    (1 << 1)        /* Alignment abort enable               */
  22 #define CR_C    (1 << 2)        /* Dcache enable                        */
  23 #define CR_W    (1 << 3)        /* Write buffer enable                  */
  24 #define CR_P    (1 << 4)        /* 32-bit exception handler             */
  25 #define CR_D    (1 << 5)        /* 32-bit data address range            */
  26 #define CR_L    (1 << 6)        /* Implementation defined               */
  27 #define CR_B    (1 << 7)        /* Big endian                           */
  28 #define CR_S    (1 << 8)        /* System MMU protection                */
  29 #define CR_R    (1 << 9)        /* ROM MMU protection                   */
  30 #define CR_F    (1 << 10)       /* Implementation defined               */
  31 #define CR_Z    (1 << 11)       /* Implementation defined               */
  32 #define CR_I    (1 << 12)       /* Icache enable                        */
  33 #define CR_V    (1 << 13)       /* Vectors relocated to 0xffff0000      */
  34 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
  35 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
  36 #define CR_DT   (1 << 16)
  37 #define CR_IT   (1 << 18)
  38 #define CR_ST   (1 << 19)
  39 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
  40 #define CR_U    (1 << 22)       /* Unaligned access operation           */
  41 #define CR_XP   (1 << 23)       /* Extended page tables                 */
  42 #define CR_VE   (1 << 24)       /* Vectored interrupts                  */
  43 #define CR_EE   (1 << 25)       /* Exception (Big) Endian               */
  44 #define CR_TRE  (1 << 28)       /* TEX remap enable                     */
  45 #define CR_AFE  (1 << 29)       /* Access flag enable                   */
  46 #define CR_TE   (1 << 30)       /* Thumb exception enable               */
  47
  48 /*
  49  * This is used to ensure the compiler did actually allocate the register we
  50  * asked it for some inline assembly sequences.  Apparently we can't trust
  51  * the compiler from one version to another so a bit of paranoia won't hurt.
  52  * This string is meant to be concatenated with the inline asm string and
  53  * will cause compilation to stop on mismatch.
  54  * (for details, see gcc PR 15089)
  55  */
  56 #define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
  57
  58 #ifndef __ASSEMBLY__
  59
  60 #include <linux/compiler.h>
  61 #include <linux/linkage.h>
  62 #include <linux/irqflags.h>
  63
  64 #include <asm/outercache.h>
  65
  66 struct thread_info;
  67 struct task_struct;
  68
  69 /* information about the system we're running on */
  70 extern unsigned int system_rev;
  71 extern unsigned int system_serial_low;
  72 extern unsigned int system_serial_high;
  73 extern unsigned int mem_fclk_21285;
  74
  75 struct pt_regs;
  76
  77 void die(const char *msg, struct pt_regs *regs, int err);
  78
  79 struct siginfo;
  80 void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
  81                 unsigned long err, unsigned long trap);
  82
  83 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
  84                                        struct pt_regs *),
  85                      int sig, int code, const char *name);
  86
  87 void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
  88                                        struct pt_regs *),
  89                      int sig, int code, const char *name);
  90
  91 #define xchg(ptr,x) \
  92         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  93
  94 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
  95
  96 struct mm_struct;
  97 extern void show_pte(struct mm_struct *mm, unsigned long addr);
  98 extern void __show_regs(struct pt_regs *);
  99
 100 extern int __pure cpu_architecture(void);
 101 extern void cpu_init(void);
 102
 103 void arm_machine_restart(char mode, const char *cmd);
 104 extern void (*arm_pm_restart)(char str, const char *cmd);
 105
 106 #define UDBG_UNDEFINED  (1 << 0)
 107 #define UDBG_SYSCALL    (1 << 1)
 108 #define UDBG_BADABORT   (1 << 2)
 109 #define UDBG_SEGV       (1 << 3)
 110 #define UDBG_BUS        (1 << 4)
 111
 112 extern unsigned int user_debug;
 113
 114 #if __LINUX_ARM_ARCH__ >= 4
 115 #define vectors_high()  (cr_alignment & CR_V)
 116 #else
 117 #define vectors_high()  (0)
 118 #endif
 119
 120 #if __LINUX_ARM_ARCH__ >= 7 ||          \
 121         (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
 122 #define sev()   __asm__ __volatile__ ("sev" : : : "memory")
 123 #define wfe()   __asm__ __volatile__ ("wfe" : : : "memory")
 124 #define wfi()   __asm__ __volatile__ ("wfi" : : : "memory")
 125 #endif
 126
 127 #if __LINUX_ARM_ARCH__ >= 7
 128 #define isb() __asm__ __volatile__ ("isb" : : : "memory")
 129 #define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
 130 #define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
 131 #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
 132 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
 133                                     : : "r" (0) : "memory")
 134 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
 135                                     : : "r" (0) : "memory")
 136 #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
 137                                     : : "r" (0) : "memory")
 138 #elif defined(CONFIG_CPU_FA526)
 139 #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
 140                                     : : "r" (0) : "memory")
 141 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
 142                                     : : "r" (0) : "memory")
 143 #define dmb() __asm__ __volatile__ ("" : : : "memory")
 144 #else
 145 #define isb() __asm__ __volatile__ ("" : : : "memory")
 146 #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
 147                                     : : "r" (0) : "memory")
 148 #define dmb() __asm__ __volatile__ ("" : : : "memory")
 149 #endif
 150
 151 #ifdef CONFIG_ARCH_HAS_BARRIERS
 152 #include <mach/barriers.h>
 153 #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
 154 #define mb()            do { dsb(); outer_sync(); } while (0)
 155 #define rmb()           dsb()
 156 #define wmb()           mb()
 157 #else
 158 #include <asm/memory.h>
 159 #define mb()    do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 160 #define rmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 161 #define wmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 162 #endif
 163
 164 #ifndef CONFIG_SMP
 165 #define smp_mb()        barrier()
 166 #define smp_rmb()       barrier()
 167 #define smp_wmb()       barrier()
 168 #else
 169 #define smp_mb()        dmb()
 170 #define smp_rmb()       dmb()
 171 #define smp_wmb()       dmb()
 172 #endif
 173
 174 #define read_barrier_depends()          do { } while(0)
 175 #define smp_read_barrier_depends()      do { } while(0)
 176
 177 #define set_mb(var, value)      do { var = value; smp_mb(); } while (0)
 178 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 179
 180 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 181 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 182
 183 static inline unsigned int get_cr(void)
 184 {
 185         unsigned int val;
 186         asm("mrc p15, 0, %0, c1, c0, 0  @ get CR" : "=r" (val) : : "cc");
 187         return val;
 188 }
 189
 190 static inline void set_cr(unsigned int val)
 191 {
 192         asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
 193           : : "r" (val) : "cc");
 194         isb();
 195 }
 196
 197 #ifndef CONFIG_SMP
 198 extern void adjust_cr(unsigned long mask, unsigned long set);
 199 #endif
 200
 201 #define CPACC_FULL(n)           (3 << (n * 2))
 202 #define CPACC_SVC(n)            (1 << (n * 2))
 203 #define CPACC_DISABLE(n)        (0 << (n * 2))
 204
 205 static inline unsigned int get_copro_access(void)
 206 {
 207         unsigned int val;
 208         asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
 209           : "=r" (val) : : "cc");
 210         return val;
 211 }
 212
 213 static inline void set_copro_access(unsigned int val)
 214 {
 215         asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
 216           : : "r" (val) : "cc");
 217         isb();
 218 }
 219
 220 /*
 221  * switch_mm() may do a full cache flush over the context switch,
 222  * so enable interrupts over the context switch to avoid high
 223  * latency.
 224  */
 225 #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
 226
 227 /*
 228  * switch_to(prev, next) should switch from task `prev' to `next'
 229  * `prev' will never be the same as `next'.  schedule() itself
 230  * contains the memory barrier to tell GCC not to cache `current'.
 231  */
 232 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
 233
 234 #define switch_to(prev,next,last)                                       \
 235 do {                                                                    \
 236         last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));        \
 237 } while (0)
 238
 239 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
 240 /*
 241  * On the StrongARM, "swp" is terminally broken since it bypasses the
 242  * cache totally.  This means that the cache becomes inconsistent, and,
 243  * since we use normal loads/stores as well, this is really bad.
 244  * Typically, this causes oopsen in filp_close, but could have other,
 245  * more disastrous effects.  There are two work-arounds:
 246  *  1. Disable interrupts and emulate the atomic swap
 247  *  2. Clean the cache, perform atomic swap, flush the cache
 248  *
 249  * We choose (1) since its the "easiest" to achieve here and is not
 250  * dependent on the processor type.
 251  *
 252  * NOTE that this solution won't work on an SMP system, so explcitly
 253  * forbid it here.
 254  */
 255 #define swp_is_buggy
 256 #endif
 257
 258 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 259 {
 260         extern void __bad_xchg(volatile void *, int);
 261         unsigned long ret;
 262 #ifdef swp_is_buggy
 263         unsigned long flags;
 264 #endif
 265 #if __LINUX_ARM_ARCH__ >= 6
 266         unsigned int tmp;
 267 #endif
 268
 269         smp_mb();
 270
 271         switch (size) {
 272 #if __LINUX_ARM_ARCH__ >= 6
 273         case 1:
 274                 asm volatile("@ __xchg1\n"
 275                 "1:     ldrexb  %0, [%3]\n"
 276                 "       strexb  %1, %2, [%3]\n"
 277                 "       teq     %1, #0\n"
 278                 "       bne     1b"
 279                         : "=&r" (ret), "=&r" (tmp)
 280                         : "r" (x), "r" (ptr)
 281                         : "memory", "cc");
 282                 break;
 283         case 4:
 284                 asm volatile("@ __xchg4\n"
 285                 "1:     ldrex   %0, [%3]\n"
 286                 "       strex   %1, %2, [%3]\n"
 287                 "       teq     %1, #0\n"
 288                 "       bne     1b"
 289                         : "=&r" (ret), "=&r" (tmp)
 290                         : "r" (x), "r" (ptr)
 291                         : "memory", "cc");
 292                 break;
 293 #elif defined(swp_is_buggy)
 294 #ifdef CONFIG_SMP
 295 #error SMP is not supported on this platform
 296 #endif
 297         case 1:
 298                 raw_local_irq_save(flags);
 299                 ret = *(volatile unsigned char *)ptr;
 300                 *(volatile unsigned char *)ptr = x;
 301                 raw_local_irq_restore(flags);
 302                 break;
 303
 304         case 4:
 305                 raw_local_irq_save(flags);
 306                 ret = *(volatile unsigned long *)ptr;
 307                 *(volatile unsigned long *)ptr = x;
 308                 raw_local_irq_restore(flags);
 309                 break;
 310 #else
 311         case 1:
 312                 asm volatile("@ __xchg1\n"
 313                 "       swpb    %0, %1, [%2]"
 314                         : "=&r" (ret)
 315                         : "r" (x), "r" (ptr)
 316                         : "memory", "cc");
 317                 break;
 318         case 4:
 319                 asm volatile("@ __xchg4\n"
 320                 "       swp     %0, %1, [%2]"
 321                         : "=&r" (ret)
 322                         : "r" (x), "r" (ptr)
 323                         : "memory", "cc");
 324                 break;
 325 #endif
 326         default:
 327                 __bad_xchg(ptr, size), ret = 0;
 328                 break;
 329         }
 330         smp_mb();
 331
 332         return ret;
 333 }
 334
 335 extern void disable_hlt(void);
 336 extern void enable_hlt(void);
 337
 338 void cpu_idle_wait(void);
 339
 340 #include <asm-generic/cmpxchg-local.h>
 341
 342 #if __LINUX_ARM_ARCH__ < 6
 343 /* min ARCH < ARMv6 */
 344
 345 #ifdef CONFIG_SMP
 346 #error "SMP is not supported on this platform"
 347 #endif
 348
 349 /*
 350  * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 351  * them available.
 352  */
 353 #define cmpxchg_local(ptr, o, n)                                               \
 354         ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
 355                         (unsigned long)(n), sizeof(*(ptr))))
 356 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 357
 358 #ifndef CONFIG_SMP
 359 #include <asm-generic/cmpxchg.h>
 360 #endif
 361
 362 #else   /* min ARCH >= ARMv6 */
 363
 364 extern void __bad_cmpxchg(volatile void *ptr, int size);
 365
 366 /*
 367  * cmpxchg only support 32-bits operands on ARMv6.
 368  */
 369
 370 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 371                                       unsigned long new, int size)
 372 {
 373         unsigned long oldval, res;
 374
 375         switch (size) {
 376 #ifndef CONFIG_CPU_V6   /* min ARCH >= ARMv6K */
 377         case 1:
 378                 do {
 379                         asm volatile("@ __cmpxchg1\n"
 380                         "       ldrexb  %1, [%2]\n"
 381                         "       mov     %0, #0\n"
 382                         "       teq     %1, %3\n"
 383                         "       strexbeq %0, %4, [%2]\n"
 384                                 : "=&r" (res), "=&r" (oldval)
 385                                 : "r" (ptr), "Ir" (old), "r" (new)
 386                                 : "memory", "cc");
 387                 } while (res);
 388                 break;
 389         case 2:
 390                 do {
 391                         asm volatile("@ __cmpxchg1\n"
 392                         "       ldrexh  %1, [%2]\n"
 393                         "       mov     %0, #0\n"
 394                         "       teq     %1, %3\n"
 395                         "       strexheq %0, %4, [%2]\n"
 396                                 : "=&r" (res), "=&r" (oldval)
 397                                 : "r" (ptr), "Ir" (old), "r" (new)
 398                                 : "memory", "cc");
 399                 } while (res);
 400                 break;
 401 #endif
 402         case 4:
 403                 do {
 404                         asm volatile("@ __cmpxchg4\n"
 405                         "       ldrex   %1, [%2]\n"
 406                         "       mov     %0, #0\n"
 407                         "       teq     %1, %3\n"
 408                         "       strexeq %0, %4, [%2]\n"
 409                                 : "=&r" (res), "=&r" (oldval)
 410                                 : "r" (ptr), "Ir" (old), "r" (new)
 411                                 : "memory", "cc");
 412                 } while (res);
 413                 break;
 414         default:
 415                 __bad_cmpxchg(ptr, size);
 416                 oldval = 0;
 417         }
 418
 419         return oldval;
 420 }
 421
 422 static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
 423                                          unsigned long new, int size)
 424 {
 425         unsigned long ret;
 426
 427         smp_mb();
 428         ret = __cmpxchg(ptr, old, new, size);
 429         smp_mb();
 430
 431         return ret;
 432 }
 433
 434 #define cmpxchg(ptr,o,n)                                                \
 435         ((__typeof__(*(ptr)))__cmpxchg_mb((ptr),                        \
 436                                           (unsigned long)(o),           \
 437                                           (unsigned long)(n),           \
 438                                           sizeof(*(ptr))))
 439
 440 static inline unsigned long __cmpxchg_local(volatile void *ptr,
 441                                             unsigned long old,
 442                                             unsigned long new, int size)
 443 {
 444         unsigned long ret;
 445
 446         switch (size) {
 447 #ifdef CONFIG_CPU_V6    /* min ARCH == ARMv6 */
 448         case 1:
 449         case 2:
 450                 ret = __cmpxchg_local_generic(ptr, old, new, size);
 451                 break;
 452 #endif
 453         default:
 454                 ret = __cmpxchg(ptr, old, new, size);
 455         }
 456
 457         return ret;
 458 }
 459
 460 #define cmpxchg_local(ptr,o,n)                                          \
 461         ((__typeof__(*(ptr)))__cmpxchg_local((ptr),                     \
 462                                        (unsigned long)(o),              \
 463                                        (unsigned long)(n),              \
 464                                        sizeof(*(ptr))))
 465
 466 #ifndef CONFIG_CPU_V6   /* min ARCH >= ARMv6K */
 467
 468 /*
 469  * Note : ARMv7-M (currently unsupported by Linux) does not support
 470  * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
 471  * not be allowed to use __cmpxchg64.
 472  */
 473 static inline unsigned long long __cmpxchg64(volatile void *ptr,
 474                                              unsigned long long old,
 475                                              unsigned long long new)
 476 {
 477         register unsigned long long oldval asm("r0");
 478         register unsigned long long __old asm("r2") = old;
 479         register unsigned long long __new asm("r4") = new;
 480         unsigned long res;
 481
 482         do {
 483                 asm volatile(
 484                 "       @ __cmpxchg8\n"
 485                 "       ldrexd  %1, %H1, [%2]\n"
 486                 "       mov     %0, #0\n"
 487                 "       teq     %1, %3\n"
 488                 "       teqeq   %H1, %H3\n"
 489                 "       strexdeq %0, %4, %H4, [%2]\n"
 490                         : "=&r" (res), "=&r" (oldval)
 491                         : "r" (ptr), "Ir" (__old), "r" (__new)
 492                         : "memory", "cc");
 493         } while (res);
 494
 495         return oldval;
 496 }
 497
 498 static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
 499                                                 unsigned long long old,
 500                                                 unsigned long long new)
 501 {
 502         unsigned long long ret;
 503
 504         smp_mb();
 505         ret = __cmpxchg64(ptr, old, new);
 506         smp_mb();
 507
 508         return ret;
 509 }
 510
 511 #define cmpxchg64(ptr,o,n)                                              \
 512         ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),                      \
 513                                             (unsigned long long)(o),    \
 514                                             (unsigned long long)(n)))
 515
 516 #define cmpxchg64_local(ptr,o,n)                                        \
 517         ((__typeof__(*(ptr)))__cmpxchg64((ptr),                         \
 518                                          (unsigned long long)(o),       \
 519                                          (unsigned long long)(n)))
 520
 521 #else /* min ARCH = ARMv6 */
 522
 523 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 524
 525 #endif
 526
 527 #endif  /* __LINUX_ARM_ARCH__ >= 6 */
 528
 529 #endif /* __ASSEMBLY__ */
 530
 531 #define arch_align_stack(x) (x)
 532
 533 #endif /* __KERNEL__ */
 534
 535 #endif