4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
12 #define pr_fmt(fmt) "hw perfevents: " fmt
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/irq.h>
18 #include <linux/irqdesc.h>
20 #include <asm/irq_regs.h>
24 armpmu_map_cache_event(const unsigned (*cache_map
)
25 [PERF_COUNT_HW_CACHE_MAX
]
26 [PERF_COUNT_HW_CACHE_OP_MAX
]
27 [PERF_COUNT_HW_CACHE_RESULT_MAX
],
30 unsigned int cache_type
, cache_op
, cache_result
, ret
;
32 cache_type
= (config
>> 0) & 0xff;
33 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
36 cache_op
= (config
>> 8) & 0xff;
37 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
40 cache_result
= (config
>> 16) & 0xff;
41 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
44 ret
= (int)(*cache_map
)[cache_type
][cache_op
][cache_result
];
46 if (ret
== CACHE_OP_UNSUPPORTED
)
53 armpmu_map_hw_event(const unsigned (*event_map
)[PERF_COUNT_HW_MAX
], u64 config
)
57 if (config
>= PERF_COUNT_HW_MAX
)
60 mapping
= (*event_map
)[config
];
61 return mapping
== HW_OP_UNSUPPORTED
? -ENOENT
: mapping
;
65 armpmu_map_raw_event(u32 raw_event_mask
, u64 config
)
67 return (int)(config
& raw_event_mask
);
71 armpmu_map_event(struct perf_event
*event
,
72 const unsigned (*event_map
)[PERF_COUNT_HW_MAX
],
73 const unsigned (*cache_map
)
74 [PERF_COUNT_HW_CACHE_MAX
]
75 [PERF_COUNT_HW_CACHE_OP_MAX
]
76 [PERF_COUNT_HW_CACHE_RESULT_MAX
],
79 u64 config
= event
->attr
.config
;
80 int type
= event
->attr
.type
;
82 if (type
== event
->pmu
->type
)
83 return armpmu_map_raw_event(raw_event_mask
, config
);
86 case PERF_TYPE_HARDWARE
:
87 return armpmu_map_hw_event(event_map
, config
);
88 case PERF_TYPE_HW_CACHE
:
89 return armpmu_map_cache_event(cache_map
, config
);
91 return armpmu_map_raw_event(raw_event_mask
, config
);
97 int armpmu_event_set_period(struct perf_event
*event
)
99 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
100 struct hw_perf_event
*hwc
= &event
->hw
;
101 s64 left
= local64_read(&hwc
->period_left
);
102 s64 period
= hwc
->sample_period
;
105 if (unlikely(left
<= -period
)) {
107 local64_set(&hwc
->period_left
, left
);
108 hwc
->last_period
= period
;
112 if (unlikely(left
<= 0)) {
114 local64_set(&hwc
->period_left
, left
);
115 hwc
->last_period
= period
;
119 if (left
> (s64
)armpmu
->max_period
)
120 left
= armpmu
->max_period
;
122 local64_set(&hwc
->prev_count
, (u64
)-left
);
124 armpmu
->write_counter(event
, (u64
)(-left
) & 0xffffffff);
126 perf_event_update_userpage(event
);
131 u64
armpmu_event_update(struct perf_event
*event
)
133 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
134 struct hw_perf_event
*hwc
= &event
->hw
;
135 u64 delta
, prev_raw_count
, new_raw_count
;
138 prev_raw_count
= local64_read(&hwc
->prev_count
);
139 new_raw_count
= armpmu
->read_counter(event
);
141 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
142 new_raw_count
) != prev_raw_count
)
145 delta
= (new_raw_count
- prev_raw_count
) & armpmu
->max_period
;
147 local64_add(delta
, &event
->count
);
148 local64_sub(delta
, &hwc
->period_left
);
150 return new_raw_count
;
154 armpmu_read(struct perf_event
*event
)
156 armpmu_event_update(event
);
160 armpmu_stop(struct perf_event
*event
, int flags
)
162 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
163 struct hw_perf_event
*hwc
= &event
->hw
;
166 * ARM pmu always has to update the counter, so ignore
167 * PERF_EF_UPDATE, see comments in armpmu_start().
169 if (!(hwc
->state
& PERF_HES_STOPPED
)) {
170 armpmu
->disable(event
);
171 armpmu_event_update(event
);
172 hwc
->state
|= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
176 static void armpmu_start(struct perf_event
*event
, int flags
)
178 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
179 struct hw_perf_event
*hwc
= &event
->hw
;
182 * ARM pmu always has to reprogram the period, so ignore
183 * PERF_EF_RELOAD, see the comment below.
185 if (flags
& PERF_EF_RELOAD
)
186 WARN_ON_ONCE(!(hwc
->state
& PERF_HES_UPTODATE
));
190 * Set the period again. Some counters can't be stopped, so when we
191 * were stopped we simply disabled the IRQ source and the counter
192 * may have been left counting. If we don't do this step then we may
193 * get an interrupt too soon or *way* too late if the overflow has
194 * happened since disabling.
196 armpmu_event_set_period(event
);
197 armpmu
->enable(event
);
201 armpmu_del(struct perf_event
*event
, int flags
)
203 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
204 struct pmu_hw_events
*hw_events
= this_cpu_ptr(armpmu
->hw_events
);
205 struct hw_perf_event
*hwc
= &event
->hw
;
208 armpmu_stop(event
, PERF_EF_UPDATE
);
209 hw_events
->events
[idx
] = NULL
;
210 clear_bit(idx
, hw_events
->used_mask
);
211 if (armpmu
->clear_event_idx
)
212 armpmu
->clear_event_idx(hw_events
, event
);
214 perf_event_update_userpage(event
);
218 armpmu_add(struct perf_event
*event
, int flags
)
220 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
221 struct pmu_hw_events
*hw_events
= this_cpu_ptr(armpmu
->hw_events
);
222 struct hw_perf_event
*hwc
= &event
->hw
;
226 perf_pmu_disable(event
->pmu
);
228 /* If we don't have a space for the counter then finish early. */
229 idx
= armpmu
->get_event_idx(hw_events
, event
);
236 * If there is an event in the counter we are going to use then make
237 * sure it is disabled.
240 armpmu
->disable(event
);
241 hw_events
->events
[idx
] = event
;
243 hwc
->state
= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
244 if (flags
& PERF_EF_START
)
245 armpmu_start(event
, PERF_EF_RELOAD
);
247 /* Propagate our changes to the userspace mapping. */
248 perf_event_update_userpage(event
);
251 perf_pmu_enable(event
->pmu
);
256 validate_event(struct pmu_hw_events
*hw_events
,
257 struct perf_event
*event
)
259 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
261 if (is_software_event(event
))
264 if (event
->state
< PERF_EVENT_STATE_OFF
)
267 if (event
->state
== PERF_EVENT_STATE_OFF
&& !event
->attr
.enable_on_exec
)
270 return armpmu
->get_event_idx(hw_events
, event
) >= 0;
274 validate_group(struct perf_event
*event
)
276 struct perf_event
*sibling
, *leader
= event
->group_leader
;
277 struct pmu_hw_events fake_pmu
;
280 * Initialise the fake PMU. We only need to populate the
281 * used_mask for the purposes of validation.
283 memset(&fake_pmu
.used_mask
, 0, sizeof(fake_pmu
.used_mask
));
285 if (!validate_event(&fake_pmu
, leader
))
288 list_for_each_entry(sibling
, &leader
->sibling_list
, group_entry
) {
289 if (!validate_event(&fake_pmu
, sibling
))
293 if (!validate_event(&fake_pmu
, event
))
299 static irqreturn_t
armpmu_dispatch_irq(int irq
, void *dev
)
301 struct arm_pmu
*armpmu
;
302 struct platform_device
*plat_device
;
303 struct arm_pmu_platdata
*plat
;
305 u64 start_clock
, finish_clock
;
308 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
309 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
310 * do any necessary shifting, we just need to perform the first
313 armpmu
= *(void **)dev
;
314 plat_device
= armpmu
->plat_device
;
315 plat
= dev_get_platdata(&plat_device
->dev
);
317 start_clock
= sched_clock();
318 if (plat
&& plat
->handle_irq
)
319 ret
= plat
->handle_irq(irq
, armpmu
, armpmu
->handle_irq
);
321 ret
= armpmu
->handle_irq(irq
, armpmu
);
322 finish_clock
= sched_clock();
324 perf_sample_event_took(finish_clock
- start_clock
);
329 armpmu_release_hardware(struct arm_pmu
*armpmu
)
331 armpmu
->free_irq(armpmu
);
332 pm_runtime_put_sync(&armpmu
->plat_device
->dev
);
336 armpmu_reserve_hardware(struct arm_pmu
*armpmu
)
339 struct platform_device
*pmu_device
= armpmu
->plat_device
;
344 pm_runtime_get_sync(&pmu_device
->dev
);
345 err
= armpmu
->request_irq(armpmu
, armpmu_dispatch_irq
);
347 armpmu_release_hardware(armpmu
);
355 hw_perf_event_destroy(struct perf_event
*event
)
357 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
358 atomic_t
*active_events
= &armpmu
->active_events
;
359 struct mutex
*pmu_reserve_mutex
= &armpmu
->reserve_mutex
;
361 if (atomic_dec_and_mutex_lock(active_events
, pmu_reserve_mutex
)) {
362 armpmu_release_hardware(armpmu
);
363 mutex_unlock(pmu_reserve_mutex
);
368 event_requires_mode_exclusion(struct perf_event_attr
*attr
)
370 return attr
->exclude_idle
|| attr
->exclude_user
||
371 attr
->exclude_kernel
|| attr
->exclude_hv
;
375 __hw_perf_event_init(struct perf_event
*event
)
377 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
378 struct hw_perf_event
*hwc
= &event
->hw
;
381 mapping
= armpmu
->map_event(event
);
384 pr_debug("event %x:%llx not supported\n", event
->attr
.type
,
390 * We don't assign an index until we actually place the event onto
391 * hardware. Use -1 to signify that we haven't decided where to put it
392 * yet. For SMP systems, each core has it's own PMU so we can't do any
393 * clever allocation or constraints checking at this point.
396 hwc
->config_base
= 0;
401 * Check whether we need to exclude the counter from certain modes.
403 if ((!armpmu
->set_event_filter
||
404 armpmu
->set_event_filter(hwc
, &event
->attr
)) &&
405 event_requires_mode_exclusion(&event
->attr
)) {
406 pr_debug("ARM performance counters do not support "
412 * Store the event encoding into the config_base field.
414 hwc
->config_base
|= (unsigned long)mapping
;
416 if (!is_sampling_event(event
)) {
418 * For non-sampling runs, limit the sample_period to half
419 * of the counter width. That way, the new counter value
420 * is far less likely to overtake the previous one unless
421 * you have some serious IRQ latency issues.
423 hwc
->sample_period
= armpmu
->max_period
>> 1;
424 hwc
->last_period
= hwc
->sample_period
;
425 local64_set(&hwc
->period_left
, hwc
->sample_period
);
428 if (event
->group_leader
!= event
) {
429 if (validate_group(event
) != 0)
436 static int armpmu_event_init(struct perf_event
*event
)
438 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
440 atomic_t
*active_events
= &armpmu
->active_events
;
442 /* does not support taken branch sampling */
443 if (has_branch_stack(event
))
446 if (armpmu
->map_event(event
) == -ENOENT
)
449 event
->destroy
= hw_perf_event_destroy
;
451 if (!atomic_inc_not_zero(active_events
)) {
452 mutex_lock(&armpmu
->reserve_mutex
);
453 if (atomic_read(active_events
) == 0)
454 err
= armpmu_reserve_hardware(armpmu
);
457 atomic_inc(active_events
);
458 mutex_unlock(&armpmu
->reserve_mutex
);
464 err
= __hw_perf_event_init(event
);
466 hw_perf_event_destroy(event
);
471 static void armpmu_enable(struct pmu
*pmu
)
473 struct arm_pmu
*armpmu
= to_arm_pmu(pmu
);
474 struct pmu_hw_events
*hw_events
= this_cpu_ptr(armpmu
->hw_events
);
475 int enabled
= bitmap_weight(hw_events
->used_mask
, armpmu
->num_events
);
478 armpmu
->start(armpmu
);
481 static void armpmu_disable(struct pmu
*pmu
)
483 struct arm_pmu
*armpmu
= to_arm_pmu(pmu
);
484 armpmu
->stop(armpmu
);
487 #ifdef CONFIG_PM_RUNTIME
488 static int armpmu_runtime_resume(struct device
*dev
)
490 struct arm_pmu_platdata
*plat
= dev_get_platdata(dev
);
492 if (plat
&& plat
->runtime_resume
)
493 return plat
->runtime_resume(dev
);
498 static int armpmu_runtime_suspend(struct device
*dev
)
500 struct arm_pmu_platdata
*plat
= dev_get_platdata(dev
);
502 if (plat
&& plat
->runtime_suspend
)
503 return plat
->runtime_suspend(dev
);
509 const struct dev_pm_ops armpmu_dev_pm_ops
= {
510 SET_RUNTIME_PM_OPS(armpmu_runtime_suspend
, armpmu_runtime_resume
, NULL
)
513 static void armpmu_init(struct arm_pmu
*armpmu
)
515 atomic_set(&armpmu
->active_events
, 0);
516 mutex_init(&armpmu
->reserve_mutex
);
518 armpmu
->pmu
= (struct pmu
) {
519 .pmu_enable
= armpmu_enable
,
520 .pmu_disable
= armpmu_disable
,
521 .event_init
= armpmu_event_init
,
524 .start
= armpmu_start
,
530 int armpmu_register(struct arm_pmu
*armpmu
, int type
)
533 pm_runtime_enable(&armpmu
->plat_device
->dev
);
534 pr_info("enabled with %s PMU driver, %d counters available\n",
535 armpmu
->name
, armpmu
->num_events
);
536 return perf_pmu_register(&armpmu
->pmu
, armpmu
->name
, type
);