4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/perf_event.h>
19 #include <linux/platform_device.h>
20 #include <linux/spinlock.h>
21 #include <linux/uaccess.h>
23 #include <asm/cputype.h>
25 #include <asm/irq_regs.h>
27 #include <asm/stacktrace.h>
30 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
31 * another platform that supports more, we need to increase this to be the
32 * largest of all platforms.
34 * ARMv7 supports up to 32 events:
35 * cycle counter CCNT + 31 events counters CNT0..30.
36 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
38 #define ARMPMU_MAX_HWEVENTS 32
40 /* The events for a given CPU. */
41 struct cpu_hw_events
{
43 * The events that are active on the CPU for the given index.
45 struct perf_event
*events
[ARMPMU_MAX_HWEVENTS
];
48 * A 1 bit for an index indicates that the counter is being used for
49 * an event. A 0 means that the counter can be used.
51 unsigned long used_mask
[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS
)];
54 * Hardware lock to serialize accesses to PMU registers. Needed for the
55 * read/modify/write sequences.
57 raw_spinlock_t pmu_lock
;
59 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
);
62 enum arm_perf_pmu_ids id
;
63 enum arm_pmu_type type
;
64 cpumask_t active_irqs
;
66 irqreturn_t (*handle_irq
)(int irq_num
, void *dev
);
67 void (*enable
)(struct hw_perf_event
*evt
, int idx
);
68 void (*disable
)(struct hw_perf_event
*evt
, int idx
);
69 int (*get_event_idx
)(struct cpu_hw_events
*cpuc
,
70 struct hw_perf_event
*hwc
);
71 int (*set_event_filter
)(struct hw_perf_event
*evt
,
72 struct perf_event_attr
*attr
);
73 u32 (*read_counter
)(int idx
);
74 void (*write_counter
)(int idx
, u32 val
);
77 void (*reset
)(void *);
78 const unsigned (*cache_map
)[PERF_COUNT_HW_CACHE_MAX
]
79 [PERF_COUNT_HW_CACHE_OP_MAX
]
80 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
81 const unsigned (*event_map
)[PERF_COUNT_HW_MAX
];
84 atomic_t active_events
;
85 struct mutex reserve_mutex
;
87 struct platform_device
*plat_device
;
88 struct cpu_hw_events
*(*get_hw_events
)(void);
91 /* Set at runtime when we know what CPU type we are. */
92 static struct arm_pmu
*armpmu
;
95 armpmu_get_pmu_id(void)
104 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id
);
107 armpmu_get_max_events(void)
112 max_events
= armpmu
->num_events
;
116 EXPORT_SYMBOL_GPL(armpmu_get_max_events
);
118 int perf_num_counters(void)
120 return armpmu_get_max_events();
122 EXPORT_SYMBOL_GPL(perf_num_counters
);
124 #define HW_OP_UNSUPPORTED 0xFFFF
127 PERF_COUNT_HW_CACHE_##_x
129 #define CACHE_OP_UNSUPPORTED 0xFFFF
132 armpmu_map_cache_event(u64 config
)
134 unsigned int cache_type
, cache_op
, cache_result
, ret
;
136 cache_type
= (config
>> 0) & 0xff;
137 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
140 cache_op
= (config
>> 8) & 0xff;
141 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
144 cache_result
= (config
>> 16) & 0xff;
145 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
148 ret
= (int)(*armpmu
->cache_map
)[cache_type
][cache_op
][cache_result
];
150 if (ret
== CACHE_OP_UNSUPPORTED
)
157 armpmu_map_event(u64 config
)
159 int mapping
= (*armpmu
->event_map
)[config
];
160 return mapping
== HW_OP_UNSUPPORTED
? -EOPNOTSUPP
: mapping
;
164 armpmu_map_raw_event(u64 config
)
166 return (int)(config
& armpmu
->raw_event_mask
);
170 armpmu_event_set_period(struct perf_event
*event
,
171 struct hw_perf_event
*hwc
,
174 s64 left
= local64_read(&hwc
->period_left
);
175 s64 period
= hwc
->sample_period
;
178 if (unlikely(left
<= -period
)) {
180 local64_set(&hwc
->period_left
, left
);
181 hwc
->last_period
= period
;
185 if (unlikely(left
<= 0)) {
187 local64_set(&hwc
->period_left
, left
);
188 hwc
->last_period
= period
;
192 if (left
> (s64
)armpmu
->max_period
)
193 left
= armpmu
->max_period
;
195 local64_set(&hwc
->prev_count
, (u64
)-left
);
197 armpmu
->write_counter(idx
, (u64
)(-left
) & 0xffffffff);
199 perf_event_update_userpage(event
);
205 armpmu_event_update(struct perf_event
*event
,
206 struct hw_perf_event
*hwc
,
207 int idx
, int overflow
)
209 u64 delta
, prev_raw_count
, new_raw_count
;
212 prev_raw_count
= local64_read(&hwc
->prev_count
);
213 new_raw_count
= armpmu
->read_counter(idx
);
215 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
216 new_raw_count
) != prev_raw_count
)
219 new_raw_count
&= armpmu
->max_period
;
220 prev_raw_count
&= armpmu
->max_period
;
223 delta
= armpmu
->max_period
- prev_raw_count
+ new_raw_count
+ 1;
225 delta
= new_raw_count
- prev_raw_count
;
227 local64_add(delta
, &event
->count
);
228 local64_sub(delta
, &hwc
->period_left
);
230 return new_raw_count
;
234 armpmu_read(struct perf_event
*event
)
236 struct hw_perf_event
*hwc
= &event
->hw
;
238 /* Don't read disabled counters! */
242 armpmu_event_update(event
, hwc
, hwc
->idx
, 0);
246 armpmu_stop(struct perf_event
*event
, int flags
)
248 struct hw_perf_event
*hwc
= &event
->hw
;
251 * ARM pmu always has to update the counter, so ignore
252 * PERF_EF_UPDATE, see comments in armpmu_start().
254 if (!(hwc
->state
& PERF_HES_STOPPED
)) {
255 armpmu
->disable(hwc
, hwc
->idx
);
256 barrier(); /* why? */
257 armpmu_event_update(event
, hwc
, hwc
->idx
, 0);
258 hwc
->state
|= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
263 armpmu_start(struct perf_event
*event
, int flags
)
265 struct hw_perf_event
*hwc
= &event
->hw
;
268 * ARM pmu always has to reprogram the period, so ignore
269 * PERF_EF_RELOAD, see the comment below.
271 if (flags
& PERF_EF_RELOAD
)
272 WARN_ON_ONCE(!(hwc
->state
& PERF_HES_UPTODATE
));
276 * Set the period again. Some counters can't be stopped, so when we
277 * were stopped we simply disabled the IRQ source and the counter
278 * may have been left counting. If we don't do this step then we may
279 * get an interrupt too soon or *way* too late if the overflow has
280 * happened since disabling.
282 armpmu_event_set_period(event
, hwc
, hwc
->idx
);
283 armpmu
->enable(hwc
, hwc
->idx
);
287 armpmu_del(struct perf_event
*event
, int flags
)
289 struct cpu_hw_events
*cpuc
= armpmu
->get_hw_events();
290 struct hw_perf_event
*hwc
= &event
->hw
;
295 armpmu_stop(event
, PERF_EF_UPDATE
);
296 cpuc
->events
[idx
] = NULL
;
297 clear_bit(idx
, cpuc
->used_mask
);
299 perf_event_update_userpage(event
);
303 armpmu_add(struct perf_event
*event
, int flags
)
305 struct cpu_hw_events
*cpuc
= armpmu
->get_hw_events();
306 struct hw_perf_event
*hwc
= &event
->hw
;
310 perf_pmu_disable(event
->pmu
);
312 /* If we don't have a space for the counter then finish early. */
313 idx
= armpmu
->get_event_idx(cpuc
, hwc
);
320 * If there is an event in the counter we are going to use then make
321 * sure it is disabled.
324 armpmu
->disable(hwc
, idx
);
325 cpuc
->events
[idx
] = event
;
327 hwc
->state
= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
328 if (flags
& PERF_EF_START
)
329 armpmu_start(event
, PERF_EF_RELOAD
);
331 /* Propagate our changes to the userspace mapping. */
332 perf_event_update_userpage(event
);
335 perf_pmu_enable(event
->pmu
);
339 static struct pmu pmu
;
342 validate_event(struct cpu_hw_events
*cpuc
,
343 struct perf_event
*event
)
345 struct hw_perf_event fake_event
= event
->hw
;
346 struct pmu
*leader_pmu
= event
->group_leader
->pmu
;
348 if (event
->pmu
!= leader_pmu
|| event
->state
<= PERF_EVENT_STATE_OFF
)
351 return armpmu
->get_event_idx(cpuc
, &fake_event
) >= 0;
355 validate_group(struct perf_event
*event
)
357 struct perf_event
*sibling
, *leader
= event
->group_leader
;
358 struct cpu_hw_events fake_pmu
;
360 memset(&fake_pmu
, 0, sizeof(fake_pmu
));
362 if (!validate_event(&fake_pmu
, leader
))
365 list_for_each_entry(sibling
, &leader
->sibling_list
, group_entry
) {
366 if (!validate_event(&fake_pmu
, sibling
))
370 if (!validate_event(&fake_pmu
, event
))
376 static irqreturn_t
armpmu_platform_irq(int irq
, void *dev
)
378 struct platform_device
*plat_device
= armpmu
->plat_device
;
379 struct arm_pmu_platdata
*plat
= dev_get_platdata(&plat_device
->dev
);
381 return plat
->handle_irq(irq
, dev
, armpmu
->handle_irq
);
385 armpmu_release_hardware(void)
388 struct platform_device
*pmu_device
= armpmu
->plat_device
;
390 irqs
= min(pmu_device
->num_resources
, num_possible_cpus());
392 for (i
= 0; i
< irqs
; ++i
) {
393 if (!cpumask_test_and_clear_cpu(i
, &armpmu
->active_irqs
))
395 irq
= platform_get_irq(pmu_device
, i
);
400 release_pmu(armpmu
->type
);
404 armpmu_reserve_hardware(void)
406 struct arm_pmu_platdata
*plat
;
407 irq_handler_t handle_irq
;
408 int i
, err
, irq
, irqs
;
409 struct platform_device
*pmu_device
= armpmu
->plat_device
;
411 err
= reserve_pmu(armpmu
->type
);
413 pr_warning("unable to reserve pmu\n");
417 plat
= dev_get_platdata(&pmu_device
->dev
);
418 if (plat
&& plat
->handle_irq
)
419 handle_irq
= armpmu_platform_irq
;
421 handle_irq
= armpmu
->handle_irq
;
423 irqs
= min(pmu_device
->num_resources
, num_possible_cpus());
425 pr_err("no irqs for PMUs defined\n");
429 for (i
= 0; i
< irqs
; ++i
) {
431 irq
= platform_get_irq(pmu_device
, i
);
436 * If we have a single PMU interrupt that we can't shift,
437 * assume that we're running on a uniprocessor machine and
438 * continue. Otherwise, continue without this interrupt.
440 if (irq_set_affinity(irq
, cpumask_of(i
)) && irqs
> 1) {
441 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
446 err
= request_irq(irq
, handle_irq
,
447 IRQF_DISABLED
| IRQF_NOBALANCING
,
450 pr_err("unable to request IRQ%d for ARM PMU counters\n",
452 armpmu_release_hardware();
456 cpumask_set_cpu(i
, &armpmu
->active_irqs
);
463 hw_perf_event_destroy(struct perf_event
*event
)
465 atomic_t
*active_events
= &armpmu
->active_events
;
466 struct mutex
*pmu_reserve_mutex
= &armpmu
->reserve_mutex
;
468 if (atomic_dec_and_mutex_lock(active_events
, pmu_reserve_mutex
)) {
469 armpmu_release_hardware();
470 mutex_unlock(pmu_reserve_mutex
);
475 event_requires_mode_exclusion(struct perf_event_attr
*attr
)
477 return attr
->exclude_idle
|| attr
->exclude_user
||
478 attr
->exclude_kernel
|| attr
->exclude_hv
;
482 __hw_perf_event_init(struct perf_event
*event
)
484 struct hw_perf_event
*hwc
= &event
->hw
;
487 /* Decode the generic type into an ARM event identifier. */
488 if (PERF_TYPE_HARDWARE
== event
->attr
.type
) {
489 mapping
= armpmu_map_event(event
->attr
.config
);
490 } else if (PERF_TYPE_HW_CACHE
== event
->attr
.type
) {
491 mapping
= armpmu_map_cache_event(event
->attr
.config
);
492 } else if (PERF_TYPE_RAW
== event
->attr
.type
) {
493 mapping
= armpmu_map_raw_event(event
->attr
.config
);
495 pr_debug("event type %x not supported\n", event
->attr
.type
);
500 pr_debug("event %x:%llx not supported\n", event
->attr
.type
,
506 * We don't assign an index until we actually place the event onto
507 * hardware. Use -1 to signify that we haven't decided where to put it
508 * yet. For SMP systems, each core has it's own PMU so we can't do any
509 * clever allocation or constraints checking at this point.
512 hwc
->config_base
= 0;
517 * Check whether we need to exclude the counter from certain modes.
519 if ((!armpmu
->set_event_filter
||
520 armpmu
->set_event_filter(hwc
, &event
->attr
)) &&
521 event_requires_mode_exclusion(&event
->attr
)) {
522 pr_debug("ARM performance counters do not support "
528 * Store the event encoding into the config_base field.
530 hwc
->config_base
|= (unsigned long)mapping
;
532 if (!hwc
->sample_period
) {
533 hwc
->sample_period
= armpmu
->max_period
;
534 hwc
->last_period
= hwc
->sample_period
;
535 local64_set(&hwc
->period_left
, hwc
->sample_period
);
539 if (event
->group_leader
!= event
) {
540 err
= validate_group(event
);
548 static int armpmu_event_init(struct perf_event
*event
)
551 atomic_t
*active_events
= &armpmu
->active_events
;
553 switch (event
->attr
.type
) {
555 case PERF_TYPE_HARDWARE
:
556 case PERF_TYPE_HW_CACHE
:
563 event
->destroy
= hw_perf_event_destroy
;
565 if (!atomic_inc_not_zero(active_events
)) {
566 mutex_lock(&armpmu
->reserve_mutex
);
567 if (atomic_read(active_events
) == 0)
568 err
= armpmu_reserve_hardware();
571 atomic_inc(active_events
);
572 mutex_unlock(&armpmu
->reserve_mutex
);
578 err
= __hw_perf_event_init(event
);
580 hw_perf_event_destroy(event
);
585 static void armpmu_enable(struct pmu
*pmu
)
587 /* Enable all of the perf events on hardware. */
588 int idx
, enabled
= 0;
589 struct cpu_hw_events
*cpuc
= armpmu
->get_hw_events();
591 for (idx
= 0; idx
< armpmu
->num_events
; ++idx
) {
592 struct perf_event
*event
= cpuc
->events
[idx
];
597 armpmu
->enable(&event
->hw
, idx
);
605 static void armpmu_disable(struct pmu
*pmu
)
610 static struct pmu pmu
= {
611 .pmu_enable
= armpmu_enable
,
612 .pmu_disable
= armpmu_disable
,
613 .event_init
= armpmu_event_init
,
616 .start
= armpmu_start
,
621 static void __init
armpmu_init(struct arm_pmu
*armpmu
)
623 atomic_set(&armpmu
->active_events
, 0);
624 mutex_init(&armpmu
->reserve_mutex
);
627 /* Include the PMU-specific implementations. */
628 #include "perf_event_xscale.c"
629 #include "perf_event_v6.c"
630 #include "perf_event_v7.c"
633 * Ensure the PMU has sane values out of reset.
634 * This requires SMP to be available, so exists as a separate initcall.
639 if (armpmu
&& armpmu
->reset
)
640 return on_each_cpu(armpmu
->reset
, NULL
, 1);
643 arch_initcall(armpmu_reset
);
646 * PMU platform driver and devicetree bindings.
648 static struct of_device_id armpmu_of_device_ids
[] = {
649 {.compatible
= "arm,cortex-a9-pmu"},
650 {.compatible
= "arm,cortex-a8-pmu"},
651 {.compatible
= "arm,arm1136-pmu"},
652 {.compatible
= "arm,arm1176-pmu"},
656 static struct platform_device_id armpmu_plat_device_ids
[] = {
661 static int __devinit
armpmu_device_probe(struct platform_device
*pdev
)
663 armpmu
->plat_device
= pdev
;
667 static struct platform_driver armpmu_driver
= {
670 .of_match_table
= armpmu_of_device_ids
,
672 .probe
= armpmu_device_probe
,
673 .id_table
= armpmu_plat_device_ids
,
676 static int __init
register_pmu_driver(void)
678 return platform_driver_register(&armpmu_driver
);
680 device_initcall(register_pmu_driver
);
682 static struct cpu_hw_events
*armpmu_get_cpu_events(void)
684 return &__get_cpu_var(cpu_hw_events
);
687 static void __init
cpu_pmu_init(struct arm_pmu
*armpmu
)
690 for_each_possible_cpu(cpu
) {
691 struct cpu_hw_events
*events
= &per_cpu(cpu_hw_events
, cpu
);
692 raw_spin_lock_init(&events
->pmu_lock
);
694 armpmu
->get_hw_events
= armpmu_get_cpu_events
;
695 armpmu
->type
= ARM_PMU_DEVICE_CPU
;
699 * CPU PMU identification and registration.
702 init_hw_perf_events(void)
704 unsigned long cpuid
= read_cpuid_id();
705 unsigned long implementor
= (cpuid
& 0xFF000000) >> 24;
706 unsigned long part_number
= (cpuid
& 0xFFF0);
709 if (0x41 == implementor
) {
710 switch (part_number
) {
711 case 0xB360: /* ARM1136 */
712 case 0xB560: /* ARM1156 */
713 case 0xB760: /* ARM1176 */
714 armpmu
= armv6pmu_init();
716 case 0xB020: /* ARM11mpcore */
717 armpmu
= armv6mpcore_pmu_init();
719 case 0xC080: /* Cortex-A8 */
720 armpmu
= armv7_a8_pmu_init();
722 case 0xC090: /* Cortex-A9 */
723 armpmu
= armv7_a9_pmu_init();
725 case 0xC050: /* Cortex-A5 */
726 armpmu
= armv7_a5_pmu_init();
728 case 0xC0F0: /* Cortex-A15 */
729 armpmu
= armv7_a15_pmu_init();
732 /* Intel CPUs [xscale]. */
733 } else if (0x69 == implementor
) {
734 part_number
= (cpuid
>> 13) & 0x7;
735 switch (part_number
) {
737 armpmu
= xscale1pmu_init();
740 armpmu
= xscale2pmu_init();
746 pr_info("enabled with %s PMU driver, %d counters available\n",
747 armpmu
->name
, armpmu
->num_events
);
748 cpu_pmu_init(armpmu
);
750 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
752 pr_info("no hardware support available\n");
757 early_initcall(init_hw_perf_events
);
760 * Callchain handling code.
764 * The registers we're interested in are at the end of the variable
765 * length saved register structure. The fp points at the end of this
766 * structure so the address of this struct is:
767 * (struct frame_tail *)(xxx->fp)-1
769 * This code has been adapted from the ARM OProfile support.
772 struct frame_tail __user
*fp
;
775 } __attribute__((packed
));
778 * Get the return address for a single stackframe and return a pointer to the
781 static struct frame_tail __user
*
782 user_backtrace(struct frame_tail __user
*tail
,
783 struct perf_callchain_entry
*entry
)
785 struct frame_tail buftail
;
787 /* Also check accessibility of one struct frame_tail beyond */
788 if (!access_ok(VERIFY_READ
, tail
, sizeof(buftail
)))
790 if (__copy_from_user_inatomic(&buftail
, tail
, sizeof(buftail
)))
793 perf_callchain_store(entry
, buftail
.lr
);
796 * Frame pointers should strictly progress back up the stack
797 * (towards higher addresses).
799 if (tail
+ 1 >= buftail
.fp
)
802 return buftail
.fp
- 1;
806 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
808 struct frame_tail __user
*tail
;
811 tail
= (struct frame_tail __user
*)regs
->ARM_fp
- 1;
813 while ((entry
->nr
< PERF_MAX_STACK_DEPTH
) &&
814 tail
&& !((unsigned long)tail
& 0x3))
815 tail
= user_backtrace(tail
, entry
);
819 * Gets called by walk_stackframe() for every stackframe. This will be called
820 * whist unwinding the stackframe and is like a subroutine return so we use
824 callchain_trace(struct stackframe
*fr
,
827 struct perf_callchain_entry
*entry
= data
;
828 perf_callchain_store(entry
, fr
->pc
);
833 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
835 struct stackframe fr
;
837 fr
.fp
= regs
->ARM_fp
;
838 fr
.sp
= regs
->ARM_sp
;
839 fr
.lr
= regs
->ARM_lr
;
840 fr
.pc
= regs
->ARM_pc
;
841 walk_stackframe(&fr
, callchain_trace
, entry
);