2 * linux/arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/export.h>
11 #include <linux/kernel.h>
12 #include <linux/stddef.h>
13 #include <linux/ioport.h>
14 #include <linux/delay.h>
15 #include <linux/utsname.h>
16 #include <linux/initrd.h>
17 #include <linux/console.h>
18 #include <linux/bootmem.h>
19 #include <linux/seq_file.h>
20 #include <linux/screen_info.h>
21 #include <linux/of_platform.h>
22 #include <linux/init.h>
23 #include <linux/kexec.h>
24 #include <linux/of_fdt.h>
25 #include <linux/cpu.h>
26 #include <linux/interrupt.h>
27 #include <linux/smp.h>
28 #include <linux/proc_fs.h>
29 #include <linux/memblock.h>
30 #include <linux/bug.h>
31 #include <linux/compiler.h>
32 #include <linux/sort.h>
34 #include <asm/unified.h>
37 #include <asm/cputype.h>
39 #include <asm/procinfo.h>
41 #include <asm/sections.h>
42 #include <asm/setup.h>
43 #include <asm/smp_plat.h>
44 #include <asm/mach-types.h>
45 #include <asm/cacheflush.h>
46 #include <asm/cachetype.h>
47 #include <asm/tlbflush.h>
50 #include <asm/mach/arch.h>
51 #include <asm/mach/irq.h>
52 #include <asm/mach/time.h>
53 #include <asm/system_info.h>
54 #include <asm/system_misc.h>
55 #include <asm/traps.h>
56 #include <asm/unwind.h>
57 #include <asm/memblock.h>
63 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
66 static int __init
fpe_setup(char *line
)
68 memcpy(fpe_type
, line
, 8);
72 __setup("fpe=", fpe_setup
);
75 extern void paging_init(const struct machine_desc
*desc
);
76 extern void early_paging_init(const struct machine_desc
*,
77 struct proc_info_list
*);
78 extern void sanity_check_meminfo(void);
79 extern enum reboot_mode reboot_mode
;
80 extern void setup_dma_zone(const struct machine_desc
*desc
);
82 unsigned int processor_id
;
83 EXPORT_SYMBOL(processor_id
);
84 unsigned int __machine_arch_type __read_mostly
;
85 EXPORT_SYMBOL(__machine_arch_type
);
86 unsigned int cacheid __read_mostly
;
87 EXPORT_SYMBOL(cacheid
);
89 unsigned int __atags_pointer __initdata
;
91 unsigned int system_rev
;
92 EXPORT_SYMBOL(system_rev
);
94 unsigned int system_serial_low
;
95 EXPORT_SYMBOL(system_serial_low
);
97 unsigned int system_serial_high
;
98 EXPORT_SYMBOL(system_serial_high
);
100 unsigned int elf_hwcap __read_mostly
;
101 EXPORT_SYMBOL(elf_hwcap
);
103 unsigned int elf_hwcap2 __read_mostly
;
104 EXPORT_SYMBOL(elf_hwcap2
);
108 struct processor processor __read_mostly
;
111 struct cpu_tlb_fns cpu_tlb __read_mostly
;
114 struct cpu_user_fns cpu_user __read_mostly
;
117 struct cpu_cache_fns cpu_cache __read_mostly
;
119 #ifdef CONFIG_OUTER_CACHE
120 struct outer_cache_fns outer_cache __read_mostly
;
121 EXPORT_SYMBOL(outer_cache
);
125 * Cached cpu_architecture() result for use by assembler code.
126 * C code should use the cpu_architecture() function instead of accessing this
129 int __cpu_architecture __read_mostly
= CPU_ARCH_UNKNOWN
;
135 } ____cacheline_aligned
;
137 #ifndef CONFIG_CPU_V7M
138 static struct stack stacks
[NR_CPUS
];
141 char elf_platform
[ELF_PLATFORM_SIZE
];
142 EXPORT_SYMBOL(elf_platform
);
144 static const char *cpu_name
;
145 static const char *machine_name
;
146 static char __initdata cmd_line
[COMMAND_LINE_SIZE
];
147 const struct machine_desc
*machine_desc __initdata
;
149 static union { char c
[4]; unsigned long l
; } endian_test __initdata
= { { 'l', '?', '?', 'b' } };
150 #define ENDIANNESS ((char)endian_test.l)
152 DEFINE_PER_CPU(struct cpuinfo_arm
, cpu_data
);
155 * Standard memory resources
157 static struct resource mem_res
[] = {
162 .flags
= IORESOURCE_MEM
165 .name
= "Kernel code",
168 .flags
= IORESOURCE_MEM
171 .name
= "Kernel data",
174 .flags
= IORESOURCE_MEM
178 #define video_ram mem_res[0]
179 #define kernel_code mem_res[1]
180 #define kernel_data mem_res[2]
182 static struct resource io_res
[] = {
187 .flags
= IORESOURCE_IO
| IORESOURCE_BUSY
193 .flags
= IORESOURCE_IO
| IORESOURCE_BUSY
199 .flags
= IORESOURCE_IO
| IORESOURCE_BUSY
203 #define lp0 io_res[0]
204 #define lp1 io_res[1]
205 #define lp2 io_res[2]
207 static const char *proc_arch
[] = {
227 #ifdef CONFIG_CPU_V7M
228 static int __get_cpu_architecture(void)
230 return CPU_ARCH_ARMv7M
;
233 static int __get_cpu_architecture(void)
237 if ((read_cpuid_id() & 0x0008f000) == 0) {
238 cpu_arch
= CPU_ARCH_UNKNOWN
;
239 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
240 cpu_arch
= (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T
: CPU_ARCH_ARMv3
;
241 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
242 cpu_arch
= (read_cpuid_id() >> 16) & 7;
244 cpu_arch
+= CPU_ARCH_ARMv3
;
245 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
248 /* Revised CPUID format. Read the Memory Model Feature
249 * Register 0 and check for VMSAv7 or PMSAv7 */
250 asm("mrc p15, 0, %0, c0, c1, 4"
252 if ((mmfr0
& 0x0000000f) >= 0x00000003 ||
253 (mmfr0
& 0x000000f0) >= 0x00000030)
254 cpu_arch
= CPU_ARCH_ARMv7
;
255 else if ((mmfr0
& 0x0000000f) == 0x00000002 ||
256 (mmfr0
& 0x000000f0) == 0x00000020)
257 cpu_arch
= CPU_ARCH_ARMv6
;
259 cpu_arch
= CPU_ARCH_UNKNOWN
;
261 cpu_arch
= CPU_ARCH_UNKNOWN
;
267 int __pure
cpu_architecture(void)
269 BUG_ON(__cpu_architecture
== CPU_ARCH_UNKNOWN
);
271 return __cpu_architecture
;
274 static int cpu_has_aliasing_icache(unsigned int arch
)
277 unsigned int id_reg
, num_sets
, line_size
;
279 /* PIPT caches never alias. */
280 if (icache_is_pipt())
283 /* arch specifies the register format */
286 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
287 : /* No output operands */
290 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
292 line_size
= 4 << ((id_reg
& 0x7) + 2);
293 num_sets
= ((id_reg
>> 13) & 0x7fff) + 1;
294 aliasing_icache
= (line_size
* num_sets
) > PAGE_SIZE
;
297 aliasing_icache
= read_cpuid_cachetype() & (1 << 11);
300 /* I-cache aliases will be handled by D-cache aliasing code */
304 return aliasing_icache
;
307 static void __init
cacheid_init(void)
309 unsigned int arch
= cpu_architecture();
311 if (arch
== CPU_ARCH_ARMv7M
) {
313 } else if (arch
>= CPU_ARCH_ARMv6
) {
314 unsigned int cachetype
= read_cpuid_cachetype();
315 if ((cachetype
& (7 << 29)) == 4 << 29) {
316 /* ARMv7 register format */
317 arch
= CPU_ARCH_ARMv7
;
318 cacheid
= CACHEID_VIPT_NONALIASING
;
319 switch (cachetype
& (3 << 14)) {
321 cacheid
|= CACHEID_ASID_TAGGED
;
324 cacheid
|= CACHEID_PIPT
;
328 arch
= CPU_ARCH_ARMv6
;
329 if (cachetype
& (1 << 23))
330 cacheid
= CACHEID_VIPT_ALIASING
;
332 cacheid
= CACHEID_VIPT_NONALIASING
;
334 if (cpu_has_aliasing_icache(arch
))
335 cacheid
|= CACHEID_VIPT_I_ALIASING
;
337 cacheid
= CACHEID_VIVT
;
340 pr_info("CPU: %s data cache, %s instruction cache\n",
341 cache_is_vivt() ? "VIVT" :
342 cache_is_vipt_aliasing() ? "VIPT aliasing" :
343 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
344 cache_is_vivt() ? "VIVT" :
345 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
346 icache_is_vipt_aliasing() ? "VIPT aliasing" :
347 icache_is_pipt() ? "PIPT" :
348 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
352 * These functions re-use the assembly code in head.S, which
353 * already provide the required functionality.
355 extern struct proc_info_list
*lookup_processor_type(unsigned int);
357 void __init
early_print(const char *str
, ...)
359 extern void printascii(const char *);
364 vsnprintf(buf
, sizeof(buf
), str
, ap
);
367 #ifdef CONFIG_DEBUG_LL
373 static void __init
cpuid_init_hwcaps(void)
375 unsigned int divide_instrs
, vmsa
;
377 if (cpu_architecture() < CPU_ARCH_ARMv7
)
380 divide_instrs
= (read_cpuid_ext(CPUID_EXT_ISAR0
) & 0x0f000000) >> 24;
382 switch (divide_instrs
) {
384 elf_hwcap
|= HWCAP_IDIVA
;
386 elf_hwcap
|= HWCAP_IDIVT
;
389 /* LPAE implies atomic ldrd/strd instructions */
390 vmsa
= (read_cpuid_ext(CPUID_EXT_MMFR0
) & 0xf) >> 0;
392 elf_hwcap
|= HWCAP_LPAE
;
395 static void __init
feat_v6_fixup(void)
397 int id
= read_cpuid_id();
399 if ((id
& 0xff0f0000) != 0x41070000)
403 * HWCAP_TLS is available only on 1136 r1p0 and later,
404 * see also kuser_get_tls_init.
406 if ((((id
>> 4) & 0xfff) == 0xb36) && (((id
>> 20) & 3) == 0))
407 elf_hwcap
&= ~HWCAP_TLS
;
411 * cpu_init - initialise one CPU.
413 * cpu_init sets up the per-CPU stacks.
415 void notrace
cpu_init(void)
417 #ifndef CONFIG_CPU_V7M
418 unsigned int cpu
= smp_processor_id();
419 struct stack
*stk
= &stacks
[cpu
];
421 if (cpu
>= NR_CPUS
) {
422 pr_crit("CPU%u: bad primary CPU number\n", cpu
);
427 * This only works on resume and secondary cores. For booting on the
428 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
430 set_my_cpu_offset(per_cpu_offset(cpu
));
435 * Define the placement constraint for the inline asm directive below.
436 * In Thumb-2, msr with an immediate value is not allowed.
438 #ifdef CONFIG_THUMB2_KERNEL
445 * setup stacks for re-entrant exception handlers
449 "add r14, %0, %2\n\t"
452 "add r14, %0, %4\n\t"
455 "add r14, %0, %6\n\t"
460 PLC (PSR_F_BIT
| PSR_I_BIT
| IRQ_MODE
),
461 "I" (offsetof(struct stack
, irq
[0])),
462 PLC (PSR_F_BIT
| PSR_I_BIT
| ABT_MODE
),
463 "I" (offsetof(struct stack
, abt
[0])),
464 PLC (PSR_F_BIT
| PSR_I_BIT
| UND_MODE
),
465 "I" (offsetof(struct stack
, und
[0])),
466 PLC (PSR_F_BIT
| PSR_I_BIT
| SVC_MODE
)
471 u32 __cpu_logical_map
[NR_CPUS
] = { [0 ... NR_CPUS
-1] = MPIDR_INVALID
};
473 void __init
smp_setup_processor_id(void)
476 u32 mpidr
= is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK
: 0;
477 u32 cpu
= MPIDR_AFFINITY_LEVEL(mpidr
, 0);
479 cpu_logical_map(0) = cpu
;
480 for (i
= 1; i
< nr_cpu_ids
; ++i
)
481 cpu_logical_map(i
) = i
== cpu
? 0 : i
;
484 * clear __my_cpu_offset on boot CPU to avoid hang caused by
485 * using percpu variable early, for example, lockdep will
486 * access percpu variable inside lock_release
488 set_my_cpu_offset(0);
490 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr
);
493 struct mpidr_hash mpidr_hash
;
496 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
497 * level in order to build a linear index from an
498 * MPIDR value. Resulting algorithm is a collision
499 * free hash carried out through shifting and ORing
501 static void __init
smp_build_mpidr_hash(void)
504 u32 fs
[3], bits
[3], ls
, mask
= 0;
506 * Pre-scan the list of MPIDRS and filter out bits that do
507 * not contribute to affinity levels, ie they never toggle.
509 for_each_possible_cpu(i
)
510 mask
|= (cpu_logical_map(i
) ^ cpu_logical_map(0));
511 pr_debug("mask of set bits 0x%x\n", mask
);
513 * Find and stash the last and first bit set at all affinity levels to
514 * check how many bits are required to represent them.
516 for (i
= 0; i
< 3; i
++) {
517 affinity
= MPIDR_AFFINITY_LEVEL(mask
, i
);
519 * Find the MSB bit and LSB bits position
520 * to determine how many bits are required
521 * to express the affinity level.
524 fs
[i
] = affinity
? ffs(affinity
) - 1 : 0;
525 bits
[i
] = ls
- fs
[i
];
528 * An index can be created from the MPIDR by isolating the
529 * significant bits at each affinity level and by shifting
530 * them in order to compress the 24 bits values space to a
531 * compressed set of values. This is equivalent to hashing
532 * the MPIDR through shifting and ORing. It is a collision free
533 * hash though not minimal since some levels might contain a number
534 * of CPUs that is not an exact power of 2 and their bit
535 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
537 mpidr_hash
.shift_aff
[0] = fs
[0];
538 mpidr_hash
.shift_aff
[1] = MPIDR_LEVEL_BITS
+ fs
[1] - bits
[0];
539 mpidr_hash
.shift_aff
[2] = 2*MPIDR_LEVEL_BITS
+ fs
[2] -
541 mpidr_hash
.mask
= mask
;
542 mpidr_hash
.bits
= bits
[2] + bits
[1] + bits
[0];
543 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
544 mpidr_hash
.shift_aff
[0],
545 mpidr_hash
.shift_aff
[1],
546 mpidr_hash
.shift_aff
[2],
550 * 4x is an arbitrary value used to warn on a hash table much bigger
551 * than expected on most systems.
553 if (mpidr_hash_size() > 4 * num_possible_cpus())
554 pr_warn("Large number of MPIDR hash buckets detected\n");
555 sync_cache_w(&mpidr_hash
);
559 static void __init
setup_processor(void)
561 struct proc_info_list
*list
;
564 * locate processor in the list of supported processor
565 * types. The linker builds this table for us from the
566 * entries in arch/arm/mm/proc-*.S
568 list
= lookup_processor_type(read_cpuid_id());
570 pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
575 cpu_name
= list
->cpu_name
;
576 __cpu_architecture
= __get_cpu_architecture();
579 processor
= *list
->proc
;
582 cpu_tlb
= *list
->tlb
;
585 cpu_user
= *list
->user
;
588 cpu_cache
= *list
->cache
;
591 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
592 cpu_name
, read_cpuid_id(), read_cpuid_id() & 15,
593 proc_arch
[cpu_architecture()], cr_alignment
);
595 snprintf(init_utsname()->machine
, __NEW_UTS_LEN
+ 1, "%s%c",
596 list
->arch_name
, ENDIANNESS
);
597 snprintf(elf_platform
, ELF_PLATFORM_SIZE
, "%s%c",
598 list
->elf_name
, ENDIANNESS
);
599 elf_hwcap
= list
->elf_hwcap
;
603 #ifndef CONFIG_ARM_THUMB
604 elf_hwcap
&= ~(HWCAP_THUMB
| HWCAP_IDIVT
);
607 erratum_a15_798181_init();
615 void __init
dump_machine_table(void)
617 const struct machine_desc
*p
;
619 early_print("Available machine support:\n\nID (hex)\tNAME\n");
620 for_each_machine_desc(p
)
621 early_print("%08x\t%s\n", p
->nr
, p
->name
);
623 early_print("\nPlease check your kernel config and/or bootloader.\n");
626 /* can't use cpu_relax() here as it may require MMU setup */;
629 int __init
arm_add_memory(u64 start
, u64 size
)
631 struct membank
*bank
= &meminfo
.bank
[meminfo
.nr_banks
];
634 if (meminfo
.nr_banks
>= NR_BANKS
) {
635 pr_crit("NR_BANKS too low, ignoring memory at 0x%08llx\n",
641 * Ensure that start/size are aligned to a page boundary.
642 * Size is appropriately rounded down, start is rounded up.
644 size
-= start
& ~PAGE_MASK
;
645 aligned_start
= PAGE_ALIGN(start
);
647 #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
648 if (aligned_start
> ULONG_MAX
) {
649 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
654 if (aligned_start
+ size
> ULONG_MAX
) {
655 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
658 * To ensure bank->start + bank->size is representable in
659 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
660 * This means we lose a page after masking.
662 size
= ULONG_MAX
- aligned_start
;
666 if (aligned_start
< PHYS_OFFSET
) {
667 if (aligned_start
+ size
<= PHYS_OFFSET
) {
668 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
669 aligned_start
, aligned_start
+ size
);
673 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
674 aligned_start
, (u64
)PHYS_OFFSET
);
676 size
-= PHYS_OFFSET
- aligned_start
;
677 aligned_start
= PHYS_OFFSET
;
680 bank
->start
= aligned_start
;
681 bank
->size
= size
& ~(phys_addr_t
)(PAGE_SIZE
- 1);
684 * Check whether this memory region has non-zero size or
685 * invalid node number.
695 * Pick out the memory size. We look for mem=size@start,
696 * where start and size are "size[KkMm]"
698 static int __init
early_mem(char *p
)
700 static int usermem __initdata
= 0;
706 * If the user specifies memory size, we
707 * blow away any automatically generated
712 meminfo
.nr_banks
= 0;
716 size
= memparse(p
, &endp
);
718 start
= memparse(endp
+ 1, NULL
);
720 arm_add_memory(start
, size
);
724 early_param("mem", early_mem
);
726 static void __init
request_standard_resources(const struct machine_desc
*mdesc
)
728 struct memblock_region
*region
;
729 struct resource
*res
;
731 kernel_code
.start
= virt_to_phys(_text
);
732 kernel_code
.end
= virt_to_phys(_etext
- 1);
733 kernel_data
.start
= virt_to_phys(_sdata
);
734 kernel_data
.end
= virt_to_phys(_end
- 1);
736 for_each_memblock(memory
, region
) {
737 res
= memblock_virt_alloc_low(sizeof(*res
), 0);
738 res
->name
= "System RAM";
739 res
->start
= __pfn_to_phys(memblock_region_memory_base_pfn(region
));
740 res
->end
= __pfn_to_phys(memblock_region_memory_end_pfn(region
)) - 1;
741 res
->flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
743 request_resource(&iomem_resource
, res
);
745 if (kernel_code
.start
>= res
->start
&&
746 kernel_code
.end
<= res
->end
)
747 request_resource(res
, &kernel_code
);
748 if (kernel_data
.start
>= res
->start
&&
749 kernel_data
.end
<= res
->end
)
750 request_resource(res
, &kernel_data
);
753 if (mdesc
->video_start
) {
754 video_ram
.start
= mdesc
->video_start
;
755 video_ram
.end
= mdesc
->video_end
;
756 request_resource(&iomem_resource
, &video_ram
);
760 * Some machines don't have the possibility of ever
761 * possessing lp0, lp1 or lp2
763 if (mdesc
->reserve_lp0
)
764 request_resource(&ioport_resource
, &lp0
);
765 if (mdesc
->reserve_lp1
)
766 request_resource(&ioport_resource
, &lp1
);
767 if (mdesc
->reserve_lp2
)
768 request_resource(&ioport_resource
, &lp2
);
771 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
772 struct screen_info screen_info
= {
773 .orig_video_lines
= 30,
774 .orig_video_cols
= 80,
775 .orig_video_mode
= 0,
776 .orig_video_ega_bx
= 0,
777 .orig_video_isVGA
= 1,
778 .orig_video_points
= 8
782 static int __init
customize_machine(void)
785 * customizes platform devices, or adds new ones
786 * On DT based machines, we fall back to populating the
787 * machine from the device tree, if no callback is provided,
788 * otherwise we would always need an init_machine callback.
790 if (machine_desc
->init_machine
)
791 machine_desc
->init_machine();
794 of_platform_populate(NULL
, of_default_bus_match_table
,
799 arch_initcall(customize_machine
);
801 static int __init
init_machine_late(void)
803 if (machine_desc
->init_late
)
804 machine_desc
->init_late();
807 late_initcall(init_machine_late
);
810 static inline unsigned long long get_total_mem(void)
814 total
= max_low_pfn
- min_low_pfn
;
815 return total
<< PAGE_SHIFT
;
819 * reserve_crashkernel() - reserves memory are for crash kernel
821 * This function reserves memory area given in "crashkernel=" kernel command
822 * line parameter. The memory reserved is used by a dump capture kernel when
823 * primary kernel is crashing.
825 static void __init
reserve_crashkernel(void)
827 unsigned long long crash_size
, crash_base
;
828 unsigned long long total_mem
;
831 total_mem
= get_total_mem();
832 ret
= parse_crashkernel(boot_command_line
, total_mem
,
833 &crash_size
, &crash_base
);
837 ret
= memblock_reserve(crash_base
, crash_size
);
839 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
840 (unsigned long)crash_base
);
844 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
845 (unsigned long)(crash_size
>> 20),
846 (unsigned long)(crash_base
>> 20),
847 (unsigned long)(total_mem
>> 20));
849 crashk_res
.start
= crash_base
;
850 crashk_res
.end
= crash_base
+ crash_size
- 1;
851 insert_resource(&iomem_resource
, &crashk_res
);
854 static inline void reserve_crashkernel(void) {}
855 #endif /* CONFIG_KEXEC */
857 static int __init
meminfo_cmp(const void *_a
, const void *_b
)
859 const struct membank
*a
= _a
, *b
= _b
;
860 long cmp
= bank_pfn_start(a
) - bank_pfn_start(b
);
861 return cmp
< 0 ? -1 : cmp
> 0 ? 1 : 0;
864 void __init
hyp_mode_check(void)
866 #ifdef CONFIG_ARM_VIRT_EXT
869 if (is_hyp_mode_available()) {
870 pr_info("CPU: All CPU(s) started in HYP mode.\n");
871 pr_info("CPU: Virtualization extensions available.\n");
872 } else if (is_hyp_mode_mismatched()) {
873 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
874 __boot_cpu_mode
& MODE_MASK
);
875 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
877 pr_info("CPU: All CPU(s) started in SVC mode.\n");
881 void __init
setup_arch(char **cmdline_p
)
883 const struct machine_desc
*mdesc
;
886 mdesc
= setup_machine_fdt(__atags_pointer
);
888 mdesc
= setup_machine_tags(__atags_pointer
, __machine_arch_type
);
889 machine_desc
= mdesc
;
890 machine_name
= mdesc
->name
;
892 if (mdesc
->reboot_mode
!= REBOOT_HARD
)
893 reboot_mode
= mdesc
->reboot_mode
;
895 init_mm
.start_code
= (unsigned long) _text
;
896 init_mm
.end_code
= (unsigned long) _etext
;
897 init_mm
.end_data
= (unsigned long) _edata
;
898 init_mm
.brk
= (unsigned long) _end
;
900 /* populate cmd_line too for later use, preserving boot_command_line */
901 strlcpy(cmd_line
, boot_command_line
, COMMAND_LINE_SIZE
);
902 *cmdline_p
= cmd_line
;
906 sort(&meminfo
.bank
, meminfo
.nr_banks
, sizeof(meminfo
.bank
[0]), meminfo_cmp
, NULL
);
908 early_paging_init(mdesc
, lookup_processor_type(read_cpuid_id()));
909 setup_dma_zone(mdesc
);
910 sanity_check_meminfo();
911 arm_memblock_init(&meminfo
, mdesc
);
914 request_standard_resources(mdesc
);
917 arm_pm_restart
= mdesc
->restart
;
919 unflatten_device_tree();
921 arm_dt_init_cpu_maps();
925 if (!mdesc
->smp_init
|| !mdesc
->smp_init()) {
926 if (psci_smp_available())
927 smp_set_ops(&psci_smp_ops
);
929 smp_set_ops(mdesc
->smp
);
932 smp_build_mpidr_hash();
939 reserve_crashkernel();
941 #ifdef CONFIG_MULTI_IRQ_HANDLER
942 handle_arch_irq
= mdesc
->handle_irq
;
946 #if defined(CONFIG_VGA_CONSOLE)
947 conswitchp
= &vga_con
;
948 #elif defined(CONFIG_DUMMY_CONSOLE)
949 conswitchp
= &dummy_con
;
953 if (mdesc
->init_early
)
958 static int __init
topology_init(void)
962 for_each_possible_cpu(cpu
) {
963 struct cpuinfo_arm
*cpuinfo
= &per_cpu(cpu_data
, cpu
);
964 cpuinfo
->cpu
.hotpluggable
= 1;
965 register_cpu(&cpuinfo
->cpu
, cpu
);
970 subsys_initcall(topology_init
);
972 #ifdef CONFIG_HAVE_PROC_CPU
973 static int __init
proc_cpu_init(void)
975 struct proc_dir_entry
*res
;
977 res
= proc_mkdir("cpu", NULL
);
982 fs_initcall(proc_cpu_init
);
985 static const char *hwcap_str
[] = {
1011 static const char *hwcap2_str
[] = {
1015 static int c_show(struct seq_file
*m
, void *v
)
1020 for_each_online_cpu(i
) {
1022 * glibc reads /proc/cpuinfo to determine the number of
1023 * online processors, looking for lines beginning with
1024 * "processor". Give glibc what it expects.
1026 seq_printf(m
, "processor\t: %d\n", i
);
1027 cpuid
= is_smp() ? per_cpu(cpu_data
, i
).cpuid
: read_cpuid_id();
1028 seq_printf(m
, "model name\t: %s rev %d (%s)\n",
1029 cpu_name
, cpuid
& 15, elf_platform
);
1031 /* dump out the processor features */
1032 seq_puts(m
, "Features\t: ");
1034 for (j
= 0; hwcap_str
[j
]; j
++)
1035 if (elf_hwcap
& (1 << j
))
1036 seq_printf(m
, "%s ", hwcap_str
[j
]);
1038 for (j
= 0; hwcap2_str
[j
]; j
++)
1039 if (elf_hwcap2
& (1 << j
))
1040 seq_printf(m
, "%s ", hwcap2_str
[j
]);
1042 seq_printf(m
, "\nCPU implementer\t: 0x%02x\n", cpuid
>> 24);
1043 seq_printf(m
, "CPU architecture: %s\n",
1044 proc_arch
[cpu_architecture()]);
1046 if ((cpuid
& 0x0008f000) == 0x00000000) {
1048 seq_printf(m
, "CPU part\t: %07x\n", cpuid
>> 4);
1050 if ((cpuid
& 0x0008f000) == 0x00007000) {
1052 seq_printf(m
, "CPU variant\t: 0x%02x\n",
1053 (cpuid
>> 16) & 127);
1056 seq_printf(m
, "CPU variant\t: 0x%x\n",
1057 (cpuid
>> 20) & 15);
1059 seq_printf(m
, "CPU part\t: 0x%03x\n",
1060 (cpuid
>> 4) & 0xfff);
1062 seq_printf(m
, "CPU revision\t: %d\n\n", cpuid
& 15);
1065 seq_printf(m
, "Hardware\t: %s\n", machine_name
);
1066 seq_printf(m
, "Revision\t: %04x\n", system_rev
);
1067 seq_printf(m
, "Serial\t\t: %08x%08x\n",
1068 system_serial_high
, system_serial_low
);
1073 static void *c_start(struct seq_file
*m
, loff_t
*pos
)
1075 return *pos
< 1 ? (void *)1 : NULL
;
1078 static void *c_next(struct seq_file
*m
, void *v
, loff_t
*pos
)
1084 static void c_stop(struct seq_file
*m
, void *v
)
1088 const struct seq_operations cpuinfo_op
= {