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2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 #include <linux/kvm_host.h>
21 #include <asm/kvm_arm.h>
22 #include <asm/kvm_emulate.h>
23 #include <asm/opcodes.h>
24 #include <trace/events/kvm.h>
28 #define VCPU_NR_MODES 6
29 #define VCPU_REG_OFFSET_USR 0
30 #define VCPU_REG_OFFSET_FIQ 1
31 #define VCPU_REG_OFFSET_IRQ 2
32 #define VCPU_REG_OFFSET_SVC 3
33 #define VCPU_REG_OFFSET_ABT 4
34 #define VCPU_REG_OFFSET_UND 5
35 #define REG_OFFSET(_reg) \
36 (offsetof(struct kvm_regs, _reg) / sizeof(u32))
38 #define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
40 static const unsigned long vcpu_reg_offsets
[VCPU_NR_MODES
][15] = {
41 /* USR/SYS Registers */
42 [VCPU_REG_OFFSET_USR
] = {
43 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
44 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
45 USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
46 USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
47 USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
51 [VCPU_REG_OFFSET_FIQ
] = {
52 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
53 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
54 USR_REG_OFFSET(6), USR_REG_OFFSET(7),
55 REG_OFFSET(fiq_regs
[0]), /* r8 */
56 REG_OFFSET(fiq_regs
[1]), /* r9 */
57 REG_OFFSET(fiq_regs
[2]), /* r10 */
58 REG_OFFSET(fiq_regs
[3]), /* r11 */
59 REG_OFFSET(fiq_regs
[4]), /* r12 */
60 REG_OFFSET(fiq_regs
[5]), /* r13 */
61 REG_OFFSET(fiq_regs
[6]), /* r14 */
65 [VCPU_REG_OFFSET_IRQ
] = {
66 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
67 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
68 USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
69 USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
71 REG_OFFSET(irq_regs
[0]), /* r13 */
72 REG_OFFSET(irq_regs
[1]), /* r14 */
76 [VCPU_REG_OFFSET_SVC
] = {
77 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
78 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
79 USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
80 USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
82 REG_OFFSET(svc_regs
[0]), /* r13 */
83 REG_OFFSET(svc_regs
[1]), /* r14 */
87 [VCPU_REG_OFFSET_ABT
] = {
88 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
89 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
90 USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
91 USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
93 REG_OFFSET(abt_regs
[0]), /* r13 */
94 REG_OFFSET(abt_regs
[1]), /* r14 */
98 [VCPU_REG_OFFSET_UND
] = {
99 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
100 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
101 USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
102 USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
104 REG_OFFSET(und_regs
[0]), /* r13 */
105 REG_OFFSET(und_regs
[1]), /* r14 */
110 * Return a pointer to the register number valid in the current mode of
113 unsigned long *vcpu_reg(struct kvm_vcpu
*vcpu
, u8 reg_num
)
115 unsigned long *reg_array
= (unsigned long *)&vcpu
->arch
.regs
;
116 unsigned long mode
= *vcpu_cpsr(vcpu
) & MODE_MASK
;
119 case USR_MODE
...SVC_MODE
:
120 mode
&= ~MODE32_BIT
; /* 0 ... 3 */
124 mode
= VCPU_REG_OFFSET_ABT
;
128 mode
= VCPU_REG_OFFSET_UND
;
132 mode
= VCPU_REG_OFFSET_USR
;
139 return reg_array
+ vcpu_reg_offsets
[mode
][reg_num
];
143 * Return the SPSR for the current mode of the virtual CPU.
145 unsigned long *vcpu_spsr(struct kvm_vcpu
*vcpu
)
147 unsigned long mode
= *vcpu_cpsr(vcpu
) & MODE_MASK
;
150 return &vcpu
->arch
.regs
.KVM_ARM_SVC_spsr
;
152 return &vcpu
->arch
.regs
.KVM_ARM_ABT_spsr
;
154 return &vcpu
->arch
.regs
.KVM_ARM_UND_spsr
;
156 return &vcpu
->arch
.regs
.KVM_ARM_IRQ_spsr
;
158 return &vcpu
->arch
.regs
.KVM_ARM_FIQ_spsr
;
165 * A conditional instruction is allowed to trap, even though it
166 * wouldn't be executed. So let's re-implement the hardware, in
169 bool kvm_condition_valid(struct kvm_vcpu
*vcpu
)
171 unsigned long cpsr
, cond
, insn
;
174 * Exception Code 0 can only happen if we set HCR.TGE to 1, to
175 * catch undefined instructions, and then we won't get past
176 * the arm_exit_handlers test anyway.
178 BUG_ON(!kvm_vcpu_trap_get_class(vcpu
));
180 /* Top two bits non-zero? Unconditional. */
181 if (kvm_vcpu_get_hsr(vcpu
) >> 30)
184 cpsr
= *vcpu_cpsr(vcpu
);
186 /* Is condition field valid? */
187 if ((kvm_vcpu_get_hsr(vcpu
) & HSR_CV
) >> HSR_CV_SHIFT
)
188 cond
= (kvm_vcpu_get_hsr(vcpu
) & HSR_COND
) >> HSR_COND_SHIFT
;
190 /* This can happen in Thumb mode: examine IT state. */
193 it
= ((cpsr
>> 8) & 0xFC) | ((cpsr
>> 25) & 0x3);
195 /* it == 0 => unconditional. */
199 /* The cond for this insn works out as the top 4 bits. */
203 /* Shift makes it look like an ARM-mode instruction */
205 return arm_check_condition(insn
, cpsr
) != ARM_OPCODE_CONDTEST_FAIL
;
209 * adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
210 * @vcpu: The VCPU pointer
212 * When exceptions occur while instructions are executed in Thumb IF-THEN
213 * blocks, the ITSTATE field of the CPSR is not advanved (updated), so we have
214 * to do this little bit of work manually. The fields map like this:
216 * IT[7:0] -> CPSR[26:25],CPSR[15:10]
218 static void kvm_adjust_itstate(struct kvm_vcpu
*vcpu
)
220 unsigned long itbits
, cond
;
221 unsigned long cpsr
= *vcpu_cpsr(vcpu
);
222 bool is_arm
= !(cpsr
& PSR_T_BIT
);
224 BUG_ON(is_arm
&& (cpsr
& PSR_IT_MASK
));
226 if (!(cpsr
& PSR_IT_MASK
))
229 cond
= (cpsr
& 0xe000) >> 13;
230 itbits
= (cpsr
& 0x1c00) >> (10 - 2);
231 itbits
|= (cpsr
& (0x3 << 25)) >> 25;
233 /* Perform ITAdvance (see page A-52 in ARM DDI 0406C) */
234 if ((itbits
& 0x7) == 0)
237 itbits
= (itbits
<< 1) & 0x1f;
239 cpsr
&= ~PSR_IT_MASK
;
241 cpsr
|= (itbits
& 0x1c) << (10 - 2);
242 cpsr
|= (itbits
& 0x3) << 25;
243 *vcpu_cpsr(vcpu
) = cpsr
;
247 * kvm_skip_instr - skip a trapped instruction and proceed to the next
248 * @vcpu: The vcpu pointer
250 void kvm_skip_instr(struct kvm_vcpu
*vcpu
, bool is_wide_instr
)
254 is_thumb
= !!(*vcpu_cpsr(vcpu
) & PSR_T_BIT
);
255 if (is_thumb
&& !is_wide_instr
)
259 kvm_adjust_itstate(vcpu
);
263 /******************************************************************************
264 * Inject exceptions into the guest
267 static u32
exc_vector_base(struct kvm_vcpu
*vcpu
)
269 u32 sctlr
= vcpu
->arch
.cp15
[c1_SCTLR
];
270 u32 vbar
= vcpu
->arch
.cp15
[c12_VBAR
];
274 else /* always have security exceptions */
279 * Switch to an exception mode, updating both CPSR and SPSR. Follow
280 * the logic described in AArch32.EnterMode() from the ARMv8 ARM.
282 static void kvm_update_psr(struct kvm_vcpu
*vcpu
, unsigned long mode
)
284 unsigned long cpsr
= *vcpu_cpsr(vcpu
);
285 u32 sctlr
= vcpu
->arch
.cp15
[c1_SCTLR
];
287 *vcpu_cpsr(vcpu
) = (cpsr
& ~MODE_MASK
) | mode
;
291 *vcpu_cpsr(vcpu
) |= PSR_F_BIT
;
295 *vcpu_cpsr(vcpu
) |= PSR_A_BIT
;
298 *vcpu_cpsr(vcpu
) |= PSR_I_BIT
;
301 *vcpu_cpsr(vcpu
) &= ~(PSR_IT_MASK
| PSR_J_BIT
| PSR_E_BIT
| PSR_T_BIT
);
303 if (sctlr
& SCTLR_TE
)
304 *vcpu_cpsr(vcpu
) |= PSR_T_BIT
;
305 if (sctlr
& SCTLR_EE
)
306 *vcpu_cpsr(vcpu
) |= PSR_E_BIT
;
308 /* Note: These now point to the mode banked copies */
309 *vcpu_spsr(vcpu
) = cpsr
;
313 * kvm_inject_undefined - inject an undefined exception into the guest
314 * @vcpu: The VCPU to receive the undefined exception
316 * It is assumed that this code is called from the VCPU thread and that the
317 * VCPU therefore is not currently executing guest code.
319 * Modelled after TakeUndefInstrException() pseudocode.
321 void kvm_inject_undefined(struct kvm_vcpu
*vcpu
)
323 unsigned long cpsr
= *vcpu_cpsr(vcpu
);
324 bool is_thumb
= (cpsr
& PSR_T_BIT
);
326 u32 return_offset
= (is_thumb
) ? 2 : 4;
328 kvm_update_psr(vcpu
, UND_MODE
);
329 *vcpu_reg(vcpu
, 14) = *vcpu_pc(vcpu
) - return_offset
;
331 /* Branch to exception vector */
332 *vcpu_pc(vcpu
) = exc_vector_base(vcpu
) + vect_offset
;
336 * Modelled after TakeDataAbortException() and TakePrefetchAbortException
339 static void inject_abt(struct kvm_vcpu
*vcpu
, bool is_pabt
, unsigned long addr
)
341 unsigned long cpsr
= *vcpu_cpsr(vcpu
);
342 bool is_thumb
= (cpsr
& PSR_T_BIT
);
344 u32 return_offset
= (is_thumb
) ? 4 : 0;
347 kvm_update_psr(vcpu
, ABT_MODE
);
348 *vcpu_reg(vcpu
, 14) = *vcpu_pc(vcpu
) + return_offset
;
355 /* Branch to exception vector */
356 *vcpu_pc(vcpu
) = exc_vector_base(vcpu
) + vect_offset
;
359 /* Set IFAR and IFSR */
360 vcpu
->arch
.cp15
[c6_IFAR
] = addr
;
361 is_lpae
= (vcpu
->arch
.cp15
[c2_TTBCR
] >> 31);
362 /* Always give debug fault for now - should give guest a clue */
364 vcpu
->arch
.cp15
[c5_IFSR
] = 1 << 9 | 0x22;
366 vcpu
->arch
.cp15
[c5_IFSR
] = 2;
368 /* Set DFAR and DFSR */
369 vcpu
->arch
.cp15
[c6_DFAR
] = addr
;
370 is_lpae
= (vcpu
->arch
.cp15
[c2_TTBCR
] >> 31);
371 /* Always give debug fault for now - should give guest a clue */
373 vcpu
->arch
.cp15
[c5_DFSR
] = 1 << 9 | 0x22;
375 vcpu
->arch
.cp15
[c5_DFSR
] = 2;
381 * kvm_inject_dabt - inject a data abort into the guest
382 * @vcpu: The VCPU to receive the undefined exception
383 * @addr: The address to report in the DFAR
385 * It is assumed that this code is called from the VCPU thread and that the
386 * VCPU therefore is not currently executing guest code.
388 void kvm_inject_dabt(struct kvm_vcpu
*vcpu
, unsigned long addr
)
390 inject_abt(vcpu
, false, addr
);
394 * kvm_inject_pabt - inject a prefetch abort into the guest
395 * @vcpu: The VCPU to receive the undefined exception
396 * @addr: The address to report in the DFAR
398 * It is assumed that this code is called from the VCPU thread and that the
399 * VCPU therefore is not currently executing guest code.
401 void kvm_inject_pabt(struct kvm_vcpu
*vcpu
, unsigned long addr
)
403 inject_abt(vcpu
, true, addr
);