arch/arm/kvm/hyp/switch.c

   1 /*
   2  * Copyright (C) 2015 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <asm/kvm_asm.h>
  19 #include <asm/kvm_hyp.h>
  20
  21 __asm__(".arch_extension     virt");
  22
  23 /*
  24  * Activate the traps, saving the host's fpexc register before
  25  * overwriting it. We'll restore it on VM exit.
  26  */
  27 static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu, u32 *fpexc_host)
  28 {
  29         u32 val;
  30
  31         /*
  32          * We are about to set HCPTR.TCP10/11 to trap all floating point
  33          * register accesses to HYP, however, the ARM ARM clearly states that
  34          * traps are only taken to HYP if the operation would not otherwise
  35          * trap to SVC.  Therefore, always make sure that for 32-bit guests,
  36          * we set FPEXC.EN to prevent traps to SVC, when setting the TCP bits.
  37          */
  38         val = read_sysreg(VFP_FPEXC);
  39         *fpexc_host = val;
  40         if (!(val & FPEXC_EN)) {
  41                 write_sysreg(val | FPEXC_EN, VFP_FPEXC);
  42                 isb();
  43         }
  44
  45         write_sysreg(vcpu->arch.hcr | vcpu->arch.irq_lines, HCR);
  46         /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
  47         write_sysreg(HSTR_T(15), HSTR);
  48         write_sysreg(HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11), HCPTR);
  49         val = read_sysreg(HDCR);
  50         write_sysreg(val | HDCR_TPM | HDCR_TPMCR, HDCR);
  51 }
  52
  53 static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
  54 {
  55         u32 val;
  56
  57         /*
  58          * If we pended a virtual abort, preserve it until it gets
  59          * cleared. See B1.9.9 (Virtual Abort exception) for details,
  60          * but the crucial bit is the zeroing of HCR.VA in the
  61          * pseudocode.
  62          */
  63         if (vcpu->arch.hcr & HCR_VA)
  64                 vcpu->arch.hcr = read_sysreg(HCR);
  65
  66         write_sysreg(0, HCR);
  67         write_sysreg(0, HSTR);
  68         val = read_sysreg(HDCR);
  69         write_sysreg(val & ~(HDCR_TPM | HDCR_TPMCR), HDCR);
  70         write_sysreg(0, HCPTR);
  71 }
  72
  73 static void __hyp_text __activate_vm(struct kvm_vcpu *vcpu)
  74 {
  75         struct kvm *kvm = kern_hyp_va(vcpu->kvm);
  76         write_sysreg(kvm->arch.vttbr, VTTBR);
  77         write_sysreg(vcpu->arch.midr, VPIDR);
  78 }
  79
  80 static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
  81 {
  82         write_sysreg(0, VTTBR);
  83         write_sysreg(read_sysreg(MIDR), VPIDR);
  84 }
  85
  86 static void __hyp_text __vgic_save_state(struct kvm_vcpu *vcpu)
  87 {
  88         __vgic_v2_save_state(vcpu);
  89 }
  90
  91 static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
  92 {
  93         __vgic_v2_restore_state(vcpu);
  94 }
  95
  96 static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
  97 {
  98         u32 hsr = read_sysreg(HSR);
  99         u8 ec = hsr >> HSR_EC_SHIFT;
 100         u32 hpfar, far;
 101
 102         vcpu->arch.fault.hsr = hsr;
 103
 104         if (ec == HSR_EC_IABT)
 105                 far = read_sysreg(HIFAR);
 106         else if (ec == HSR_EC_DABT)
 107                 far = read_sysreg(HDFAR);
 108         else
 109                 return true;
 110
 111         /*
 112          * B3.13.5 Reporting exceptions taken to the Non-secure PL2 mode:
 113          *
 114          * Abort on the stage 2 translation for a memory access from a
 115          * Non-secure PL1 or PL0 mode:
 116          *
 117          * For any Access flag fault or Translation fault, and also for any
 118          * Permission fault on the stage 2 translation of a memory access
 119          * made as part of a translation table walk for a stage 1 translation,
 120          * the HPFAR holds the IPA that caused the fault. Otherwise, the HPFAR
 121          * is UNKNOWN.
 122          */
 123         if (!(hsr & HSR_DABT_S1PTW) && (hsr & HSR_FSC_TYPE) == FSC_PERM) {
 124                 u64 par, tmp;
 125
 126                 par = read_sysreg(PAR);
 127                 write_sysreg(far, ATS1CPR);
 128                 isb();
 129
 130                 tmp = read_sysreg(PAR);
 131                 write_sysreg(par, PAR);
 132
 133                 if (unlikely(tmp & 1))
 134                         return false; /* Translation failed, back to guest */
 135
 136                 hpfar = ((tmp >> 12) & ((1UL << 28) - 1)) << 4;
 137         } else {
 138                 hpfar = read_sysreg(HPFAR);
 139         }
 140
 141         vcpu->arch.fault.hxfar = far;
 142         vcpu->arch.fault.hpfar = hpfar;
 143         return true;
 144 }
 145
 146 int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
 147 {
 148         struct kvm_cpu_context *host_ctxt;
 149         struct kvm_cpu_context *guest_ctxt;
 150         bool fp_enabled;
 151         u64 exit_code;
 152         u32 fpexc;
 153
 154         vcpu = kern_hyp_va(vcpu);
 155         write_sysreg(vcpu, HTPIDR);
 156
 157         host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
 158         guest_ctxt = &vcpu->arch.ctxt;
 159
 160         __sysreg_save_state(host_ctxt);
 161         __banked_save_state(host_ctxt);
 162
 163         __activate_traps(vcpu, &fpexc);
 164         __activate_vm(vcpu);
 165
 166         __vgic_restore_state(vcpu);
 167         __timer_restore_state(vcpu);
 168
 169         __sysreg_restore_state(guest_ctxt);
 170         __banked_restore_state(guest_ctxt);
 171
 172         /* Jump in the fire! */
 173 again:
 174         exit_code = __guest_enter(vcpu, host_ctxt);
 175         /* And we're baaack! */
 176
 177         if (exit_code == ARM_EXCEPTION_HVC && !__populate_fault_info(vcpu))
 178                 goto again;
 179
 180         fp_enabled = __vfp_enabled();
 181
 182         __banked_save_state(guest_ctxt);
 183         __sysreg_save_state(guest_ctxt);
 184         __timer_save_state(vcpu);
 185         __vgic_save_state(vcpu);
 186
 187         __deactivate_traps(vcpu);
 188         __deactivate_vm(vcpu);
 189
 190         __banked_restore_state(host_ctxt);
 191         __sysreg_restore_state(host_ctxt);
 192
 193         if (fp_enabled) {
 194                 __vfp_save_state(&guest_ctxt->vfp);
 195                 __vfp_restore_state(&host_ctxt->vfp);
 196         }
 197
 198         write_sysreg(fpexc, VFP_FPEXC);
 199
 200         return exit_code;
 201 }
 202
 203 static const char * const __hyp_panic_string[] = {
 204         [ARM_EXCEPTION_RESET]      = "\nHYP panic: RST   PC:%08x CPSR:%08x",
 205         [ARM_EXCEPTION_UNDEFINED]  = "\nHYP panic: UNDEF PC:%08x CPSR:%08x",
 206         [ARM_EXCEPTION_SOFTWARE]   = "\nHYP panic: SVC   PC:%08x CPSR:%08x",
 207         [ARM_EXCEPTION_PREF_ABORT] = "\nHYP panic: PABRT PC:%08x CPSR:%08x",
 208         [ARM_EXCEPTION_DATA_ABORT] = "\nHYP panic: DABRT PC:%08x ADDR:%08x",
 209         [ARM_EXCEPTION_IRQ]        = "\nHYP panic: IRQ   PC:%08x CPSR:%08x",
 210         [ARM_EXCEPTION_FIQ]        = "\nHYP panic: FIQ   PC:%08x CPSR:%08x",
 211         [ARM_EXCEPTION_HVC]        = "\nHYP panic: HVC   PC:%08x CPSR:%08x",
 212 };
 213
 214 void __hyp_text __noreturn __hyp_panic(int cause)
 215 {
 216         u32 elr = read_special(ELR_hyp);
 217         u32 val;
 218
 219         if (cause == ARM_EXCEPTION_DATA_ABORT)
 220                 val = read_sysreg(HDFAR);
 221         else
 222                 val = read_special(SPSR);
 223
 224         if (read_sysreg(VTTBR)) {
 225                 struct kvm_vcpu *vcpu;
 226                 struct kvm_cpu_context *host_ctxt;
 227
 228                 vcpu = (struct kvm_vcpu *)read_sysreg(HTPIDR);
 229                 host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
 230                 __deactivate_traps(vcpu);
 231                 __deactivate_vm(vcpu);
 232                 __sysreg_restore_state(host_ctxt);
 233         }
 234
 235         /* Call panic for real */
 236         __hyp_do_panic(__hyp_panic_string[cause], elr, val);
 237
 238         unreachable();
 239 }