arch/arm/mach-at91/at91cap9.c

   1 /*
   2  * arch/arm/mach-at91/at91cap9.c
   3  *
   4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
   5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
   6  *  Copyright (C) 2007 Atmel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16
  17 #include <asm/irq.h>
  18 #include <asm/mach/arch.h>
  19 #include <asm/mach/map.h>
  20 #include <asm/system_info.h>
  21 #include <asm/system_misc.h>
  22
  23 #include <mach/cpu.h>
  24 #include <mach/at91cap9.h>
  25 #include <mach/at91_pmc.h>
  26
  27 #include "soc.h"
  28 #include "generic.h"
  29 #include "clock.h"
  30 #include "sam9_smc.h"
  31
  32 /* --------------------------------------------------------------------
  33  *  Clocks
  34  * -------------------------------------------------------------------- */
  35
  36 /*
  37  * The peripheral clocks.
  38  */
  39 static struct clk pioABCD_clk = {
  40         .name           = "pioABCD_clk",
  41         .pmc_mask       = 1 << AT91CAP9_ID_PIOABCD,
  42         .type           = CLK_TYPE_PERIPHERAL,
  43 };
  44 static struct clk mpb0_clk = {
  45         .name           = "mpb0_clk",
  46         .pmc_mask       = 1 << AT91CAP9_ID_MPB0,
  47         .type           = CLK_TYPE_PERIPHERAL,
  48 };
  49 static struct clk mpb1_clk = {
  50         .name           = "mpb1_clk",
  51         .pmc_mask       = 1 << AT91CAP9_ID_MPB1,
  52         .type           = CLK_TYPE_PERIPHERAL,
  53 };
  54 static struct clk mpb2_clk = {
  55         .name           = "mpb2_clk",
  56         .pmc_mask       = 1 << AT91CAP9_ID_MPB2,
  57         .type           = CLK_TYPE_PERIPHERAL,
  58 };
  59 static struct clk mpb3_clk = {
  60         .name           = "mpb3_clk",
  61         .pmc_mask       = 1 << AT91CAP9_ID_MPB3,
  62         .type           = CLK_TYPE_PERIPHERAL,
  63 };
  64 static struct clk mpb4_clk = {
  65         .name           = "mpb4_clk",
  66         .pmc_mask       = 1 << AT91CAP9_ID_MPB4,
  67         .type           = CLK_TYPE_PERIPHERAL,
  68 };
  69 static struct clk usart0_clk = {
  70         .name           = "usart0_clk",
  71         .pmc_mask       = 1 << AT91CAP9_ID_US0,
  72         .type           = CLK_TYPE_PERIPHERAL,
  73 };
  74 static struct clk usart1_clk = {
  75         .name           = "usart1_clk",
  76         .pmc_mask       = 1 << AT91CAP9_ID_US1,
  77         .type           = CLK_TYPE_PERIPHERAL,
  78 };
  79 static struct clk usart2_clk = {
  80         .name           = "usart2_clk",
  81         .pmc_mask       = 1 << AT91CAP9_ID_US2,
  82         .type           = CLK_TYPE_PERIPHERAL,
  83 };
  84 static struct clk mmc0_clk = {
  85         .name           = "mci0_clk",
  86         .pmc_mask       = 1 << AT91CAP9_ID_MCI0,
  87         .type           = CLK_TYPE_PERIPHERAL,
  88 };
  89 static struct clk mmc1_clk = {
  90         .name           = "mci1_clk",
  91         .pmc_mask       = 1 << AT91CAP9_ID_MCI1,
  92         .type           = CLK_TYPE_PERIPHERAL,
  93 };
  94 static struct clk can_clk = {
  95         .name           = "can_clk",
  96         .pmc_mask       = 1 << AT91CAP9_ID_CAN,
  97         .type           = CLK_TYPE_PERIPHERAL,
  98 };
  99 static struct clk twi_clk = {
 100         .name           = "twi_clk",
 101         .pmc_mask       = 1 << AT91CAP9_ID_TWI,
 102         .type           = CLK_TYPE_PERIPHERAL,
 103 };
 104 static struct clk spi0_clk = {
 105         .name           = "spi0_clk",
 106         .pmc_mask       = 1 << AT91CAP9_ID_SPI0,
 107         .type           = CLK_TYPE_PERIPHERAL,
 108 };
 109 static struct clk spi1_clk = {
 110         .name           = "spi1_clk",
 111         .pmc_mask       = 1 << AT91CAP9_ID_SPI1,
 112         .type           = CLK_TYPE_PERIPHERAL,
 113 };
 114 static struct clk ssc0_clk = {
 115         .name           = "ssc0_clk",
 116         .pmc_mask       = 1 << AT91CAP9_ID_SSC0,
 117         .type           = CLK_TYPE_PERIPHERAL,
 118 };
 119 static struct clk ssc1_clk = {
 120         .name           = "ssc1_clk",
 121         .pmc_mask       = 1 << AT91CAP9_ID_SSC1,
 122         .type           = CLK_TYPE_PERIPHERAL,
 123 };
 124 static struct clk ac97_clk = {
 125         .name           = "ac97_clk",
 126         .pmc_mask       = 1 << AT91CAP9_ID_AC97C,
 127         .type           = CLK_TYPE_PERIPHERAL,
 128 };
 129 static struct clk tcb_clk = {
 130         .name           = "tcb_clk",
 131         .pmc_mask       = 1 << AT91CAP9_ID_TCB,
 132         .type           = CLK_TYPE_PERIPHERAL,
 133 };
 134 static struct clk pwm_clk = {
 135         .name           = "pwm_clk",
 136         .pmc_mask       = 1 << AT91CAP9_ID_PWMC,
 137         .type           = CLK_TYPE_PERIPHERAL,
 138 };
 139 static struct clk macb_clk = {
 140         .name           = "pclk",
 141         .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
 142         .type           = CLK_TYPE_PERIPHERAL,
 143 };
 144 static struct clk aestdes_clk = {
 145         .name           = "aestdes_clk",
 146         .pmc_mask       = 1 << AT91CAP9_ID_AESTDES,
 147         .type           = CLK_TYPE_PERIPHERAL,
 148 };
 149 static struct clk adc_clk = {
 150         .name           = "adc_clk",
 151         .pmc_mask       = 1 << AT91CAP9_ID_ADC,
 152         .type           = CLK_TYPE_PERIPHERAL,
 153 };
 154 static struct clk isi_clk = {
 155         .name           = "isi_clk",
 156         .pmc_mask       = 1 << AT91CAP9_ID_ISI,
 157         .type           = CLK_TYPE_PERIPHERAL,
 158 };
 159 static struct clk lcdc_clk = {
 160         .name           = "lcdc_clk",
 161         .pmc_mask       = 1 << AT91CAP9_ID_LCDC,
 162         .type           = CLK_TYPE_PERIPHERAL,
 163 };
 164 static struct clk dma_clk = {
 165         .name           = "dma_clk",
 166         .pmc_mask       = 1 << AT91CAP9_ID_DMA,
 167         .type           = CLK_TYPE_PERIPHERAL,
 168 };
 169 static struct clk udphs_clk = {
 170         .name           = "udphs_clk",
 171         .pmc_mask       = 1 << AT91CAP9_ID_UDPHS,
 172         .type           = CLK_TYPE_PERIPHERAL,
 173 };
 174 static struct clk ohci_clk = {
 175         .name           = "ohci_clk",
 176         .pmc_mask       = 1 << AT91CAP9_ID_UHP,
 177         .type           = CLK_TYPE_PERIPHERAL,
 178 };
 179
 180 static struct clk *periph_clocks[] __initdata = {
 181         &pioABCD_clk,
 182         &mpb0_clk,
 183         &mpb1_clk,
 184         &mpb2_clk,
 185         &mpb3_clk,
 186         &mpb4_clk,
 187         &usart0_clk,
 188         &usart1_clk,
 189         &usart2_clk,
 190         &mmc0_clk,
 191         &mmc1_clk,
 192         &can_clk,
 193         &twi_clk,
 194         &spi0_clk,
 195         &spi1_clk,
 196         &ssc0_clk,
 197         &ssc1_clk,
 198         &ac97_clk,
 199         &tcb_clk,
 200         &pwm_clk,
 201         &macb_clk,
 202         &aestdes_clk,
 203         &adc_clk,
 204         &isi_clk,
 205         &lcdc_clk,
 206         &dma_clk,
 207         &udphs_clk,
 208         &ohci_clk,
 209         // irq0 .. irq1
 210 };
 211
 212 static struct clk_lookup periph_clocks_lookups[] = {
 213         /* One additional fake clock for macb_hclk */
 214         CLKDEV_CON_ID("hclk", &macb_clk),
 215         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
 216         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
 217         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
 218         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
 219         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 220         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 221         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
 222         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 223         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 224         /* fake hclk clock */
 225         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 226         CLKDEV_CON_ID("pioA", &pioABCD_clk),
 227         CLKDEV_CON_ID("pioB", &pioABCD_clk),
 228         CLKDEV_CON_ID("pioC", &pioABCD_clk),
 229         CLKDEV_CON_ID("pioD", &pioABCD_clk),
 230 };
 231
 232 static struct clk_lookup usart_clocks_lookups[] = {
 233         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 234         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 235         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 236         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 237 };
 238
 239 /*
 240  * The four programmable clocks.
 241  * You must configure pin multiplexing to bring these signals out.
 242  */
 243 static struct clk pck0 = {
 244         .name           = "pck0",
 245         .pmc_mask       = AT91_PMC_PCK0,
 246         .type           = CLK_TYPE_PROGRAMMABLE,
 247         .id             = 0,
 248 };
 249 static struct clk pck1 = {
 250         .name           = "pck1",
 251         .pmc_mask       = AT91_PMC_PCK1,
 252         .type           = CLK_TYPE_PROGRAMMABLE,
 253         .id             = 1,
 254 };
 255 static struct clk pck2 = {
 256         .name           = "pck2",
 257         .pmc_mask       = AT91_PMC_PCK2,
 258         .type           = CLK_TYPE_PROGRAMMABLE,
 259         .id             = 2,
 260 };
 261 static struct clk pck3 = {
 262         .name           = "pck3",
 263         .pmc_mask       = AT91_PMC_PCK3,
 264         .type           = CLK_TYPE_PROGRAMMABLE,
 265         .id             = 3,
 266 };
 267
 268 static void __init at91cap9_register_clocks(void)
 269 {
 270         int i;
 271
 272         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 273                 clk_register(periph_clocks[i]);
 274
 275         clkdev_add_table(periph_clocks_lookups,
 276                          ARRAY_SIZE(periph_clocks_lookups));
 277         clkdev_add_table(usart_clocks_lookups,
 278                          ARRAY_SIZE(usart_clocks_lookups));
 279
 280         clk_register(&pck0);
 281         clk_register(&pck1);
 282         clk_register(&pck2);
 283         clk_register(&pck3);
 284 }
 285
 286 static struct clk_lookup console_clock_lookup;
 287
 288 void __init at91cap9_set_console_clock(int id)
 289 {
 290         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 291                 return;
 292
 293         console_clock_lookup.con_id = "usart";
 294         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 295         clkdev_add(&console_clock_lookup);
 296 }
 297
 298 /* --------------------------------------------------------------------
 299  *  GPIO
 300  * -------------------------------------------------------------------- */
 301
 302 static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
 303         {
 304                 .id             = AT91CAP9_ID_PIOABCD,
 305                 .regbase        = AT91CAP9_BASE_PIOA,
 306         }, {
 307                 .id             = AT91CAP9_ID_PIOABCD,
 308                 .regbase        = AT91CAP9_BASE_PIOB,
 309         }, {
 310                 .id             = AT91CAP9_ID_PIOABCD,
 311                 .regbase        = AT91CAP9_BASE_PIOC,
 312         }, {
 313                 .id             = AT91CAP9_ID_PIOABCD,
 314                 .regbase        = AT91CAP9_BASE_PIOD,
 315         }
 316 };
 317
 318 /* --------------------------------------------------------------------
 319  *  AT91CAP9 processor initialization
 320  * -------------------------------------------------------------------- */
 321
 322 static void __init at91cap9_map_io(void)
 323 {
 324         at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
 325 }
 326
 327 static void __init at91cap9_ioremap_registers(void)
 328 {
 329         at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
 330         at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
 331         at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
 332         at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
 333 }
 334
 335 static void __init at91cap9_initialize(void)
 336 {
 337         arm_pm_restart = at91sam9g45_restart;
 338         at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
 339
 340         /* Register GPIO subsystem */
 341         at91_gpio_init(at91cap9_gpio, 4);
 342
 343         /* Remember the silicon revision */
 344         if (cpu_is_at91cap9_revB())
 345                 system_rev = 0xB;
 346         else if (cpu_is_at91cap9_revC())
 347                 system_rev = 0xC;
 348 }
 349
 350 /* --------------------------------------------------------------------
 351  *  Interrupt initialization
 352  * -------------------------------------------------------------------- */
 353
 354 /*
 355  * The default interrupt priority levels (0 = lowest, 7 = highest).
 356  */
 357 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
 358         7,      /* Advanced Interrupt Controller (FIQ) */
 359         7,      /* System Peripherals */
 360         1,      /* Parallel IO Controller A, B, C and D */
 361         0,      /* MP Block Peripheral 0 */
 362         0,      /* MP Block Peripheral 1 */
 363         0,      /* MP Block Peripheral 2 */
 364         0,      /* MP Block Peripheral 3 */
 365         0,      /* MP Block Peripheral 4 */
 366         5,      /* USART 0 */
 367         5,      /* USART 1 */
 368         5,      /* USART 2 */
 369         0,      /* Multimedia Card Interface 0 */
 370         0,      /* Multimedia Card Interface 1 */
 371         3,      /* CAN */
 372         6,      /* Two-Wire Interface */
 373         5,      /* Serial Peripheral Interface 0 */
 374         5,      /* Serial Peripheral Interface 1 */
 375         4,      /* Serial Synchronous Controller 0 */
 376         4,      /* Serial Synchronous Controller 1 */
 377         5,      /* AC97 Controller */
 378         0,      /* Timer Counter 0, 1 and 2 */
 379         0,      /* Pulse Width Modulation Controller */
 380         3,      /* Ethernet */
 381         0,      /* Advanced Encryption Standard, Triple DES*/
 382         0,      /* Analog-to-Digital Converter */
 383         0,      /* Image Sensor Interface */
 384         3,      /* LCD Controller */
 385         0,      /* DMA Controller */
 386         2,      /* USB Device Port */
 387         2,      /* USB Host port */
 388         0,      /* Advanced Interrupt Controller (IRQ0) */
 389         0,      /* Advanced Interrupt Controller (IRQ1) */
 390 };
 391
 392 struct at91_init_soc __initdata at91cap9_soc = {
 393         .map_io = at91cap9_map_io,
 394         .default_irq_priority = at91cap9_default_irq_priority,
 395         .ioremap_registers = at91cap9_ioremap_registers,
 396         .register_clocks = at91cap9_register_clocks,
 397         .init = at91cap9_initialize,
 398 };