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Merge commit 'v2.6.29' into timers/core
[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-at91 / at91sam9260_devices.c
1 /*
2 * arch/arm/mach-at91/at91sam9260_devices.c
3 *
4 * Copyright (C) 2006 Atmel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c-gpio.h>
18
19 #include <mach/board.h>
20 #include <mach/gpio.h>
21 #include <mach/cpu.h>
22 #include <mach/at91sam9260.h>
23 #include <mach/at91sam9260_matrix.h>
24 #include <mach/at91sam9_smc.h>
25
26 #include "generic.h"
27
28
29 /* --------------------------------------------------------------------
30 * USB Host
31 * -------------------------------------------------------------------- */
32
33 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
34 static u64 ohci_dmamask = DMA_BIT_MASK(32);
35 static struct at91_usbh_data usbh_data;
36
37 static struct resource usbh_resources[] = {
38 [0] = {
39 .start = AT91SAM9260_UHP_BASE,
40 .end = AT91SAM9260_UHP_BASE + SZ_1M - 1,
41 .flags = IORESOURCE_MEM,
42 },
43 [1] = {
44 .start = AT91SAM9260_ID_UHP,
45 .end = AT91SAM9260_ID_UHP,
46 .flags = IORESOURCE_IRQ,
47 },
48 };
49
50 static struct platform_device at91_usbh_device = {
51 .name = "at91_ohci",
52 .id = -1,
53 .dev = {
54 .dma_mask = &ohci_dmamask,
55 .coherent_dma_mask = DMA_BIT_MASK(32),
56 .platform_data = &usbh_data,
57 },
58 .resource = usbh_resources,
59 .num_resources = ARRAY_SIZE(usbh_resources),
60 };
61
62 void __init at91_add_device_usbh(struct at91_usbh_data *data)
63 {
64 if (!data)
65 return;
66
67 usbh_data = *data;
68 platform_device_register(&at91_usbh_device);
69 }
70 #else
71 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
72 #endif
73
74
75 /* --------------------------------------------------------------------
76 * USB Device (Gadget)
77 * -------------------------------------------------------------------- */
78
79 #ifdef CONFIG_USB_GADGET_AT91
80 static struct at91_udc_data udc_data;
81
82 static struct resource udc_resources[] = {
83 [0] = {
84 .start = AT91SAM9260_BASE_UDP,
85 .end = AT91SAM9260_BASE_UDP + SZ_16K - 1,
86 .flags = IORESOURCE_MEM,
87 },
88 [1] = {
89 .start = AT91SAM9260_ID_UDP,
90 .end = AT91SAM9260_ID_UDP,
91 .flags = IORESOURCE_IRQ,
92 },
93 };
94
95 static struct platform_device at91_udc_device = {
96 .name = "at91_udc",
97 .id = -1,
98 .dev = {
99 .platform_data = &udc_data,
100 },
101 .resource = udc_resources,
102 .num_resources = ARRAY_SIZE(udc_resources),
103 };
104
105 void __init at91_add_device_udc(struct at91_udc_data *data)
106 {
107 if (!data)
108 return;
109
110 if (data->vbus_pin) {
111 at91_set_gpio_input(data->vbus_pin, 0);
112 at91_set_deglitch(data->vbus_pin, 1);
113 }
114
115 /* Pullup pin is handled internally by USB device peripheral */
116
117 udc_data = *data;
118 platform_device_register(&at91_udc_device);
119 }
120 #else
121 void __init at91_add_device_udc(struct at91_udc_data *data) {}
122 #endif
123
124
125 /* --------------------------------------------------------------------
126 * Ethernet
127 * -------------------------------------------------------------------- */
128
129 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
130 static u64 eth_dmamask = DMA_BIT_MASK(32);
131 static struct at91_eth_data eth_data;
132
133 static struct resource eth_resources[] = {
134 [0] = {
135 .start = AT91SAM9260_BASE_EMAC,
136 .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
137 .flags = IORESOURCE_MEM,
138 },
139 [1] = {
140 .start = AT91SAM9260_ID_EMAC,
141 .end = AT91SAM9260_ID_EMAC,
142 .flags = IORESOURCE_IRQ,
143 },
144 };
145
146 static struct platform_device at91sam9260_eth_device = {
147 .name = "macb",
148 .id = -1,
149 .dev = {
150 .dma_mask = &eth_dmamask,
151 .coherent_dma_mask = DMA_BIT_MASK(32),
152 .platform_data = &eth_data,
153 },
154 .resource = eth_resources,
155 .num_resources = ARRAY_SIZE(eth_resources),
156 };
157
158 void __init at91_add_device_eth(struct at91_eth_data *data)
159 {
160 if (!data)
161 return;
162
163 if (data->phy_irq_pin) {
164 at91_set_gpio_input(data->phy_irq_pin, 0);
165 at91_set_deglitch(data->phy_irq_pin, 1);
166 }
167
168 /* Pins used for MII and RMII */
169 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
170 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
171 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
172 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
173 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
174 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
175 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
176 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
177 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
178 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
179
180 if (!data->is_rmii) {
181 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
182 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
183 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
184 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
185 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
186 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
187 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
188 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
189 }
190
191 eth_data = *data;
192 platform_device_register(&at91sam9260_eth_device);
193 }
194 #else
195 void __init at91_add_device_eth(struct at91_eth_data *data) {}
196 #endif
197
198
199 /* --------------------------------------------------------------------
200 * MMC / SD
201 * -------------------------------------------------------------------- */
202
203 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
204 static u64 mmc_dmamask = DMA_BIT_MASK(32);
205 static struct at91_mmc_data mmc_data;
206
207 static struct resource mmc_resources[] = {
208 [0] = {
209 .start = AT91SAM9260_BASE_MCI,
210 .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
211 .flags = IORESOURCE_MEM,
212 },
213 [1] = {
214 .start = AT91SAM9260_ID_MCI,
215 .end = AT91SAM9260_ID_MCI,
216 .flags = IORESOURCE_IRQ,
217 },
218 };
219
220 static struct platform_device at91sam9260_mmc_device = {
221 .name = "at91_mci",
222 .id = -1,
223 .dev = {
224 .dma_mask = &mmc_dmamask,
225 .coherent_dma_mask = DMA_BIT_MASK(32),
226 .platform_data = &mmc_data,
227 },
228 .resource = mmc_resources,
229 .num_resources = ARRAY_SIZE(mmc_resources),
230 };
231
232 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
233 {
234 if (!data)
235 return;
236
237 /* input/irq */
238 if (data->det_pin) {
239 at91_set_gpio_input(data->det_pin, 1);
240 at91_set_deglitch(data->det_pin, 1);
241 }
242 if (data->wp_pin)
243 at91_set_gpio_input(data->wp_pin, 1);
244 if (data->vcc_pin)
245 at91_set_gpio_output(data->vcc_pin, 0);
246
247 /* CLK */
248 at91_set_A_periph(AT91_PIN_PA8, 0);
249
250 if (data->slot_b) {
251 /* CMD */
252 at91_set_B_periph(AT91_PIN_PA1, 1);
253
254 /* DAT0, maybe DAT1..DAT3 */
255 at91_set_B_periph(AT91_PIN_PA0, 1);
256 if (data->wire4) {
257 at91_set_B_periph(AT91_PIN_PA5, 1);
258 at91_set_B_periph(AT91_PIN_PA4, 1);
259 at91_set_B_periph(AT91_PIN_PA3, 1);
260 }
261 } else {
262 /* CMD */
263 at91_set_A_periph(AT91_PIN_PA7, 1);
264
265 /* DAT0, maybe DAT1..DAT3 */
266 at91_set_A_periph(AT91_PIN_PA6, 1);
267 if (data->wire4) {
268 at91_set_A_periph(AT91_PIN_PA9, 1);
269 at91_set_A_periph(AT91_PIN_PA10, 1);
270 at91_set_A_periph(AT91_PIN_PA11, 1);
271 }
272 }
273
274 mmc_data = *data;
275 platform_device_register(&at91sam9260_mmc_device);
276 }
277 #else
278 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
279 #endif
280
281
282 /* --------------------------------------------------------------------
283 * NAND / SmartMedia
284 * -------------------------------------------------------------------- */
285
286 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
287 static struct atmel_nand_data nand_data;
288
289 #define NAND_BASE AT91_CHIPSELECT_3
290
291 static struct resource nand_resources[] = {
292 [0] = {
293 .start = NAND_BASE,
294 .end = NAND_BASE + SZ_256M - 1,
295 .flags = IORESOURCE_MEM,
296 },
297 [1] = {
298 .start = AT91_BASE_SYS + AT91_ECC,
299 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
300 .flags = IORESOURCE_MEM,
301 }
302 };
303
304 static struct platform_device at91sam9260_nand_device = {
305 .name = "atmel_nand",
306 .id = -1,
307 .dev = {
308 .platform_data = &nand_data,
309 },
310 .resource = nand_resources,
311 .num_resources = ARRAY_SIZE(nand_resources),
312 };
313
314 void __init at91_add_device_nand(struct atmel_nand_data *data)
315 {
316 unsigned long csa;
317
318 if (!data)
319 return;
320
321 csa = at91_sys_read(AT91_MATRIX_EBICSA);
322 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
323
324 /* enable pin */
325 if (data->enable_pin)
326 at91_set_gpio_output(data->enable_pin, 1);
327
328 /* ready/busy pin */
329 if (data->rdy_pin)
330 at91_set_gpio_input(data->rdy_pin, 1);
331
332 /* card detect pin */
333 if (data->det_pin)
334 at91_set_gpio_input(data->det_pin, 1);
335
336 nand_data = *data;
337 platform_device_register(&at91sam9260_nand_device);
338 }
339 #else
340 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
341 #endif
342
343
344 /* --------------------------------------------------------------------
345 * TWI (i2c)
346 * -------------------------------------------------------------------- */
347
348 /*
349 * Prefer the GPIO code since the TWI controller isn't robust
350 * (gets overruns and underruns under load) and can only issue
351 * repeated STARTs in one scenario (the driver doesn't yet handle them).
352 */
353
354 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
355
356 static struct i2c_gpio_platform_data pdata = {
357 .sda_pin = AT91_PIN_PA23,
358 .sda_is_open_drain = 1,
359 .scl_pin = AT91_PIN_PA24,
360 .scl_is_open_drain = 1,
361 .udelay = 2, /* ~100 kHz */
362 };
363
364 static struct platform_device at91sam9260_twi_device = {
365 .name = "i2c-gpio",
366 .id = -1,
367 .dev.platform_data = &pdata,
368 };
369
370 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
371 {
372 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
373 at91_set_multi_drive(AT91_PIN_PA23, 1);
374
375 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
376 at91_set_multi_drive(AT91_PIN_PA24, 1);
377
378 i2c_register_board_info(0, devices, nr_devices);
379 platform_device_register(&at91sam9260_twi_device);
380 }
381
382 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
383
384 static struct resource twi_resources[] = {
385 [0] = {
386 .start = AT91SAM9260_BASE_TWI,
387 .end = AT91SAM9260_BASE_TWI + SZ_16K - 1,
388 .flags = IORESOURCE_MEM,
389 },
390 [1] = {
391 .start = AT91SAM9260_ID_TWI,
392 .end = AT91SAM9260_ID_TWI,
393 .flags = IORESOURCE_IRQ,
394 },
395 };
396
397 static struct platform_device at91sam9260_twi_device = {
398 .name = "at91_i2c",
399 .id = -1,
400 .resource = twi_resources,
401 .num_resources = ARRAY_SIZE(twi_resources),
402 };
403
404 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
405 {
406 /* pins used for TWI interface */
407 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
408 at91_set_multi_drive(AT91_PIN_PA23, 1);
409
410 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
411 at91_set_multi_drive(AT91_PIN_PA24, 1);
412
413 i2c_register_board_info(0, devices, nr_devices);
414 platform_device_register(&at91sam9260_twi_device);
415 }
416 #else
417 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
418 #endif
419
420
421 /* --------------------------------------------------------------------
422 * SPI
423 * -------------------------------------------------------------------- */
424
425 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
426 static u64 spi_dmamask = DMA_BIT_MASK(32);
427
428 static struct resource spi0_resources[] = {
429 [0] = {
430 .start = AT91SAM9260_BASE_SPI0,
431 .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
432 .flags = IORESOURCE_MEM,
433 },
434 [1] = {
435 .start = AT91SAM9260_ID_SPI0,
436 .end = AT91SAM9260_ID_SPI0,
437 .flags = IORESOURCE_IRQ,
438 },
439 };
440
441 static struct platform_device at91sam9260_spi0_device = {
442 .name = "atmel_spi",
443 .id = 0,
444 .dev = {
445 .dma_mask = &spi_dmamask,
446 .coherent_dma_mask = DMA_BIT_MASK(32),
447 },
448 .resource = spi0_resources,
449 .num_resources = ARRAY_SIZE(spi0_resources),
450 };
451
452 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
453
454 static struct resource spi1_resources[] = {
455 [0] = {
456 .start = AT91SAM9260_BASE_SPI1,
457 .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
458 .flags = IORESOURCE_MEM,
459 },
460 [1] = {
461 .start = AT91SAM9260_ID_SPI1,
462 .end = AT91SAM9260_ID_SPI1,
463 .flags = IORESOURCE_IRQ,
464 },
465 };
466
467 static struct platform_device at91sam9260_spi1_device = {
468 .name = "atmel_spi",
469 .id = 1,
470 .dev = {
471 .dma_mask = &spi_dmamask,
472 .coherent_dma_mask = DMA_BIT_MASK(32),
473 },
474 .resource = spi1_resources,
475 .num_resources = ARRAY_SIZE(spi1_resources),
476 };
477
478 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
479
480 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
481 {
482 int i;
483 unsigned long cs_pin;
484 short enable_spi0 = 0;
485 short enable_spi1 = 0;
486
487 /* Choose SPI chip-selects */
488 for (i = 0; i < nr_devices; i++) {
489 if (devices[i].controller_data)
490 cs_pin = (unsigned long) devices[i].controller_data;
491 else if (devices[i].bus_num == 0)
492 cs_pin = spi0_standard_cs[devices[i].chip_select];
493 else
494 cs_pin = spi1_standard_cs[devices[i].chip_select];
495
496 if (devices[i].bus_num == 0)
497 enable_spi0 = 1;
498 else
499 enable_spi1 = 1;
500
501 /* enable chip-select pin */
502 at91_set_gpio_output(cs_pin, 1);
503
504 /* pass chip-select pin to driver */
505 devices[i].controller_data = (void *) cs_pin;
506 }
507
508 spi_register_board_info(devices, nr_devices);
509
510 /* Configure SPI bus(es) */
511 if (enable_spi0) {
512 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
513 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
514 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
515
516 at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk");
517 platform_device_register(&at91sam9260_spi0_device);
518 }
519 if (enable_spi1) {
520 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
521 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
522 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
523
524 at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk");
525 platform_device_register(&at91sam9260_spi1_device);
526 }
527 }
528 #else
529 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
530 #endif
531
532
533 /* --------------------------------------------------------------------
534 * Timer/Counter blocks
535 * -------------------------------------------------------------------- */
536
537 #ifdef CONFIG_ATMEL_TCLIB
538
539 static struct resource tcb0_resources[] = {
540 [0] = {
541 .start = AT91SAM9260_BASE_TCB0,
542 .end = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
543 .flags = IORESOURCE_MEM,
544 },
545 [1] = {
546 .start = AT91SAM9260_ID_TC0,
547 .end = AT91SAM9260_ID_TC0,
548 .flags = IORESOURCE_IRQ,
549 },
550 [2] = {
551 .start = AT91SAM9260_ID_TC1,
552 .end = AT91SAM9260_ID_TC1,
553 .flags = IORESOURCE_IRQ,
554 },
555 [3] = {
556 .start = AT91SAM9260_ID_TC2,
557 .end = AT91SAM9260_ID_TC2,
558 .flags = IORESOURCE_IRQ,
559 },
560 };
561
562 static struct platform_device at91sam9260_tcb0_device = {
563 .name = "atmel_tcb",
564 .id = 0,
565 .resource = tcb0_resources,
566 .num_resources = ARRAY_SIZE(tcb0_resources),
567 };
568
569 static struct resource tcb1_resources[] = {
570 [0] = {
571 .start = AT91SAM9260_BASE_TCB1,
572 .end = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
573 .flags = IORESOURCE_MEM,
574 },
575 [1] = {
576 .start = AT91SAM9260_ID_TC3,
577 .end = AT91SAM9260_ID_TC3,
578 .flags = IORESOURCE_IRQ,
579 },
580 [2] = {
581 .start = AT91SAM9260_ID_TC4,
582 .end = AT91SAM9260_ID_TC4,
583 .flags = IORESOURCE_IRQ,
584 },
585 [3] = {
586 .start = AT91SAM9260_ID_TC5,
587 .end = AT91SAM9260_ID_TC5,
588 .flags = IORESOURCE_IRQ,
589 },
590 };
591
592 static struct platform_device at91sam9260_tcb1_device = {
593 .name = "atmel_tcb",
594 .id = 1,
595 .resource = tcb1_resources,
596 .num_resources = ARRAY_SIZE(tcb1_resources),
597 };
598
599 static void __init at91_add_device_tc(void)
600 {
601 /* this chip has a separate clock and irq for each TC channel */
602 at91_clock_associate("tc0_clk", &at91sam9260_tcb0_device.dev, "t0_clk");
603 at91_clock_associate("tc1_clk", &at91sam9260_tcb0_device.dev, "t1_clk");
604 at91_clock_associate("tc2_clk", &at91sam9260_tcb0_device.dev, "t2_clk");
605 platform_device_register(&at91sam9260_tcb0_device);
606
607 at91_clock_associate("tc3_clk", &at91sam9260_tcb1_device.dev, "t0_clk");
608 at91_clock_associate("tc4_clk", &at91sam9260_tcb1_device.dev, "t1_clk");
609 at91_clock_associate("tc5_clk", &at91sam9260_tcb1_device.dev, "t2_clk");
610 platform_device_register(&at91sam9260_tcb1_device);
611 }
612 #else
613 static void __init at91_add_device_tc(void) { }
614 #endif
615
616
617 /* --------------------------------------------------------------------
618 * RTT
619 * -------------------------------------------------------------------- */
620
621 static struct resource rtt_resources[] = {
622 {
623 .start = AT91_BASE_SYS + AT91_RTT,
624 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
625 .flags = IORESOURCE_MEM,
626 }
627 };
628
629 static struct platform_device at91sam9260_rtt_device = {
630 .name = "at91_rtt",
631 .id = 0,
632 .resource = rtt_resources,
633 .num_resources = ARRAY_SIZE(rtt_resources),
634 };
635
636 static void __init at91_add_device_rtt(void)
637 {
638 platform_device_register(&at91sam9260_rtt_device);
639 }
640
641
642 /* --------------------------------------------------------------------
643 * Watchdog
644 * -------------------------------------------------------------------- */
645
646 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
647 static struct platform_device at91sam9260_wdt_device = {
648 .name = "at91_wdt",
649 .id = -1,
650 .num_resources = 0,
651 };
652
653 static void __init at91_add_device_watchdog(void)
654 {
655 platform_device_register(&at91sam9260_wdt_device);
656 }
657 #else
658 static void __init at91_add_device_watchdog(void) {}
659 #endif
660
661
662 /* --------------------------------------------------------------------
663 * SSC -- Synchronous Serial Controller
664 * -------------------------------------------------------------------- */
665
666 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
667 static u64 ssc_dmamask = DMA_BIT_MASK(32);
668
669 static struct resource ssc_resources[] = {
670 [0] = {
671 .start = AT91SAM9260_BASE_SSC,
672 .end = AT91SAM9260_BASE_SSC + SZ_16K - 1,
673 .flags = IORESOURCE_MEM,
674 },
675 [1] = {
676 .start = AT91SAM9260_ID_SSC,
677 .end = AT91SAM9260_ID_SSC,
678 .flags = IORESOURCE_IRQ,
679 },
680 };
681
682 static struct platform_device at91sam9260_ssc_device = {
683 .name = "ssc",
684 .id = 0,
685 .dev = {
686 .dma_mask = &ssc_dmamask,
687 .coherent_dma_mask = DMA_BIT_MASK(32),
688 },
689 .resource = ssc_resources,
690 .num_resources = ARRAY_SIZE(ssc_resources),
691 };
692
693 static inline void configure_ssc_pins(unsigned pins)
694 {
695 if (pins & ATMEL_SSC_TF)
696 at91_set_A_periph(AT91_PIN_PB17, 1);
697 if (pins & ATMEL_SSC_TK)
698 at91_set_A_periph(AT91_PIN_PB16, 1);
699 if (pins & ATMEL_SSC_TD)
700 at91_set_A_periph(AT91_PIN_PB18, 1);
701 if (pins & ATMEL_SSC_RD)
702 at91_set_A_periph(AT91_PIN_PB19, 1);
703 if (pins & ATMEL_SSC_RK)
704 at91_set_A_periph(AT91_PIN_PB20, 1);
705 if (pins & ATMEL_SSC_RF)
706 at91_set_A_periph(AT91_PIN_PB21, 1);
707 }
708
709 /*
710 * SSC controllers are accessed through library code, instead of any
711 * kind of all-singing/all-dancing driver. For example one could be
712 * used by a particular I2S audio codec's driver, while another one
713 * on the same system might be used by a custom data capture driver.
714 */
715 void __init at91_add_device_ssc(unsigned id, unsigned pins)
716 {
717 struct platform_device *pdev;
718
719 /*
720 * NOTE: caller is responsible for passing information matching
721 * "pins" to whatever will be using each particular controller.
722 */
723 switch (id) {
724 case AT91SAM9260_ID_SSC:
725 pdev = &at91sam9260_ssc_device;
726 configure_ssc_pins(pins);
727 at91_clock_associate("ssc_clk", &pdev->dev, "pclk");
728 break;
729 default:
730 return;
731 }
732
733 platform_device_register(pdev);
734 }
735
736 #else
737 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
738 #endif
739
740
741 /* --------------------------------------------------------------------
742 * UART
743 * -------------------------------------------------------------------- */
744 #if defined(CONFIG_SERIAL_ATMEL)
745 static struct resource dbgu_resources[] = {
746 [0] = {
747 .start = AT91_VA_BASE_SYS + AT91_DBGU,
748 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
749 .flags = IORESOURCE_MEM,
750 },
751 [1] = {
752 .start = AT91_ID_SYS,
753 .end = AT91_ID_SYS,
754 .flags = IORESOURCE_IRQ,
755 },
756 };
757
758 static struct atmel_uart_data dbgu_data = {
759 .use_dma_tx = 0,
760 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
761 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
762 };
763
764 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
765
766 static struct platform_device at91sam9260_dbgu_device = {
767 .name = "atmel_usart",
768 .id = 0,
769 .dev = {
770 .dma_mask = &dbgu_dmamask,
771 .coherent_dma_mask = DMA_BIT_MASK(32),
772 .platform_data = &dbgu_data,
773 },
774 .resource = dbgu_resources,
775 .num_resources = ARRAY_SIZE(dbgu_resources),
776 };
777
778 static inline void configure_dbgu_pins(void)
779 {
780 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
781 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
782 }
783
784 static struct resource uart0_resources[] = {
785 [0] = {
786 .start = AT91SAM9260_BASE_US0,
787 .end = AT91SAM9260_BASE_US0 + SZ_16K - 1,
788 .flags = IORESOURCE_MEM,
789 },
790 [1] = {
791 .start = AT91SAM9260_ID_US0,
792 .end = AT91SAM9260_ID_US0,
793 .flags = IORESOURCE_IRQ,
794 },
795 };
796
797 static struct atmel_uart_data uart0_data = {
798 .use_dma_tx = 1,
799 .use_dma_rx = 1,
800 };
801
802 static u64 uart0_dmamask = DMA_BIT_MASK(32);
803
804 static struct platform_device at91sam9260_uart0_device = {
805 .name = "atmel_usart",
806 .id = 1,
807 .dev = {
808 .dma_mask = &uart0_dmamask,
809 .coherent_dma_mask = DMA_BIT_MASK(32),
810 .platform_data = &uart0_data,
811 },
812 .resource = uart0_resources,
813 .num_resources = ARRAY_SIZE(uart0_resources),
814 };
815
816 static inline void configure_usart0_pins(unsigned pins)
817 {
818 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
819 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
820
821 if (pins & ATMEL_UART_RTS)
822 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
823 if (pins & ATMEL_UART_CTS)
824 at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
825 if (pins & ATMEL_UART_DTR)
826 at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
827 if (pins & ATMEL_UART_DSR)
828 at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
829 if (pins & ATMEL_UART_DCD)
830 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
831 if (pins & ATMEL_UART_RI)
832 at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
833 }
834
835 static struct resource uart1_resources[] = {
836 [0] = {
837 .start = AT91SAM9260_BASE_US1,
838 .end = AT91SAM9260_BASE_US1 + SZ_16K - 1,
839 .flags = IORESOURCE_MEM,
840 },
841 [1] = {
842 .start = AT91SAM9260_ID_US1,
843 .end = AT91SAM9260_ID_US1,
844 .flags = IORESOURCE_IRQ,
845 },
846 };
847
848 static struct atmel_uart_data uart1_data = {
849 .use_dma_tx = 1,
850 .use_dma_rx = 1,
851 };
852
853 static u64 uart1_dmamask = DMA_BIT_MASK(32);
854
855 static struct platform_device at91sam9260_uart1_device = {
856 .name = "atmel_usart",
857 .id = 2,
858 .dev = {
859 .dma_mask = &uart1_dmamask,
860 .coherent_dma_mask = DMA_BIT_MASK(32),
861 .platform_data = &uart1_data,
862 },
863 .resource = uart1_resources,
864 .num_resources = ARRAY_SIZE(uart1_resources),
865 };
866
867 static inline void configure_usart1_pins(unsigned pins)
868 {
869 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
870 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
871
872 if (pins & ATMEL_UART_RTS)
873 at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
874 if (pins & ATMEL_UART_CTS)
875 at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
876 }
877
878 static struct resource uart2_resources[] = {
879 [0] = {
880 .start = AT91SAM9260_BASE_US2,
881 .end = AT91SAM9260_BASE_US2 + SZ_16K - 1,
882 .flags = IORESOURCE_MEM,
883 },
884 [1] = {
885 .start = AT91SAM9260_ID_US2,
886 .end = AT91SAM9260_ID_US2,
887 .flags = IORESOURCE_IRQ,
888 },
889 };
890
891 static struct atmel_uart_data uart2_data = {
892 .use_dma_tx = 1,
893 .use_dma_rx = 1,
894 };
895
896 static u64 uart2_dmamask = DMA_BIT_MASK(32);
897
898 static struct platform_device at91sam9260_uart2_device = {
899 .name = "atmel_usart",
900 .id = 3,
901 .dev = {
902 .dma_mask = &uart2_dmamask,
903 .coherent_dma_mask = DMA_BIT_MASK(32),
904 .platform_data = &uart2_data,
905 },
906 .resource = uart2_resources,
907 .num_resources = ARRAY_SIZE(uart2_resources),
908 };
909
910 static inline void configure_usart2_pins(unsigned pins)
911 {
912 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
913 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
914
915 if (pins & ATMEL_UART_RTS)
916 at91_set_A_periph(AT91_PIN_PA4, 0); /* RTS2 */
917 if (pins & ATMEL_UART_CTS)
918 at91_set_A_periph(AT91_PIN_PA5, 0); /* CTS2 */
919 }
920
921 static struct resource uart3_resources[] = {
922 [0] = {
923 .start = AT91SAM9260_BASE_US3,
924 .end = AT91SAM9260_BASE_US3 + SZ_16K - 1,
925 .flags = IORESOURCE_MEM,
926 },
927 [1] = {
928 .start = AT91SAM9260_ID_US3,
929 .end = AT91SAM9260_ID_US3,
930 .flags = IORESOURCE_IRQ,
931 },
932 };
933
934 static struct atmel_uart_data uart3_data = {
935 .use_dma_tx = 1,
936 .use_dma_rx = 1,
937 };
938
939 static u64 uart3_dmamask = DMA_BIT_MASK(32);
940
941 static struct platform_device at91sam9260_uart3_device = {
942 .name = "atmel_usart",
943 .id = 4,
944 .dev = {
945 .dma_mask = &uart3_dmamask,
946 .coherent_dma_mask = DMA_BIT_MASK(32),
947 .platform_data = &uart3_data,
948 },
949 .resource = uart3_resources,
950 .num_resources = ARRAY_SIZE(uart3_resources),
951 };
952
953 static inline void configure_usart3_pins(unsigned pins)
954 {
955 at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
956 at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
957
958 if (pins & ATMEL_UART_RTS)
959 at91_set_B_periph(AT91_PIN_PC8, 0); /* RTS3 */
960 if (pins & ATMEL_UART_CTS)
961 at91_set_B_periph(AT91_PIN_PC10, 0); /* CTS3 */
962 }
963
964 static struct resource uart4_resources[] = {
965 [0] = {
966 .start = AT91SAM9260_BASE_US4,
967 .end = AT91SAM9260_BASE_US4 + SZ_16K - 1,
968 .flags = IORESOURCE_MEM,
969 },
970 [1] = {
971 .start = AT91SAM9260_ID_US4,
972 .end = AT91SAM9260_ID_US4,
973 .flags = IORESOURCE_IRQ,
974 },
975 };
976
977 static struct atmel_uart_data uart4_data = {
978 .use_dma_tx = 1,
979 .use_dma_rx = 1,
980 };
981
982 static u64 uart4_dmamask = DMA_BIT_MASK(32);
983
984 static struct platform_device at91sam9260_uart4_device = {
985 .name = "atmel_usart",
986 .id = 5,
987 .dev = {
988 .dma_mask = &uart4_dmamask,
989 .coherent_dma_mask = DMA_BIT_MASK(32),
990 .platform_data = &uart4_data,
991 },
992 .resource = uart4_resources,
993 .num_resources = ARRAY_SIZE(uart4_resources),
994 };
995
996 static inline void configure_usart4_pins(void)
997 {
998 at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
999 at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
1000 }
1001
1002 static struct resource uart5_resources[] = {
1003 [0] = {
1004 .start = AT91SAM9260_BASE_US5,
1005 .end = AT91SAM9260_BASE_US5 + SZ_16K - 1,
1006 .flags = IORESOURCE_MEM,
1007 },
1008 [1] = {
1009 .start = AT91SAM9260_ID_US5,
1010 .end = AT91SAM9260_ID_US5,
1011 .flags = IORESOURCE_IRQ,
1012 },
1013 };
1014
1015 static struct atmel_uart_data uart5_data = {
1016 .use_dma_tx = 1,
1017 .use_dma_rx = 1,
1018 };
1019
1020 static u64 uart5_dmamask = DMA_BIT_MASK(32);
1021
1022 static struct platform_device at91sam9260_uart5_device = {
1023 .name = "atmel_usart",
1024 .id = 6,
1025 .dev = {
1026 .dma_mask = &uart5_dmamask,
1027 .coherent_dma_mask = DMA_BIT_MASK(32),
1028 .platform_data = &uart5_data,
1029 },
1030 .resource = uart5_resources,
1031 .num_resources = ARRAY_SIZE(uart5_resources),
1032 };
1033
1034 static inline void configure_usart5_pins(void)
1035 {
1036 at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
1037 at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
1038 }
1039
1040 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1041 struct platform_device *atmel_default_console_device; /* the serial console device */
1042
1043 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1044 {
1045 struct platform_device *pdev;
1046
1047 switch (id) {
1048 case 0: /* DBGU */
1049 pdev = &at91sam9260_dbgu_device;
1050 configure_dbgu_pins();
1051 at91_clock_associate("mck", &pdev->dev, "usart");
1052 break;
1053 case AT91SAM9260_ID_US0:
1054 pdev = &at91sam9260_uart0_device;
1055 configure_usart0_pins(pins);
1056 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1057 break;
1058 case AT91SAM9260_ID_US1:
1059 pdev = &at91sam9260_uart1_device;
1060 configure_usart1_pins(pins);
1061 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1062 break;
1063 case AT91SAM9260_ID_US2:
1064 pdev = &at91sam9260_uart2_device;
1065 configure_usart2_pins(pins);
1066 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1067 break;
1068 case AT91SAM9260_ID_US3:
1069 pdev = &at91sam9260_uart3_device;
1070 configure_usart3_pins(pins);
1071 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1072 break;
1073 case AT91SAM9260_ID_US4:
1074 pdev = &at91sam9260_uart4_device;
1075 configure_usart4_pins();
1076 at91_clock_associate("usart4_clk", &pdev->dev, "usart");
1077 break;
1078 case AT91SAM9260_ID_US5:
1079 pdev = &at91sam9260_uart5_device;
1080 configure_usart5_pins();
1081 at91_clock_associate("usart5_clk", &pdev->dev, "usart");
1082 break;
1083 default:
1084 return;
1085 }
1086 pdev->id = portnr; /* update to mapped ID */
1087
1088 if (portnr < ATMEL_MAX_UART)
1089 at91_uarts[portnr] = pdev;
1090 }
1091
1092 void __init at91_set_serial_console(unsigned portnr)
1093 {
1094 if (portnr < ATMEL_MAX_UART)
1095 atmel_default_console_device = at91_uarts[portnr];
1096 }
1097
1098 void __init at91_add_device_serial(void)
1099 {
1100 int i;
1101
1102 for (i = 0; i < ATMEL_MAX_UART; i++) {
1103 if (at91_uarts[i])
1104 platform_device_register(at91_uarts[i]);
1105 }
1106
1107 if (!atmel_default_console_device)
1108 printk(KERN_INFO "AT91: No default serial console defined.\n");
1109 }
1110 #else
1111 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1112 void __init at91_set_serial_console(unsigned portnr) {}
1113 void __init at91_add_device_serial(void) {}
1114 #endif
1115
1116
1117 /* -------------------------------------------------------------------- */
1118 /*
1119 * These devices are always present and don't need any board-specific
1120 * setup.
1121 */
1122 static int __init at91_add_standard_devices(void)
1123 {
1124 at91_add_device_rtt();
1125 at91_add_device_watchdog();
1126 at91_add_device_tc();
1127 return 0;
1128 }
1129
1130 arch_initcall(at91_add_standard_devices);
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