arch/arm/mach-at91/include/mach/uncompress.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/uncompress.h
   3  *
   4  * Copyright (C) 2003 SAN People
   5  * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #ifndef __ASM_ARCH_UNCOMPRESS_H
  23 #define __ASM_ARCH_UNCOMPRESS_H
  24
  25 #include <linux/io.h>
  26 #include <linux/atmel_serial.h>
  27 #include <mach/hardware.h>
  28
  29 #include <mach/at91_dbgu.h>
  30 #include <mach/cpu.h>
  31
  32 void __iomem *at91_uart;
  33
  34 static const u32 uarts_rm9200[] = {
  35         AT91_BASE_DBGU0,
  36         AT91RM9200_BASE_US0,
  37         AT91RM9200_BASE_US1,
  38         AT91RM9200_BASE_US2,
  39         AT91RM9200_BASE_US3,
  40         0,
  41 };
  42
  43 static const u32 uarts_sam9260[] = {
  44         AT91_BASE_DBGU0,
  45         AT91SAM9260_BASE_US0,
  46         AT91SAM9260_BASE_US1,
  47         AT91SAM9260_BASE_US2,
  48         AT91SAM9260_BASE_US3,
  49         AT91SAM9260_BASE_US4,
  50         AT91SAM9260_BASE_US5,
  51         0,
  52 };
  53
  54 static const u32 uarts_sam9261[] = {
  55         AT91_BASE_DBGU0,
  56         AT91SAM9261_BASE_US0,
  57         AT91SAM9261_BASE_US1,
  58         AT91SAM9261_BASE_US2,
  59         0,
  60 };
  61
  62 static const u32 uarts_sam9263[] = {
  63         AT91_BASE_DBGU1,
  64         AT91SAM9263_BASE_US0,
  65         AT91SAM9263_BASE_US1,
  66         AT91SAM9263_BASE_US2,
  67         0,
  68 };
  69
  70 static const u32 uarts_sam9g45[] = {
  71         AT91_BASE_DBGU1,
  72         AT91SAM9G45_BASE_US0,
  73         AT91SAM9G45_BASE_US1,
  74         AT91SAM9G45_BASE_US2,
  75         AT91SAM9G45_BASE_US3,
  76         0,
  77 };
  78
  79 static const u32 uarts_sam9rl[] = {
  80         AT91_BASE_DBGU0,
  81         AT91SAM9RL_BASE_US0,
  82         AT91SAM9RL_BASE_US1,
  83         AT91SAM9RL_BASE_US2,
  84         AT91SAM9RL_BASE_US3,
  85         0,
  86 };
  87
  88 static const u32 uarts_sam9x5[] = {
  89         AT91_BASE_DBGU0,
  90         AT91SAM9X5_BASE_USART0,
  91         AT91SAM9X5_BASE_USART1,
  92         AT91SAM9X5_BASE_USART2,
  93         0,
  94 };
  95
  96 static const u32 uarts_sama5d3[] = {
  97         AT91_BASE_DBGU1,
  98         SAMA5D3_BASE_USART0,
  99         SAMA5D3_BASE_USART1,
 100         SAMA5D3_BASE_USART2,
 101         SAMA5D3_BASE_USART3,
 102         0,
 103 };
 104
 105 static const u32 uarts_sama5d4[] = {
 106         AT91_BASE_DBGU2,
 107         SAMA5D4_BASE_USART3,
 108         0,
 109 };
 110
 111 static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
 112 {
 113         u32 cidr, socid;
 114
 115         cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
 116         socid = cidr & ~AT91_CIDR_VERSION;
 117
 118         switch (socid) {
 119         case ARCH_ID_AT91RM9200:
 120                 return uarts_rm9200;
 121
 122         case ARCH_ID_AT91SAM9G20:
 123         case ARCH_ID_AT91SAM9260:
 124                 return uarts_sam9260;
 125
 126         case ARCH_ID_AT91SAM9261:
 127                 return uarts_sam9261;
 128
 129         case ARCH_ID_AT91SAM9263:
 130                 return uarts_sam9263;
 131
 132         case ARCH_ID_AT91SAM9G45:
 133                 return uarts_sam9g45;
 134
 135         case ARCH_ID_AT91SAM9RL64:
 136                 return uarts_sam9rl;
 137
 138         case ARCH_ID_AT91SAM9N12:
 139         case ARCH_ID_AT91SAM9X5:
 140                 return uarts_sam9x5;
 141
 142         case ARCH_ID_SAMA5:
 143                 cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
 144                 if (cidr & ARCH_EXID_SAMA5D3)
 145                         return uarts_sama5d3;
 146                 else if (cidr & ARCH_EXID_SAMA5D4)
 147                         return uarts_sama5d4;
 148
 149                 break;
 150         }
 151
 152         /* at91sam9g10 */
 153         if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 154                 return uarts_sam9261;
 155         }
 156         /* at91sam9xe */
 157         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 158                 return uarts_sam9260;
 159         }
 160
 161         return NULL;
 162 }
 163
 164 static inline void arch_decomp_setup(void)
 165 {
 166         int i = 0;
 167         const u32* usarts;
 168
 169         usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
 170         if (!usarts)
 171                 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
 172         if (!usarts)
 173                 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
 174         if (!usarts) {
 175                 at91_uart = NULL;
 176                 return;
 177         }
 178
 179         do {
 180                 /* physical address */
 181                 at91_uart = (void __iomem *)usarts[i];
 182
 183                 if (__raw_readl(at91_uart + ATMEL_US_BRGR))
 184                         return;
 185                 i++;
 186         } while (usarts[i]);
 187
 188         at91_uart = NULL;
 189 }
 190
 191 /*
 192  * The following code assumes the serial port has already been
 193  * initialized by the bootloader.  If you didn't setup a port in
 194  * your bootloader then nothing will appear (which might be desired).
 195  *
 196  * This does not append a newline
 197  */
 198 static void putc(int c)
 199 {
 200         if (!at91_uart)
 201                 return;
 202
 203         while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
 204                 barrier();
 205         __raw_writel(c, at91_uart + ATMEL_US_THR);
 206 }
 207
 208 static inline void flush(void)
 209 {
 210         if (!at91_uart)
 211                 return;
 212
 213         /* wait for transmission to complete */
 214         while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
 215                 barrier();
 216 }
 217
 218 #endif