2 * linux/arch/arm/mach-at91rm9200/clock.c
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/debugfs.h>
18 #include <linux/seq_file.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/spinlock.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
26 #include <asm/semaphore.h>
28 #include <asm/mach-types.h>
30 #include <asm/arch/hardware.h>
31 #include <asm/arch/board.h> /* for master clock global */
38 * There's a lot more which can be done with clocks, including cpufreq
39 * integration, slow clock mode support (for system suspend), letting
40 * PLLB be used at other rates (on boards that don't need USB), etc.
45 unsigned long rate_hz
;
48 void (*mode
)(struct clk
*, int);
49 unsigned id
:2; /* PCK0..3, or 32k/main/a/b */
52 unsigned programmable
:1;
56 static spinlock_t clk_lock
;
57 static u32 at91_pllb_usb_init
;
60 * Four primary clock sources: two crystal oscillators (32K, main), and
61 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
62 * 48 MHz (unless no USB function clocks are needed). The main clock and
63 * both PLLs are turned off to run in "slow clock mode" (system suspend).
65 static struct clk clk32k
= {
67 .rate_hz
= AT91_SLOW_CLOCK
,
68 .users
= 1, /* always on */
72 static struct clk main_clk
= {
74 .pmc_mask
= 1 << 0, /* in PMC_SR */
79 static struct clk plla
= {
82 .pmc_mask
= 1 << 1, /* in PMC_SR */
88 static void pllb_mode(struct clk
*clk
, int is_on
)
93 is_on
= AT91_PMC_LOCKB
;
94 value
= at91_pllb_usb_init
;
98 at91_sys_write(AT91_CKGR_PLLBR
, value
);
102 } while ((at91_sys_read(AT91_PMC_SR
) & AT91_PMC_LOCKB
) != is_on
);
105 static struct clk pllb
= {
108 .pmc_mask
= 1 << 2, /* in PMC_SR */
115 static void pmc_sys_mode(struct clk
*clk
, int is_on
)
118 at91_sys_write(AT91_PMC_SCER
, clk
->pmc_mask
);
120 at91_sys_write(AT91_PMC_SCDR
, clk
->pmc_mask
);
123 /* USB function clocks (PLLB must be 48 MHz) */
124 static struct clk udpck
= {
127 .pmc_mask
= AT91_PMC_UDP
,
128 .mode
= pmc_sys_mode
,
130 static struct clk uhpck
= {
133 .pmc_mask
= AT91_PMC_UHP
,
134 .mode
= pmc_sys_mode
,
137 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
139 * The four programmable clocks can be parented by any primary clock.
140 * You must configure pin multiplexing to bring these signals out.
142 static struct clk pck0
= {
144 .pmc_mask
= AT91_PMC_PCK0
,
145 .mode
= pmc_sys_mode
,
149 static struct clk pck1
= {
151 .pmc_mask
= AT91_PMC_PCK1
,
152 .mode
= pmc_sys_mode
,
156 static struct clk pck2
= {
158 .pmc_mask
= AT91_PMC_PCK2
,
159 .mode
= pmc_sys_mode
,
163 static struct clk pck3
= {
165 .pmc_mask
= AT91_PMC_PCK3
,
166 .mode
= pmc_sys_mode
,
170 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
174 * The master clock is divided from the CPU clock (by 1-4). It's used for
175 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
176 * (e.g baud rate generation). It's sourced from one of the primary clocks.
178 static struct clk mck
= {
180 .pmc_mask
= 1 << 3, /* in PMC_SR */
181 .users
= 1, /* (must be) always on */
184 static void pmc_periph_mode(struct clk
*clk
, int is_on
)
187 at91_sys_write(AT91_PMC_PCER
, clk
->pmc_mask
);
189 at91_sys_write(AT91_PMC_PCDR
, clk
->pmc_mask
);
192 static struct clk udc_clk
= {
195 .pmc_mask
= 1 << AT91_ID_UDP
,
196 .mode
= pmc_periph_mode
,
198 static struct clk ohci_clk
= {
201 .pmc_mask
= 1 << AT91_ID_UHP
,
202 .mode
= pmc_periph_mode
,
204 static struct clk ether_clk
= {
207 .pmc_mask
= 1 << AT91_ID_EMAC
,
208 .mode
= pmc_periph_mode
,
210 static struct clk mmc_clk
= {
213 .pmc_mask
= 1 << AT91_ID_MCI
,
214 .mode
= pmc_periph_mode
,
216 static struct clk twi_clk
= {
219 .pmc_mask
= 1 << AT91_ID_TWI
,
220 .mode
= pmc_periph_mode
,
222 static struct clk usart0_clk
= {
223 .name
= "usart0_clk",
225 .pmc_mask
= 1 << AT91_ID_US0
,
226 .mode
= pmc_periph_mode
,
228 static struct clk usart1_clk
= {
229 .name
= "usart1_clk",
231 .pmc_mask
= 1 << AT91_ID_US1
,
232 .mode
= pmc_periph_mode
,
234 static struct clk usart2_clk
= {
235 .name
= "usart2_clk",
237 .pmc_mask
= 1 << AT91_ID_US2
,
238 .mode
= pmc_periph_mode
,
240 static struct clk usart3_clk
= {
241 .name
= "usart3_clk",
243 .pmc_mask
= 1 << AT91_ID_US3
,
244 .mode
= pmc_periph_mode
,
246 static struct clk spi_clk
= {
249 .pmc_mask
= 1 << AT91_ID_SPI
,
250 .mode
= pmc_periph_mode
,
253 static struct clk
*const clock_list
[] = {
254 /* four primary clocks -- MUST BE FIRST! */
260 /* PLLB children (USB) */
264 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
265 /* programmable clocks */
270 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
272 /* MCK and peripherals */
289 /* clocks are all static for now; no refcounting necessary */
290 struct clk
*clk_get(struct device
*dev
, const char *id
)
294 for (i
= 0; i
< ARRAY_SIZE(clock_list
); i
++) {
295 if (strcmp(id
, clock_list
[i
]->name
) == 0)
296 return clock_list
[i
];
299 return ERR_PTR(-ENOENT
);
301 EXPORT_SYMBOL(clk_get
);
303 void clk_put(struct clk
*clk
)
306 EXPORT_SYMBOL(clk_put
);
308 static void __clk_enable(struct clk
*clk
)
311 __clk_enable(clk
->parent
);
312 if (clk
->users
++ == 0 && clk
->mode
)
316 int clk_enable(struct clk
*clk
)
320 spin_lock_irqsave(&clk_lock
, flags
);
322 spin_unlock_irqrestore(&clk_lock
, flags
);
325 EXPORT_SYMBOL(clk_enable
);
327 static void __clk_disable(struct clk
*clk
)
329 BUG_ON(clk
->users
== 0);
330 if (--clk
->users
== 0 && clk
->mode
)
333 __clk_disable(clk
->parent
);
336 void clk_disable(struct clk
*clk
)
340 spin_lock_irqsave(&clk_lock
, flags
);
342 spin_unlock_irqrestore(&clk_lock
, flags
);
344 EXPORT_SYMBOL(clk_disable
);
346 unsigned long clk_get_rate(struct clk
*clk
)
351 spin_lock_irqsave(&clk_lock
, flags
);
354 if (rate
|| !clk
->parent
)
358 spin_unlock_irqrestore(&clk_lock
, flags
);
361 EXPORT_SYMBOL(clk_get_rate
);
363 /*------------------------------------------------------------------------*/
365 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
368 * For now, only the programmable clocks support reparenting (MCK could
369 * do this too, with care) or rate changing (the PLLs could do this too,
370 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
371 * a better rate match; we don't.
374 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
378 unsigned long actual
;
380 if (!clk
->programmable
)
382 spin_lock_irqsave(&clk_lock
, flags
);
384 actual
= clk
->parent
->rate_hz
;
385 for (prescale
= 0; prescale
< 7; prescale
++) {
386 if (actual
&& actual
<= rate
)
391 spin_unlock_irqrestore(&clk_lock
, flags
);
392 return (prescale
< 7) ? actual
: -ENOENT
;
394 EXPORT_SYMBOL(clk_round_rate
);
396 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
400 unsigned long actual
;
402 if (!clk
->programmable
)
406 spin_lock_irqsave(&clk_lock
, flags
);
408 actual
= clk
->parent
->rate_hz
;
409 for (prescale
= 0; prescale
< 7; prescale
++) {
410 if (actual
&& actual
<= rate
) {
413 pckr
= at91_sys_read(AT91_PMC_PCKR(clk
->id
));
414 pckr
&= AT91_PMC_CSS_PLLB
; /* clock selection */
415 pckr
|= prescale
<< 2;
416 at91_sys_write(AT91_PMC_PCKR(clk
->id
), pckr
);
417 clk
->rate_hz
= actual
;
423 spin_unlock_irqrestore(&clk_lock
, flags
);
424 return (prescale
< 7) ? actual
: -ENOENT
;
426 EXPORT_SYMBOL(clk_set_rate
);
428 struct clk
*clk_get_parent(struct clk
*clk
)
432 EXPORT_SYMBOL(clk_get_parent
);
434 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
440 if (!parent
->primary
|| !clk
->programmable
)
442 spin_lock_irqsave(&clk_lock
, flags
);
444 clk
->rate_hz
= parent
->rate_hz
;
445 clk
->parent
= parent
;
446 at91_sys_write(AT91_PMC_PCKR(clk
->id
), parent
->id
);
448 spin_unlock_irqrestore(&clk_lock
, flags
);
451 EXPORT_SYMBOL(clk_set_parent
);
453 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
455 /*------------------------------------------------------------------------*/
457 #ifdef CONFIG_DEBUG_FS
459 static int at91_clk_show(struct seq_file
*s
, void *unused
)
464 seq_printf(s
, "SCSR = %8x\n", scsr
= at91_sys_read(AT91_PMC_SCSR
));
465 seq_printf(s
, "PCSR = %8x\n", pcsr
= at91_sys_read(AT91_PMC_PCSR
));
467 seq_printf(s
, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR
));
468 seq_printf(s
, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR
));
469 seq_printf(s
, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR
));
470 seq_printf(s
, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR
));
472 seq_printf(s
, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR
));
473 for (i
= 0; i
< 4; i
++)
474 seq_printf(s
, "PCK%d = %8x\n", i
, at91_sys_read(AT91_PMC_PCKR(i
)));
475 seq_printf(s
, "SR = %8x\n", sr
= at91_sys_read(AT91_PMC_SR
));
479 for (i
= 0; i
< ARRAY_SIZE(clock_list
); i
++) {
481 struct clk
*clk
= clock_list
[i
];
483 if (clk
->mode
== pmc_sys_mode
)
484 state
= (scsr
& clk
->pmc_mask
) ? "on" : "off";
485 else if (clk
->mode
== pmc_periph_mode
)
486 state
= (pcsr
& clk
->pmc_mask
) ? "on" : "off";
487 else if (clk
->pmc_mask
)
488 state
= (sr
& clk
->pmc_mask
) ? "on" : "off";
489 else if (clk
== &clk32k
|| clk
== &main_clk
)
494 seq_printf(s
, "%-10s users=%2d %-3s %9ld Hz %s\n",
495 clk
->name
, clk
->users
, state
, clk_get_rate(clk
),
496 clk
->parent
? clk
->parent
->name
: "");
501 static int at91_clk_open(struct inode
*inode
, struct file
*file
)
503 return single_open(file
, at91_clk_show
, NULL
);
506 static struct file_operations at91_clk_operations
= {
507 .open
= at91_clk_open
,
510 .release
= single_release
,
513 static int __init
at91_clk_debugfs_init(void)
515 /* /sys/kernel/debug/at91_clk */
516 (void) debugfs_create_file("at91_clk", S_IFREG
| S_IRUGO
, NULL
, NULL
, &at91_clk_operations
);
520 postcore_initcall(at91_clk_debugfs_init
);
524 /*------------------------------------------------------------------------*/
526 static u32 __init
at91_pll_rate(struct clk
*pll
, u32 freq
, u32 reg
)
531 mul
= (reg
>> 16) & 0x7ff;
541 static u32 __init
at91_usb_rate(struct clk
*pll
, u32 freq
, u32 reg
)
543 if (pll
== &pllb
&& (reg
& AT91_PMC_USB96M
))
549 static unsigned __init
at91_pll_calc(unsigned main_freq
, unsigned out_freq
)
551 unsigned i
, div
= 0, mul
= 0, diff
= 1 << 30;
552 unsigned ret
= (out_freq
> 155000000) ? 0xbe00 : 0x3e00;
554 /* PLL output max 240 MHz (or 180 MHz per errata) */
555 if (out_freq
> 240000000)
558 for (i
= 1; i
< 256; i
++) {
560 unsigned input
, mul1
;
563 * PLL input between 1MHz and 32MHz per spec, but lower
564 * frequences seem necessary in some cases so allow 100K.
566 input
= main_freq
/ i
;
569 if (input
> 32000000)
572 mul1
= out_freq
/ input
;
578 diff1
= out_freq
- input
* mul1
;
589 if (i
== 256 && diff
> (out_freq
>> 5))
591 return ret
| ((mul
- 1) << 16) | div
;
596 int __init
at91_clock_init(unsigned long main_clock
)
598 unsigned tmp
, freq
, mckr
;
600 spin_lock_init(&clk_lock
);
603 * When the bootloader initialized the main oscillator correctly,
604 * there's no problem using the cycle counter. But if it didn't,
605 * or when using oscillator bypass mode, we must be told the speed
610 tmp
= at91_sys_read(AT91_CKGR_MCFR
);
611 } while (!(tmp
& AT91_PMC_MAINRDY
));
612 main_clock
= (tmp
& AT91_PMC_MAINF
) * (AT91_SLOW_CLOCK
/ 16);
614 main_clk
.rate_hz
= main_clock
;
616 /* report if PLLA is more than mildly overclocked */
617 plla
.rate_hz
= at91_pll_rate(&plla
, main_clock
, at91_sys_read(AT91_CKGR_PLLAR
));
618 if (plla
.rate_hz
> 209000000)
619 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla
.rate_hz
/ 1000000);
622 * USB clock init: choose 48 MHz PLLB value, turn all clocks off,
623 * disable 48MHz clock during usb peripheral suspend.
625 * REVISIT: assumes MCK doesn't derive from PLLB!
627 at91_pllb_usb_init
= at91_pll_calc(main_clock
, 48000000 * 2) | AT91_PMC_USB96M
;
628 pllb
.rate_hz
= at91_pll_rate(&pllb
, main_clock
, at91_pllb_usb_init
);
629 at91_sys_write(AT91_PMC_PCDR
, (1 << AT91_ID_UHP
) | (1 << AT91_ID_UDP
));
630 at91_sys_write(AT91_PMC_SCDR
, AT91_PMC_UHP
| AT91_PMC_UDP
);
631 at91_sys_write(AT91_CKGR_PLLBR
, 0);
632 at91_sys_write(AT91_PMC_SCER
, AT91_PMC_MCKUDP
);
634 udpck
.rate_hz
= at91_usb_rate(&pllb
, pllb
.rate_hz
, at91_pllb_usb_init
);
635 uhpck
.rate_hz
= at91_usb_rate(&pllb
, pllb
.rate_hz
, at91_pllb_usb_init
);
638 * MCK and CPU derive from one of those primary clocks.
639 * For now, assume this parentage won't change.
641 mckr
= at91_sys_read(AT91_PMC_MCKR
);
642 mck
.parent
= clock_list
[mckr
& AT91_PMC_CSS
];
644 freq
= mck
.parent
->rate_hz
;
645 freq
/= (1 << ((mckr
>> 2) & 3)); /* prescale */
646 mck
.rate_hz
= freq
/ (1 + ((mckr
>> 8) & 3)); /* mdiv */
648 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
649 freq
/ 1000000, (unsigned) mck
.rate_hz
/ 1000000,
650 (unsigned) main_clock
/ 1000000,
651 ((unsigned) main_clock
% 1000000) / 1000);
653 /* FIXME get rid of master_clock global */
654 at91_master_clock
= mck
.rate_hz
;
656 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
657 /* establish PCK0..PCK3 parentage */
658 for (tmp
= 0; tmp
< ARRAY_SIZE(clock_list
); tmp
++) {
659 struct clk
*clk
= clock_list
[tmp
], *parent
;
662 if (!clk
->programmable
)
665 pckr
= at91_sys_read(AT91_PMC_PCKR(clk
->id
));
666 parent
= clock_list
[pckr
& 3];
667 clk
->parent
= parent
;
668 clk
->rate_hz
= parent
->rate_hz
/ (1 << ((pckr
>> 2) & 3));
671 /* disable unused clocks */
672 at91_sys_write(AT91_PMC_SCDR
, AT91_PMC_PCK0
| AT91_PMC_PCK1
| AT91_PMC_PCK2
| AT91_PMC_PCK3
);
673 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
675 /* FIXME several unused clocks may still be active... provide
676 * a CONFIG option to turn off all unused clocks at some point
677 * before driver init starts.