arch/arm/mach-at91rm9200/clock.c

   1 /*
   2  * linux/arch/arm/mach-at91rm9200/clock.c
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  * Copyright (C) 2005 Ivan Kokshaysky
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/fs.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/list.h>
  20 #include <linux/errno.h>
  21 #include <linux/err.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25
  26 #include <asm/semaphore.h>
  27 #include <asm/io.h>
  28 #include <asm/mach-types.h>
  29
  30 #include <asm/arch/hardware.h>
  31 #include <asm/arch/board.h>             /* for master clock global */
  32
  33 #include "generic.h"
  34
  35 #undef  DEBUG
  36
  37 /*
  38  * There's a lot more which can be done with clocks, including cpufreq
  39  * integration, slow clock mode support (for system suspend), letting
  40  * PLLB be used at other rates (on boards that don't need USB), etc.
  41  */
  42
  43 struct clk {
  44         const char      *name;
  45         unsigned long   rate_hz;
  46         struct clk      *parent;
  47         u32             pmc_mask;
  48         void            (*mode)(struct clk *, int);
  49         unsigned        id:2;           /* PCK0..3, or 32k/main/a/b */
  50         unsigned        primary:1;
  51         unsigned        pll:1;
  52         unsigned        programmable:1;
  53         u16             users;
  54 };
  55
  56 static spinlock_t       clk_lock;
  57 static u32              at91_pllb_usb_init;
  58
  59 /*
  60  * Four primary clock sources:  two crystal oscillators (32K, main), and
  61  * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
  62  * 48 MHz (unless no USB function clocks are needed).  The main clock and
  63  * both PLLs are turned off to run in "slow clock mode" (system suspend).
  64  */
  65 static struct clk clk32k = {
  66         .name           = "clk32k",
  67         .rate_hz        = AT91_SLOW_CLOCK,
  68         .users          = 1,            /* always on */
  69         .id             = 0,
  70         .primary        = 1,
  71 };
  72 static struct clk main_clk = {
  73         .name           = "main",
  74         .pmc_mask       = 1 << 0,       /* in PMC_SR */
  75         .users          = 1,
  76         .id             = 1,
  77         .primary        = 1,
  78 };
  79 static struct clk plla = {
  80         .name           = "plla",
  81         .parent         = &main_clk,
  82         .pmc_mask       = 1 << 1,       /* in PMC_SR */
  83         .id             = 2,
  84         .primary        = 1,
  85         .pll            = 1,
  86 };
  87
  88 static void pllb_mode(struct clk *clk, int is_on)
  89 {
  90         u32     value;
  91
  92         if (is_on) {
  93                 is_on = AT91_PMC_LOCKB;
  94                 value = at91_pllb_usb_init;
  95         } else
  96                 value = 0;
  97
  98         at91_sys_write(AT91_CKGR_PLLBR, value);
  99
 100         do {
 101                 cpu_relax();
 102         } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
 103 }
 104
 105 static struct clk pllb = {
 106         .name           = "pllb",
 107         .parent         = &main_clk,
 108         .pmc_mask       = 1 << 2,       /* in PMC_SR */
 109         .mode           = pllb_mode,
 110         .id             = 3,
 111         .primary        = 1,
 112         .pll            = 1,
 113 };
 114
 115 static void pmc_sys_mode(struct clk *clk, int is_on)
 116 {
 117         if (is_on)
 118                 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
 119         else
 120                 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
 121 }
 122
 123 /* USB function clocks (PLLB must be 48 MHz) */
 124 static struct clk udpck = {
 125         .name           = "udpck",
 126         .parent         = &pllb,
 127         .pmc_mask       = AT91_PMC_UDP,
 128         .mode           = pmc_sys_mode,
 129 };
 130 static struct clk uhpck = {
 131         .name           = "uhpck",
 132         .parent         = &pllb,
 133         .pmc_mask       = AT91_PMC_UHP,
 134         .mode           = pmc_sys_mode,
 135 };
 136
 137 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 138 /*
 139  * The four programmable clocks can be parented by any primary clock.
 140  * You must configure pin multiplexing to bring these signals out.
 141  */
 142 static struct clk pck0 = {
 143         .name           = "pck0",
 144         .pmc_mask       = AT91_PMC_PCK0,
 145         .mode           = pmc_sys_mode,
 146         .programmable   = 1,
 147         .id             = 0,
 148 };
 149 static struct clk pck1 = {
 150         .name           = "pck1",
 151         .pmc_mask       = AT91_PMC_PCK1,
 152         .mode           = pmc_sys_mode,
 153         .programmable   = 1,
 154         .id             = 1,
 155 };
 156 static struct clk pck2 = {
 157         .name           = "pck2",
 158         .pmc_mask       = AT91_PMC_PCK2,
 159         .mode           = pmc_sys_mode,
 160         .programmable   = 1,
 161         .id             = 2,
 162 };
 163 static struct clk pck3 = {
 164         .name           = "pck3",
 165         .pmc_mask       = AT91_PMC_PCK3,
 166         .mode           = pmc_sys_mode,
 167         .programmable   = 1,
 168         .id             = 3,
 169 };
 170 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
 171
 172
 173 /*
 174  * The master clock is divided from the CPU clock (by 1-4).  It's used for
 175  * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 176  * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 177  */
 178 static struct clk mck = {
 179         .name           = "mck",
 180         .pmc_mask       = 1 << 3,       /* in PMC_SR */
 181         .users          = 1,            /* (must be) always on */
 182 };
 183
 184 static void pmc_periph_mode(struct clk *clk, int is_on)
 185 {
 186         if (is_on)
 187                 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
 188         else
 189                 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
 190 }
 191
 192 static struct clk udc_clk = {
 193         .name           = "udc_clk",
 194         .parent         = &mck,
 195         .pmc_mask       = 1 << AT91_ID_UDP,
 196         .mode           = pmc_periph_mode,
 197 };
 198 static struct clk ohci_clk = {
 199         .name           = "ohci_clk",
 200         .parent         = &mck,
 201         .pmc_mask       = 1 << AT91_ID_UHP,
 202         .mode           = pmc_periph_mode,
 203 };
 204 static struct clk ether_clk = {
 205         .name           = "ether_clk",
 206         .parent         = &mck,
 207         .pmc_mask       = 1 << AT91_ID_EMAC,
 208         .mode           = pmc_periph_mode,
 209 };
 210 static struct clk mmc_clk = {
 211         .name           = "mci_clk",
 212         .parent         = &mck,
 213         .pmc_mask       = 1 << AT91_ID_MCI,
 214         .mode           = pmc_periph_mode,
 215 };
 216 static struct clk twi_clk = {
 217         .name           = "twi_clk",
 218         .parent         = &mck,
 219         .pmc_mask       = 1 << AT91_ID_TWI,
 220         .mode           = pmc_periph_mode,
 221 };
 222 static struct clk usart0_clk = {
 223         .name           = "usart0_clk",
 224         .parent         = &mck,
 225         .pmc_mask       = 1 << AT91_ID_US0,
 226         .mode           = pmc_periph_mode,
 227 };
 228 static struct clk usart1_clk = {
 229         .name           = "usart1_clk",
 230         .parent         = &mck,
 231         .pmc_mask       = 1 << AT91_ID_US1,
 232         .mode           = pmc_periph_mode,
 233 };
 234 static struct clk usart2_clk = {
 235         .name           = "usart2_clk",
 236         .parent         = &mck,
 237         .pmc_mask       = 1 << AT91_ID_US2,
 238         .mode           = pmc_periph_mode,
 239 };
 240 static struct clk usart3_clk = {
 241         .name           = "usart3_clk",
 242         .parent         = &mck,
 243         .pmc_mask       = 1 << AT91_ID_US3,
 244         .mode           = pmc_periph_mode,
 245 };
 246 static struct clk spi_clk = {
 247         .name           = "spi0_clk",
 248         .parent         = &mck,
 249         .pmc_mask       = 1 << AT91_ID_SPI,
 250         .mode           = pmc_periph_mode,
 251 };
 252
 253 static struct clk *const clock_list[] = {
 254         /* four primary clocks -- MUST BE FIRST! */
 255         &clk32k,
 256         &main_clk,
 257         &plla,
 258         &pllb,
 259
 260         /* PLLB children (USB) */
 261         &udpck,
 262         &uhpck,
 263
 264 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 265         /* programmable clocks */
 266         &pck0,
 267         &pck1,
 268         &pck2,
 269         &pck3,
 270 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
 271
 272         /* MCK and peripherals */
 273         &mck,
 274         &usart0_clk,
 275         &usart1_clk,
 276         &usart2_clk,
 277         &usart3_clk,
 278         &mmc_clk,
 279         &udc_clk,
 280         &twi_clk,
 281         &spi_clk,
 282         // ssc0..ssc2
 283         // tc0..tc5
 284         &ohci_clk,
 285         &ether_clk,
 286 };
 287
 288
 289 /* clocks are all static for now; no refcounting necessary */
 290 struct clk *clk_get(struct device *dev, const char *id)
 291 {
 292         int i;
 293
 294         for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
 295                 if (strcmp(id, clock_list[i]->name) == 0)
 296                         return clock_list[i];
 297         }
 298
 299         return ERR_PTR(-ENOENT);
 300 }
 301 EXPORT_SYMBOL(clk_get);
 302
 303 void clk_put(struct clk *clk)
 304 {
 305 }
 306 EXPORT_SYMBOL(clk_put);
 307
 308 static void __clk_enable(struct clk *clk)
 309 {
 310         if (clk->parent)
 311                 __clk_enable(clk->parent);
 312         if (clk->users++ == 0 && clk->mode)
 313                 clk->mode(clk, 1);
 314 }
 315
 316 int clk_enable(struct clk *clk)
 317 {
 318         unsigned long   flags;
 319
 320         spin_lock_irqsave(&clk_lock, flags);
 321         __clk_enable(clk);
 322         spin_unlock_irqrestore(&clk_lock, flags);
 323         return 0;
 324 }
 325 EXPORT_SYMBOL(clk_enable);
 326
 327 static void __clk_disable(struct clk *clk)
 328 {
 329         BUG_ON(clk->users == 0);
 330         if (--clk->users == 0 && clk->mode)
 331                 clk->mode(clk, 0);
 332         if (clk->parent)
 333                 __clk_disable(clk->parent);
 334 }
 335
 336 void clk_disable(struct clk *clk)
 337 {
 338         unsigned long   flags;
 339
 340         spin_lock_irqsave(&clk_lock, flags);
 341         __clk_disable(clk);
 342         spin_unlock_irqrestore(&clk_lock, flags);
 343 }
 344 EXPORT_SYMBOL(clk_disable);
 345
 346 unsigned long clk_get_rate(struct clk *clk)
 347 {
 348         unsigned long   flags;
 349         unsigned long   rate;
 350
 351         spin_lock_irqsave(&clk_lock, flags);
 352         for (;;) {
 353                 rate = clk->rate_hz;
 354                 if (rate || !clk->parent)
 355                         break;
 356                 clk = clk->parent;
 357         }
 358         spin_unlock_irqrestore(&clk_lock, flags);
 359         return rate;
 360 }
 361 EXPORT_SYMBOL(clk_get_rate);
 362
 363 /*------------------------------------------------------------------------*/
 364
 365 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 366
 367 /*
 368  * For now, only the programmable clocks support reparenting (MCK could
 369  * do this too, with care) or rate changing (the PLLs could do this too,
 370  * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 371  * a better rate match; we don't.
 372  */
 373
 374 long clk_round_rate(struct clk *clk, unsigned long rate)
 375 {
 376         unsigned long   flags;
 377         unsigned        prescale;
 378         unsigned long   actual;
 379
 380         if (!clk->programmable)
 381                 return -EINVAL;
 382         spin_lock_irqsave(&clk_lock, flags);
 383
 384         actual = clk->parent->rate_hz;
 385         for (prescale = 0; prescale < 7; prescale++) {
 386                 if (actual && actual <= rate)
 387                         break;
 388                 actual >>= 1;
 389         }
 390
 391         spin_unlock_irqrestore(&clk_lock, flags);
 392         return (prescale < 7) ? actual : -ENOENT;
 393 }
 394 EXPORT_SYMBOL(clk_round_rate);
 395
 396 int clk_set_rate(struct clk *clk, unsigned long rate)
 397 {
 398         unsigned long   flags;
 399         unsigned        prescale;
 400         unsigned long   actual;
 401
 402         if (!clk->programmable)
 403                 return -EINVAL;
 404         if (clk->users)
 405                 return -EBUSY;
 406         spin_lock_irqsave(&clk_lock, flags);
 407
 408         actual = clk->parent->rate_hz;
 409         for (prescale = 0; prescale < 7; prescale++) {
 410                 if (actual && actual <= rate) {
 411                         u32     pckr;
 412
 413                         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 414                         pckr &= AT91_PMC_CSS_PLLB;      /* clock selection */
 415                         pckr |= prescale << 2;
 416                         at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
 417                         clk->rate_hz = actual;
 418                         break;
 419                 }
 420                 actual >>= 1;
 421         }
 422
 423         spin_unlock_irqrestore(&clk_lock, flags);
 424         return (prescale < 7) ? actual : -ENOENT;
 425 }
 426 EXPORT_SYMBOL(clk_set_rate);
 427
 428 struct clk *clk_get_parent(struct clk *clk)
 429 {
 430         return clk->parent;
 431 }
 432 EXPORT_SYMBOL(clk_get_parent);
 433
 434 int clk_set_parent(struct clk *clk, struct clk *parent)
 435 {
 436         unsigned long   flags;
 437
 438         if (clk->users)
 439                 return -EBUSY;
 440         if (!parent->primary || !clk->programmable)
 441                 return -EINVAL;
 442         spin_lock_irqsave(&clk_lock, flags);
 443
 444         clk->rate_hz = parent->rate_hz;
 445         clk->parent = parent;
 446         at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
 447
 448         spin_unlock_irqrestore(&clk_lock, flags);
 449         return 0;
 450 }
 451 EXPORT_SYMBOL(clk_set_parent);
 452
 453 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
 454
 455 /*------------------------------------------------------------------------*/
 456
 457 #ifdef CONFIG_DEBUG_FS
 458
 459 static int at91_clk_show(struct seq_file *s, void *unused)
 460 {
 461         u32             scsr, pcsr, sr;
 462         unsigned        i;
 463
 464         seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
 465         seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
 466
 467         seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
 468         seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
 469         seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
 470         seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
 471
 472         seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
 473         for (i = 0; i < 4; i++)
 474                 seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
 475         seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
 476
 477         seq_printf(s, "\n");
 478
 479         for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
 480                 char            *state;
 481                 struct clk      *clk = clock_list[i];
 482
 483                 if (clk->mode == pmc_sys_mode)
 484                         state = (scsr & clk->pmc_mask) ? "on" : "off";
 485                 else if (clk->mode == pmc_periph_mode)
 486                         state = (pcsr & clk->pmc_mask) ? "on" : "off";
 487                 else if (clk->pmc_mask)
 488                         state = (sr & clk->pmc_mask) ? "on" : "off";
 489                 else if (clk == &clk32k || clk == &main_clk)
 490                         state = "on";
 491                 else
 492                         state = "";
 493
 494                 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
 495                         clk->name, clk->users, state, clk_get_rate(clk),
 496                         clk->parent ? clk->parent->name : "");
 497         }
 498         return 0;
 499 }
 500
 501 static int at91_clk_open(struct inode *inode, struct file *file)
 502 {
 503         return single_open(file, at91_clk_show, NULL);
 504 }
 505
 506 static struct file_operations at91_clk_operations = {
 507         .open           = at91_clk_open,
 508         .read           = seq_read,
 509         .llseek         = seq_lseek,
 510         .release        = single_release,
 511 };
 512
 513 static int __init at91_clk_debugfs_init(void)
 514 {
 515         /* /sys/kernel/debug/at91_clk */
 516         (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
 517
 518         return 0;
 519 }
 520 postcore_initcall(at91_clk_debugfs_init);
 521
 522 #endif
 523
 524 /*------------------------------------------------------------------------*/
 525
 526 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
 527 {
 528         unsigned mul, div;
 529
 530         div = reg & 0xff;
 531         mul = (reg >> 16) & 0x7ff;
 532         if (div && mul) {
 533                 freq /= div;
 534                 freq *= mul + 1;
 535         } else
 536                 freq = 0;
 537
 538         return freq;
 539 }
 540
 541 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
 542 {
 543         if (pll == &pllb && (reg & AT91_PMC_USB96M))
 544                 return freq / 2;
 545         else
 546                 return freq;
 547 }
 548
 549 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
 550 {
 551         unsigned i, div = 0, mul = 0, diff = 1 << 30;
 552         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
 553
 554         /* PLL output max 240 MHz (or 180 MHz per errata) */
 555         if (out_freq > 240000000)
 556                 goto fail;
 557
 558         for (i = 1; i < 256; i++) {
 559                 int diff1;
 560                 unsigned input, mul1;
 561
 562                 /*
 563                  * PLL input between 1MHz and 32MHz per spec, but lower
 564                  * frequences seem necessary in some cases so allow 100K.
 565                  */
 566                 input = main_freq / i;
 567                 if (input < 100000)
 568                         continue;
 569                 if (input > 32000000)
 570                         continue;
 571
 572                 mul1 = out_freq / input;
 573                 if (mul1 > 2048)
 574                         continue;
 575                 if (mul1 < 2)
 576                         goto fail;
 577
 578                 diff1 = out_freq - input * mul1;
 579                 if (diff1 < 0)
 580                         diff1 = -diff1;
 581                 if (diff > diff1) {
 582                         diff = diff1;
 583                         div = i;
 584                         mul = mul1;
 585                         if (diff == 0)
 586                                 break;
 587                 }
 588         }
 589         if (i == 256 && diff > (out_freq >> 5))
 590                 goto fail;
 591         return ret | ((mul - 1) << 16) | div;
 592 fail:
 593         return 0;
 594 }
 595
 596 int __init at91_clock_init(unsigned long main_clock)
 597 {
 598         unsigned tmp, freq, mckr;
 599
 600         spin_lock_init(&clk_lock);
 601
 602         /*
 603          * When the bootloader initialized the main oscillator correctly,
 604          * there's no problem using the cycle counter.  But if it didn't,
 605          * or when using oscillator bypass mode, we must be told the speed
 606          * of the main clock.
 607          */
 608         if (!main_clock) {
 609                 do {
 610                         tmp = at91_sys_read(AT91_CKGR_MCFR);
 611                 } while (!(tmp & AT91_PMC_MAINRDY));
 612                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
 613         }
 614         main_clk.rate_hz = main_clock;
 615
 616         /* report if PLLA is more than mildly overclocked */
 617         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
 618         if (plla.rate_hz > 209000000)
 619                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 620
 621         /*
 622          * USB clock init:  choose 48 MHz PLLB value, turn all clocks off,
 623          * disable 48MHz clock during usb peripheral suspend.
 624          *
 625          * REVISIT:  assumes MCK doesn't derive from PLLB!
 626          */
 627         at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
 628         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
 629         at91_sys_write(AT91_PMC_PCDR, (1 << AT91_ID_UHP) | (1 << AT91_ID_UDP));
 630         at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP);
 631         at91_sys_write(AT91_CKGR_PLLBR, 0);
 632         at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
 633
 634         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 635         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 636
 637         /*
 638          * MCK and CPU derive from one of those primary clocks.
 639          * For now, assume this parentage won't change.
 640          */
 641         mckr = at91_sys_read(AT91_PMC_MCKR);
 642         mck.parent = clock_list[mckr & AT91_PMC_CSS];
 643         mck.parent->users++;
 644         freq = mck.parent->rate_hz;
 645         freq /= (1 << ((mckr >> 2) & 3));               /* prescale */
 646         mck.rate_hz = freq / (1 + ((mckr >> 8) & 3));   /* mdiv */
 647
 648         printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
 649                 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
 650                 (unsigned) main_clock / 1000000,
 651                 ((unsigned) main_clock % 1000000) / 1000);
 652
 653         /* FIXME get rid of master_clock global */
 654         at91_master_clock = mck.rate_hz;
 655
 656 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 657         /* establish PCK0..PCK3 parentage */
 658         for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) {
 659                 struct clk      *clk = clock_list[tmp], *parent;
 660                 u32             pckr;
 661
 662                 if (!clk->programmable)
 663                         continue;
 664
 665                 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 666                 parent = clock_list[pckr & 3];
 667                 clk->parent = parent;
 668                 clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
 669         }
 670 #else
 671         /* disable unused clocks */
 672         at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
 673 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
 674
 675         /* FIXME several unused clocks may still be active...  provide
 676          * a CONFIG option to turn off all unused clocks at some point
 677          * before driver init starts.
 678          */
 679
 680         return 0;
 681 }