2 * Broadcom STB CPU SMP and hotplug support for ARM
4 * Copyright (C) 2013-2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/init.h>
20 #include <linux/jiffies.h>
21 #include <linux/of_address.h>
22 #include <linux/of_platform.h>
23 #include <linux/printk.h>
24 #include <linux/regmap.h>
25 #include <linux/smp.h>
26 #include <linux/mfd/syscon.h>
28 #include <asm/cacheflush.h>
30 #include <asm/mach-types.h>
31 #include <asm/smp_plat.h>
36 ZONE_MAN_CLKEN_MASK
= BIT(0),
37 ZONE_MAN_RESET_CNTL_MASK
= BIT(1),
38 ZONE_MAN_MEM_PWR_MASK
= BIT(4),
39 ZONE_RESERVED_1_MASK
= BIT(5),
40 ZONE_MAN_ISO_CNTL_MASK
= BIT(6),
41 ZONE_MANUAL_CONTROL_MASK
= BIT(7),
42 ZONE_PWR_DN_REQ_MASK
= BIT(9),
43 ZONE_PWR_UP_REQ_MASK
= BIT(10),
44 ZONE_BLK_RST_ASSERT_MASK
= BIT(12),
45 ZONE_PWR_OFF_STATE_MASK
= BIT(25),
46 ZONE_PWR_ON_STATE_MASK
= BIT(26),
47 ZONE_DPG_PWR_STATE_MASK
= BIT(28),
48 ZONE_MEM_PWR_STATE_MASK
= BIT(29),
49 ZONE_RESET_STATE_MASK
= BIT(31),
50 CPU0_PWR_ZONE_CTRL_REG
= 1,
51 CPU_RESET_CONFIG_REG
= 2,
54 static void __iomem
*cpubiuctrl_block
;
55 static void __iomem
*hif_cont_block
;
56 static u32 cpu0_pwr_zone_ctrl_reg
;
57 static u32 cpu_rst_cfg_reg
;
58 static u32 hif_cont_reg
;
60 #ifdef CONFIG_HOTPLUG_CPU
62 * We must quiesce a dying CPU before it can be killed by the boot CPU. Because
63 * one or more cache may be disabled, we must flush to ensure coherency. We
64 * cannot use traditionl completion structures or spinlocks as they rely on
67 static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state
);
69 static int per_cpu_sw_state_rd(u32 cpu
)
71 sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state
, per_cpu_offset(cpu
)));
72 return per_cpu(per_cpu_sw_state
, cpu
);
75 static void per_cpu_sw_state_wr(u32 cpu
, int val
)
78 per_cpu(per_cpu_sw_state
, cpu
) = val
;
79 sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state
, per_cpu_offset(cpu
)));
82 static inline void per_cpu_sw_state_wr(u32 cpu
, int val
) { }
85 static void __iomem
*pwr_ctrl_get_base(u32 cpu
)
87 void __iomem
*base
= cpubiuctrl_block
+ cpu0_pwr_zone_ctrl_reg
;
88 base
+= (cpu_logical_map(cpu
) * 4);
92 static u32
pwr_ctrl_rd(u32 cpu
)
94 void __iomem
*base
= pwr_ctrl_get_base(cpu
);
95 return readl_relaxed(base
);
98 static void pwr_ctrl_set(unsigned int cpu
, u32 val
, u32 mask
)
100 void __iomem
*base
= pwr_ctrl_get_base(cpu
);
101 writel((readl(base
) & mask
) | val
, base
);
104 static void pwr_ctrl_clr(unsigned int cpu
, u32 val
, u32 mask
)
106 void __iomem
*base
= pwr_ctrl_get_base(cpu
);
107 writel((readl(base
) & mask
) & ~val
, base
);
110 #define POLL_TMOUT_MS 500
111 static int pwr_ctrl_wait_tmout(unsigned int cpu
, u32 set
, u32 mask
)
113 const unsigned long timeo
= jiffies
+ msecs_to_jiffies(POLL_TMOUT_MS
);
117 tmp
= pwr_ctrl_rd(cpu
) & mask
;
120 } while (time_before(jiffies
, timeo
));
122 tmp
= pwr_ctrl_rd(cpu
) & mask
;
129 static void cpu_rst_cfg_set(u32 cpu
, int set
)
132 val
= readl_relaxed(cpubiuctrl_block
+ cpu_rst_cfg_reg
);
134 val
|= BIT(cpu_logical_map(cpu
));
136 val
&= ~BIT(cpu_logical_map(cpu
));
137 writel_relaxed(val
, cpubiuctrl_block
+ cpu_rst_cfg_reg
);
140 static void cpu_set_boot_addr(u32 cpu
, unsigned long boot_addr
)
142 const int reg_ofs
= cpu_logical_map(cpu
) * 8;
143 writel_relaxed(0, hif_cont_block
+ hif_cont_reg
+ reg_ofs
);
144 writel_relaxed(boot_addr
, hif_cont_block
+ hif_cont_reg
+ 4 + reg_ofs
);
147 static void brcmstb_cpu_boot(u32 cpu
)
149 /* Mark this CPU as "up" */
150 per_cpu_sw_state_wr(cpu
, 1);
153 * Set the reset vector to point to the secondary_startup
156 cpu_set_boot_addr(cpu
, virt_to_phys(brcmstb_secondary_startup
));
159 cpu_rst_cfg_set(cpu
, 0);
162 static void brcmstb_cpu_power_on(u32 cpu
)
165 * The secondary cores power was cut, so we must go through
166 * power-on initialization.
168 pwr_ctrl_set(cpu
, ZONE_MAN_ISO_CNTL_MASK
, 0xffffff00);
169 pwr_ctrl_set(cpu
, ZONE_MANUAL_CONTROL_MASK
, -1);
170 pwr_ctrl_set(cpu
, ZONE_RESERVED_1_MASK
, -1);
172 pwr_ctrl_set(cpu
, ZONE_MAN_MEM_PWR_MASK
, -1);
174 if (pwr_ctrl_wait_tmout(cpu
, 1, ZONE_MEM_PWR_STATE_MASK
))
175 panic("ZONE_MEM_PWR_STATE_MASK set timeout");
177 pwr_ctrl_set(cpu
, ZONE_MAN_CLKEN_MASK
, -1);
179 if (pwr_ctrl_wait_tmout(cpu
, 1, ZONE_DPG_PWR_STATE_MASK
))
180 panic("ZONE_DPG_PWR_STATE_MASK set timeout");
182 pwr_ctrl_clr(cpu
, ZONE_MAN_ISO_CNTL_MASK
, -1);
183 pwr_ctrl_set(cpu
, ZONE_MAN_RESET_CNTL_MASK
, -1);
186 static int brcmstb_cpu_get_power_state(u32 cpu
)
188 int tmp
= pwr_ctrl_rd(cpu
);
189 return (tmp
& ZONE_RESET_STATE_MASK
) ? 0 : 1;
192 #ifdef CONFIG_HOTPLUG_CPU
194 static void brcmstb_cpu_die(u32 cpu
)
196 v7_exit_coherency_flush(all
);
198 per_cpu_sw_state_wr(cpu
, 0);
200 /* Sit and wait to die */
203 /* We should never get here... */
208 static int brcmstb_cpu_kill(u32 cpu
)
211 * Ordinarily, the hardware forbids power-down of CPU0 (which is good
212 * because it is the boot CPU), but this is not true when using BPCM
213 * manual mode. Consequently, we must avoid turning off CPU0 here to
214 * ensure that TI2C master reset will work.
217 pr_warn("SMP: refusing to power off CPU0\n");
221 while (per_cpu_sw_state_rd(cpu
))
224 pwr_ctrl_set(cpu
, ZONE_MANUAL_CONTROL_MASK
, -1);
225 pwr_ctrl_clr(cpu
, ZONE_MAN_RESET_CNTL_MASK
, -1);
226 pwr_ctrl_clr(cpu
, ZONE_MAN_CLKEN_MASK
, -1);
227 pwr_ctrl_set(cpu
, ZONE_MAN_ISO_CNTL_MASK
, -1);
228 pwr_ctrl_clr(cpu
, ZONE_MAN_MEM_PWR_MASK
, -1);
230 if (pwr_ctrl_wait_tmout(cpu
, 0, ZONE_MEM_PWR_STATE_MASK
))
231 panic("ZONE_MEM_PWR_STATE_MASK clear timeout");
233 pwr_ctrl_clr(cpu
, ZONE_RESERVED_1_MASK
, -1);
235 if (pwr_ctrl_wait_tmout(cpu
, 0, ZONE_DPG_PWR_STATE_MASK
))
236 panic("ZONE_DPG_PWR_STATE_MASK clear timeout");
238 /* Flush pipeline before resetting CPU */
241 /* Assert reset on the CPU */
242 cpu_rst_cfg_set(cpu
, 1);
247 #endif /* CONFIG_HOTPLUG_CPU */
249 static int __init
setup_hifcpubiuctrl_regs(struct device_node
*np
)
253 struct device_node
*syscon_np
= NULL
;
257 syscon_np
= of_parse_phandle(np
, name
, 0);
259 pr_err("can't find phandle %s\n", name
);
264 cpubiuctrl_block
= of_iomap(syscon_np
, 0);
265 if (!cpubiuctrl_block
) {
266 pr_err("iomap failed for cpubiuctrl_block\n");
271 rc
= of_property_read_u32_index(np
, name
, CPU0_PWR_ZONE_CTRL_REG
,
272 &cpu0_pwr_zone_ctrl_reg
);
274 pr_err("failed to read 1st entry from %s property (%d)\n", name
,
280 rc
= of_property_read_u32_index(np
, name
, CPU_RESET_CONFIG_REG
,
283 pr_err("failed to read 2nd entry from %s property (%d)\n", name
,
290 of_node_put(syscon_np
);
294 static int __init
setup_hifcont_regs(struct device_node
*np
)
298 struct device_node
*syscon_np
= NULL
;
300 name
= "syscon-cont";
302 syscon_np
= of_parse_phandle(np
, name
, 0);
304 pr_err("can't find phandle %s\n", name
);
309 hif_cont_block
= of_iomap(syscon_np
, 0);
310 if (!hif_cont_block
) {
311 pr_err("iomap failed for hif_cont_block\n");
316 /* Offset is at top of hif_cont_block */
320 of_node_put(syscon_np
);
324 static void __init
brcmstb_cpu_ctrl_setup(unsigned int max_cpus
)
327 struct device_node
*np
;
330 name
= "brcm,brcmstb-smpboot";
331 np
= of_find_compatible_node(NULL
, NULL
, name
);
333 pr_err("can't find compatible node %s\n", name
);
337 rc
= setup_hifcpubiuctrl_regs(np
);
341 rc
= setup_hifcont_regs(np
);
346 static int brcmstb_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
348 /* Missing the brcm,brcmstb-smpboot DT node? */
349 if (!cpubiuctrl_block
|| !hif_cont_block
)
352 /* Bring up power to the core if necessary */
353 if (brcmstb_cpu_get_power_state(cpu
) == 0)
354 brcmstb_cpu_power_on(cpu
);
356 brcmstb_cpu_boot(cpu
);
361 static struct smp_operations brcmstb_smp_ops __initdata
= {
362 .smp_prepare_cpus
= brcmstb_cpu_ctrl_setup
,
363 .smp_boot_secondary
= brcmstb_boot_secondary
,
364 #ifdef CONFIG_HOTPLUG_CPU
365 .cpu_kill
= brcmstb_cpu_kill
,
366 .cpu_die
= brcmstb_cpu_die
,
370 CPU_METHOD_OF_DECLARE(brcmstb_smp
, "brcm,brahma-b15", &brcmstb_smp_ops
);