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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / mach-davinci / board-dm365-evm.c
1 /*
2 * TI DaVinci DM365 EVM board support
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/i2c.h>
19 #include <linux/io.h>
20 #include <linux/clk.h>
21 #include <linux/i2c/at24.h>
22 #include <linux/leds.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/slab.h>
26 #include <linux/mtd/nand.h>
27 #include <linux/input.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/eeprom.h>
30
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33
34 #include <mach/mux.h>
35 #include <mach/dm365.h>
36 #include <mach/common.h>
37 #include <mach/i2c.h>
38 #include <mach/serial.h>
39 #include <mach/mmc.h>
40 #include <mach/nand.h>
41 #include <mach/keyscan.h>
42
43 #include <media/tvp514x.h>
44
45 static inline int have_imager(void)
46 {
47 /* REVISIT when it's supported, trigger via Kconfig */
48 return 0;
49 }
50
51 static inline int have_tvp7002(void)
52 {
53 /* REVISIT when it's supported, trigger via Kconfig */
54 return 0;
55 }
56
57
58 #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
59 #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
60 #define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
61
62 #define DM365_EVM_PHY_MASK (0x2)
63 #define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
64
65 /*
66 * A MAX-II CPLD is used for various board control functions.
67 */
68 #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
69
70 #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
71 #define CPLD_TEST CPLD_OFFSET(0,1)
72 #define CPLD_LEDS CPLD_OFFSET(0,2)
73 #define CPLD_MUX CPLD_OFFSET(0,3)
74 #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
75 #define CPLD_POWER CPLD_OFFSET(1,1)
76 #define CPLD_VIDEO CPLD_OFFSET(1,2)
77 #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
78
79 #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
80 #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
81
82 #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
83 #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
84 #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
85 #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
86 #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
87 #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
88 #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
89 #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
90 #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
91
92 #define CPLD_RESETS CPLD_OFFSET(4,3)
93
94 #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
95 #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
96 #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
97 #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
98 #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
99 #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
100
101 static void __iomem *cpld;
102
103
104 /* NOTE: this is geared for the standard config, with a socketed
105 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
106 * swap chips with a different block size, partitioning will
107 * need to be changed. This NAND chip MT29F16G08FAA is the default
108 * NAND shipped with the Spectrum Digital DM365 EVM
109 */
110 #define NAND_BLOCK_SIZE SZ_128K
111
112 static struct mtd_partition davinci_nand_partitions[] = {
113 {
114 /* UBL (a few copies) plus U-Boot */
115 .name = "bootloader",
116 .offset = 0,
117 .size = 28 * NAND_BLOCK_SIZE,
118 .mask_flags = MTD_WRITEABLE, /* force read-only */
119 }, {
120 /* U-Boot environment */
121 .name = "params",
122 .offset = MTDPART_OFS_APPEND,
123 .size = 2 * NAND_BLOCK_SIZE,
124 .mask_flags = 0,
125 }, {
126 .name = "kernel",
127 .offset = MTDPART_OFS_APPEND,
128 .size = SZ_4M,
129 .mask_flags = 0,
130 }, {
131 .name = "filesystem1",
132 .offset = MTDPART_OFS_APPEND,
133 .size = SZ_512M,
134 .mask_flags = 0,
135 }, {
136 .name = "filesystem2",
137 .offset = MTDPART_OFS_APPEND,
138 .size = MTDPART_SIZ_FULL,
139 .mask_flags = 0,
140 }
141 /* two blocks with bad block table (and mirror) at the end */
142 };
143
144 static struct davinci_nand_pdata davinci_nand_data = {
145 .mask_chipsel = BIT(14),
146 .parts = davinci_nand_partitions,
147 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
148 .ecc_mode = NAND_ECC_HW,
149 .options = NAND_USE_FLASH_BBT,
150 .ecc_bits = 4,
151 };
152
153 static struct resource davinci_nand_resources[] = {
154 {
155 .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
156 .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
157 .flags = IORESOURCE_MEM,
158 }, {
159 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
160 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
161 .flags = IORESOURCE_MEM,
162 },
163 };
164
165 static struct platform_device davinci_nand_device = {
166 .name = "davinci_nand",
167 .id = 0,
168 .num_resources = ARRAY_SIZE(davinci_nand_resources),
169 .resource = davinci_nand_resources,
170 .dev = {
171 .platform_data = &davinci_nand_data,
172 },
173 };
174
175 static struct at24_platform_data eeprom_info = {
176 .byte_len = (256*1024) / 8,
177 .page_size = 64,
178 .flags = AT24_FLAG_ADDR16,
179 .setup = davinci_get_mac_addr,
180 .context = (void *)0x7f00,
181 };
182
183 static struct snd_platform_data dm365_evm_snd_data;
184
185 static struct i2c_board_info i2c_info[] = {
186 {
187 I2C_BOARD_INFO("24c256", 0x50),
188 .platform_data = &eeprom_info,
189 },
190 {
191 I2C_BOARD_INFO("tlv320aic3x", 0x18),
192 },
193 };
194
195 static struct davinci_i2c_platform_data i2c_pdata = {
196 .bus_freq = 400 /* kHz */,
197 .bus_delay = 0 /* usec */,
198 };
199
200 static int dm365evm_keyscan_enable(struct device *dev)
201 {
202 return davinci_cfg_reg(DM365_KEYSCAN);
203 }
204
205 static unsigned short dm365evm_keymap[] = {
206 KEY_KP2,
207 KEY_LEFT,
208 KEY_EXIT,
209 KEY_DOWN,
210 KEY_ENTER,
211 KEY_UP,
212 KEY_KP1,
213 KEY_RIGHT,
214 KEY_MENU,
215 KEY_RECORD,
216 KEY_REWIND,
217 KEY_KPMINUS,
218 KEY_STOP,
219 KEY_FASTFORWARD,
220 KEY_KPPLUS,
221 KEY_PLAYPAUSE,
222 0
223 };
224
225 static struct davinci_ks_platform_data dm365evm_ks_data = {
226 .device_enable = dm365evm_keyscan_enable,
227 .keymap = dm365evm_keymap,
228 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
229 .rep = 1,
230 /* Scan period = strobe + interval */
231 .strobe = 0x5,
232 .interval = 0x2,
233 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
234 };
235
236 static int cpld_mmc_get_cd(int module)
237 {
238 if (!cpld)
239 return -ENXIO;
240
241 /* low == card present */
242 return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
243 }
244
245 static int cpld_mmc_get_ro(int module)
246 {
247 if (!cpld)
248 return -ENXIO;
249
250 /* high == card's write protect switch active */
251 return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
252 }
253
254 static struct davinci_mmc_config dm365evm_mmc_config = {
255 .get_cd = cpld_mmc_get_cd,
256 .get_ro = cpld_mmc_get_ro,
257 .wires = 4,
258 .max_freq = 50000000,
259 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
260 .version = MMC_CTLR_VERSION_2,
261 };
262
263 static void dm365evm_emac_configure(void)
264 {
265 /*
266 * EMAC pins are multiplexed with GPIO and UART
267 * Further details are available at the DM365 ARM
268 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
269 */
270 davinci_cfg_reg(DM365_EMAC_TX_EN);
271 davinci_cfg_reg(DM365_EMAC_TX_CLK);
272 davinci_cfg_reg(DM365_EMAC_COL);
273 davinci_cfg_reg(DM365_EMAC_TXD3);
274 davinci_cfg_reg(DM365_EMAC_TXD2);
275 davinci_cfg_reg(DM365_EMAC_TXD1);
276 davinci_cfg_reg(DM365_EMAC_TXD0);
277 davinci_cfg_reg(DM365_EMAC_RXD3);
278 davinci_cfg_reg(DM365_EMAC_RXD2);
279 davinci_cfg_reg(DM365_EMAC_RXD1);
280 davinci_cfg_reg(DM365_EMAC_RXD0);
281 davinci_cfg_reg(DM365_EMAC_RX_CLK);
282 davinci_cfg_reg(DM365_EMAC_RX_DV);
283 davinci_cfg_reg(DM365_EMAC_RX_ER);
284 davinci_cfg_reg(DM365_EMAC_CRS);
285 davinci_cfg_reg(DM365_EMAC_MDIO);
286 davinci_cfg_reg(DM365_EMAC_MDCLK);
287
288 /*
289 * EMAC interrupts are multiplexed with GPIO interrupts
290 * Details are available at the DM365 ARM
291 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
292 */
293 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
294 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
295 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
296 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
297 }
298
299 static void dm365evm_mmc_configure(void)
300 {
301 /*
302 * MMC/SD pins are multiplexed with GPIO and EMIF
303 * Further details are available at the DM365 ARM
304 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
305 */
306 davinci_cfg_reg(DM365_SD1_CLK);
307 davinci_cfg_reg(DM365_SD1_CMD);
308 davinci_cfg_reg(DM365_SD1_DATA3);
309 davinci_cfg_reg(DM365_SD1_DATA2);
310 davinci_cfg_reg(DM365_SD1_DATA1);
311 davinci_cfg_reg(DM365_SD1_DATA0);
312 }
313
314 static struct tvp514x_platform_data tvp5146_pdata = {
315 .clk_polarity = 0,
316 .hs_polarity = 1,
317 .vs_polarity = 1
318 };
319
320 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
321 /* Inputs available at the TVP5146 */
322 static struct v4l2_input tvp5146_inputs[] = {
323 {
324 .index = 0,
325 .name = "Composite",
326 .type = V4L2_INPUT_TYPE_CAMERA,
327 .std = TVP514X_STD_ALL,
328 },
329 {
330 .index = 1,
331 .name = "S-Video",
332 .type = V4L2_INPUT_TYPE_CAMERA,
333 .std = TVP514X_STD_ALL,
334 },
335 };
336
337 /*
338 * this is the route info for connecting each input to decoder
339 * ouput that goes to vpfe. There is a one to one correspondence
340 * with tvp5146_inputs
341 */
342 static struct vpfe_route tvp5146_routes[] = {
343 {
344 .input = INPUT_CVBS_VI2B,
345 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
346 },
347 {
348 .input = INPUT_SVIDEO_VI2C_VI1C,
349 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
350 },
351 };
352
353 static struct vpfe_subdev_info vpfe_sub_devs[] = {
354 {
355 .name = "tvp5146",
356 .grp_id = 0,
357 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
358 .inputs = tvp5146_inputs,
359 .routes = tvp5146_routes,
360 .can_route = 1,
361 .ccdc_if_params = {
362 .if_type = VPFE_BT656,
363 .hdpol = VPFE_PINPOL_POSITIVE,
364 .vdpol = VPFE_PINPOL_POSITIVE,
365 },
366 .board_info = {
367 I2C_BOARD_INFO("tvp5146", 0x5d),
368 .platform_data = &tvp5146_pdata,
369 },
370 },
371 };
372
373 static struct vpfe_config vpfe_cfg = {
374 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
375 .sub_devs = vpfe_sub_devs,
376 .i2c_adapter_id = 1,
377 .card_name = "DM365 EVM",
378 .ccdc = "ISIF",
379 };
380
381 static void __init evm_init_i2c(void)
382 {
383 davinci_init_i2c(&i2c_pdata);
384 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
385 }
386
387 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
388 &davinci_nand_device,
389 };
390
391 static inline int have_leds(void)
392 {
393 #ifdef CONFIG_LEDS_CLASS
394 return 1;
395 #else
396 return 0;
397 #endif
398 }
399
400 struct cpld_led {
401 struct led_classdev cdev;
402 u8 mask;
403 };
404
405 static const struct {
406 const char *name;
407 const char *trigger;
408 } cpld_leds[] = {
409 { "dm365evm::ds2", },
410 { "dm365evm::ds3", },
411 { "dm365evm::ds4", },
412 { "dm365evm::ds5", },
413 { "dm365evm::ds6", "nand-disk", },
414 { "dm365evm::ds7", "mmc1", },
415 { "dm365evm::ds8", "mmc0", },
416 { "dm365evm::ds9", "heartbeat", },
417 };
418
419 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
420 {
421 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
422 u8 reg = __raw_readb(cpld + CPLD_LEDS);
423
424 if (b != LED_OFF)
425 reg &= ~led->mask;
426 else
427 reg |= led->mask;
428 __raw_writeb(reg, cpld + CPLD_LEDS);
429 }
430
431 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
432 {
433 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
434 u8 reg = __raw_readb(cpld + CPLD_LEDS);
435
436 return (reg & led->mask) ? LED_OFF : LED_FULL;
437 }
438
439 static int __init cpld_leds_init(void)
440 {
441 int i;
442
443 if (!have_leds() || !cpld)
444 return 0;
445
446 /* setup LEDs */
447 __raw_writeb(0xff, cpld + CPLD_LEDS);
448 for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
449 struct cpld_led *led;
450
451 led = kzalloc(sizeof(*led), GFP_KERNEL);
452 if (!led)
453 break;
454
455 led->cdev.name = cpld_leds[i].name;
456 led->cdev.brightness_set = cpld_led_set;
457 led->cdev.brightness_get = cpld_led_get;
458 led->cdev.default_trigger = cpld_leds[i].trigger;
459 led->mask = BIT(i);
460
461 if (led_classdev_register(NULL, &led->cdev) < 0) {
462 kfree(led);
463 break;
464 }
465 }
466
467 return 0;
468 }
469 /* run after subsys_initcall() for LEDs */
470 fs_initcall(cpld_leds_init);
471
472
473 static void __init evm_init_cpld(void)
474 {
475 u8 mux, resets;
476 const char *label;
477 struct clk *aemif_clk;
478
479 /* Make sure we can configure the CPLD through CS1. Then
480 * leave it on for later access to MMC and LED registers.
481 */
482 aemif_clk = clk_get(NULL, "aemif");
483 if (IS_ERR(aemif_clk))
484 return;
485 clk_enable(aemif_clk);
486
487 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
488 "cpld") == NULL)
489 goto fail;
490 cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
491 if (!cpld) {
492 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
493 SECTION_SIZE);
494 fail:
495 pr_err("ERROR: can't map CPLD\n");
496 clk_disable(aemif_clk);
497 return;
498 }
499
500 /* External muxing for some signals */
501 mux = 0;
502
503 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
504 * NOTE: SW4 bus width setting must match!
505 */
506 if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
507 /* external keypad mux */
508 mux |= BIT(7);
509
510 platform_add_devices(dm365_evm_nand_devices,
511 ARRAY_SIZE(dm365_evm_nand_devices));
512 } else {
513 /* no OneNAND support yet */
514 }
515
516 /* Leave external chips in reset when unused. */
517 resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
518
519 /* Static video input config with SN74CBT16214 1-of-3 mux:
520 * - port b1 == tvp7002 (mux lowbits == 1 or 6)
521 * - port b2 == imager (mux lowbits == 2 or 7)
522 * - port b3 == tvp5146 (mux lowbits == 5)
523 *
524 * Runtime switching could work too, with limitations.
525 */
526 if (have_imager()) {
527 label = "HD imager";
528 mux |= 1;
529
530 /* externally mux MMC1/ENET/AIC33 to imager */
531 mux |= BIT(6) | BIT(5) | BIT(3);
532 } else {
533 struct davinci_soc_info *soc_info = &davinci_soc_info;
534
535 /* we can use MMC1 ... */
536 dm365evm_mmc_configure();
537 davinci_setup_mmc(1, &dm365evm_mmc_config);
538
539 /* ... and ENET ... */
540 dm365evm_emac_configure();
541 soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK;
542 soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY;
543 resets &= ~BIT(3);
544
545 /* ... and AIC33 */
546 resets &= ~BIT(1);
547
548 if (have_tvp7002()) {
549 mux |= 2;
550 resets &= ~BIT(2);
551 label = "tvp7002 HD";
552 } else {
553 /* default to tvp5146 */
554 mux |= 5;
555 resets &= ~BIT(0);
556 label = "tvp5146 SD";
557 }
558 }
559 __raw_writeb(mux, cpld + CPLD_MUX);
560 __raw_writeb(resets, cpld + CPLD_RESETS);
561 pr_info("EVM: %s video input\n", label);
562
563 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
564 }
565
566 static struct davinci_uart_config uart_config __initdata = {
567 .enabled_uarts = (1 << 0),
568 };
569
570 static void __init dm365_evm_map_io(void)
571 {
572 /* setup input configuration for VPFE input devices */
573 dm365_set_vpfe_config(&vpfe_cfg);
574 dm365_init();
575 }
576
577 static struct spi_eeprom at25640 = {
578 .byte_len = SZ_64K / 8,
579 .name = "at25640",
580 .page_size = 32,
581 .flags = EE_ADDR2,
582 };
583
584 static struct spi_board_info dm365_evm_spi_info[] __initconst = {
585 {
586 .modalias = "at25",
587 .platform_data = &at25640,
588 .max_speed_hz = 10 * 1000 * 1000,
589 .bus_num = 0,
590 .chip_select = 0,
591 .mode = SPI_MODE_0,
592 },
593 };
594
595 static __init void dm365_evm_init(void)
596 {
597 evm_init_i2c();
598 davinci_serial_init(&uart_config);
599
600 dm365evm_emac_configure();
601 dm365evm_mmc_configure();
602
603 davinci_setup_mmc(0, &dm365evm_mmc_config);
604
605 /* maybe setup mmc1/etc ... _after_ mmc0 */
606 evm_init_cpld();
607
608 dm365_init_asp(&dm365_evm_snd_data);
609 dm365_init_rtc();
610 dm365_init_ks(&dm365evm_ks_data);
611
612 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
613 ARRAY_SIZE(dm365_evm_spi_info));
614 }
615
616 static __init void dm365_evm_irq_init(void)
617 {
618 davinci_irq_init();
619 }
620
621 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
622 .phys_io = IO_PHYS,
623 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
624 .boot_params = (0x80000100),
625 .map_io = dm365_evm_map_io,
626 .init_irq = dm365_evm_irq_init,
627 .timer = &davinci_timer,
628 .init_machine = dm365_evm_init,
629 MACHINE_END
630
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