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Merge branch 'linux-next' of git://git.infradead.org/ubifs-2.6
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-davinci / board-dm365-evm.c
1 /*
2 * TI DaVinci DM365 EVM board support
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/i2c.h>
19 #include <linux/io.h>
20 #include <linux/clk.h>
21 #include <linux/i2c/at24.h>
22 #include <linux/leds.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/slab.h>
26 #include <linux/mtd/nand.h>
27 #include <linux/input.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/eeprom.h>
30
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33
34 #include <mach/mux.h>
35 #include <mach/dm365.h>
36 #include <mach/common.h>
37 #include <mach/i2c.h>
38 #include <mach/serial.h>
39 #include <mach/mmc.h>
40 #include <mach/nand.h>
41 #include <mach/keyscan.h>
42
43 #include <media/tvp514x.h>
44
45 static inline int have_imager(void)
46 {
47 /* REVISIT when it's supported, trigger via Kconfig */
48 return 0;
49 }
50
51 static inline int have_tvp7002(void)
52 {
53 /* REVISIT when it's supported, trigger via Kconfig */
54 return 0;
55 }
56
57 #define DM365_EVM_PHY_ID "0:01"
58 /*
59 * A MAX-II CPLD is used for various board control functions.
60 */
61 #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
62
63 #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
64 #define CPLD_TEST CPLD_OFFSET(0,1)
65 #define CPLD_LEDS CPLD_OFFSET(0,2)
66 #define CPLD_MUX CPLD_OFFSET(0,3)
67 #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
68 #define CPLD_POWER CPLD_OFFSET(1,1)
69 #define CPLD_VIDEO CPLD_OFFSET(1,2)
70 #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
71
72 #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
73 #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
74
75 #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
76 #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
77 #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
78 #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
79 #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
80 #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
81 #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
82 #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
83 #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
84
85 #define CPLD_RESETS CPLD_OFFSET(4,3)
86
87 #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
88 #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
89 #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
90 #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
91 #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
92 #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
93
94 static void __iomem *cpld;
95
96
97 /* NOTE: this is geared for the standard config, with a socketed
98 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
99 * swap chips with a different block size, partitioning will
100 * need to be changed. This NAND chip MT29F16G08FAA is the default
101 * NAND shipped with the Spectrum Digital DM365 EVM
102 */
103 #define NAND_BLOCK_SIZE SZ_128K
104
105 static struct mtd_partition davinci_nand_partitions[] = {
106 {
107 /* UBL (a few copies) plus U-Boot */
108 .name = "bootloader",
109 .offset = 0,
110 .size = 28 * NAND_BLOCK_SIZE,
111 .mask_flags = MTD_WRITEABLE, /* force read-only */
112 }, {
113 /* U-Boot environment */
114 .name = "params",
115 .offset = MTDPART_OFS_APPEND,
116 .size = 2 * NAND_BLOCK_SIZE,
117 .mask_flags = 0,
118 }, {
119 .name = "kernel",
120 .offset = MTDPART_OFS_APPEND,
121 .size = SZ_4M,
122 .mask_flags = 0,
123 }, {
124 .name = "filesystem1",
125 .offset = MTDPART_OFS_APPEND,
126 .size = SZ_512M,
127 .mask_flags = 0,
128 }, {
129 .name = "filesystem2",
130 .offset = MTDPART_OFS_APPEND,
131 .size = MTDPART_SIZ_FULL,
132 .mask_flags = 0,
133 }
134 /* two blocks with bad block table (and mirror) at the end */
135 };
136
137 static struct davinci_nand_pdata davinci_nand_data = {
138 .mask_chipsel = BIT(14),
139 .parts = davinci_nand_partitions,
140 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
141 .ecc_mode = NAND_ECC_HW,
142 .options = NAND_USE_FLASH_BBT,
143 .ecc_bits = 4,
144 };
145
146 static struct resource davinci_nand_resources[] = {
147 {
148 .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
149 .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
150 .flags = IORESOURCE_MEM,
151 }, {
152 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
153 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
154 .flags = IORESOURCE_MEM,
155 },
156 };
157
158 static struct platform_device davinci_nand_device = {
159 .name = "davinci_nand",
160 .id = 0,
161 .num_resources = ARRAY_SIZE(davinci_nand_resources),
162 .resource = davinci_nand_resources,
163 .dev = {
164 .platform_data = &davinci_nand_data,
165 },
166 };
167
168 static struct at24_platform_data eeprom_info = {
169 .byte_len = (256*1024) / 8,
170 .page_size = 64,
171 .flags = AT24_FLAG_ADDR16,
172 .setup = davinci_get_mac_addr,
173 .context = (void *)0x7f00,
174 };
175
176 static struct snd_platform_data dm365_evm_snd_data = {
177 .asp_chan_q = EVENTQ_3,
178 };
179
180 static struct i2c_board_info i2c_info[] = {
181 {
182 I2C_BOARD_INFO("24c256", 0x50),
183 .platform_data = &eeprom_info,
184 },
185 {
186 I2C_BOARD_INFO("tlv320aic3x", 0x18),
187 },
188 };
189
190 static struct davinci_i2c_platform_data i2c_pdata = {
191 .bus_freq = 400 /* kHz */,
192 .bus_delay = 0 /* usec */,
193 };
194
195 static int dm365evm_keyscan_enable(struct device *dev)
196 {
197 return davinci_cfg_reg(DM365_KEYSCAN);
198 }
199
200 static unsigned short dm365evm_keymap[] = {
201 KEY_KP2,
202 KEY_LEFT,
203 KEY_EXIT,
204 KEY_DOWN,
205 KEY_ENTER,
206 KEY_UP,
207 KEY_KP1,
208 KEY_RIGHT,
209 KEY_MENU,
210 KEY_RECORD,
211 KEY_REWIND,
212 KEY_KPMINUS,
213 KEY_STOP,
214 KEY_FASTFORWARD,
215 KEY_KPPLUS,
216 KEY_PLAYPAUSE,
217 0
218 };
219
220 static struct davinci_ks_platform_data dm365evm_ks_data = {
221 .device_enable = dm365evm_keyscan_enable,
222 .keymap = dm365evm_keymap,
223 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
224 .rep = 1,
225 /* Scan period = strobe + interval */
226 .strobe = 0x5,
227 .interval = 0x2,
228 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
229 };
230
231 static int cpld_mmc_get_cd(int module)
232 {
233 if (!cpld)
234 return -ENXIO;
235
236 /* low == card present */
237 return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
238 }
239
240 static int cpld_mmc_get_ro(int module)
241 {
242 if (!cpld)
243 return -ENXIO;
244
245 /* high == card's write protect switch active */
246 return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
247 }
248
249 static struct davinci_mmc_config dm365evm_mmc_config = {
250 .get_cd = cpld_mmc_get_cd,
251 .get_ro = cpld_mmc_get_ro,
252 .wires = 4,
253 .max_freq = 50000000,
254 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
255 .version = MMC_CTLR_VERSION_2,
256 };
257
258 static void dm365evm_emac_configure(void)
259 {
260 /*
261 * EMAC pins are multiplexed with GPIO and UART
262 * Further details are available at the DM365 ARM
263 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
264 */
265 davinci_cfg_reg(DM365_EMAC_TX_EN);
266 davinci_cfg_reg(DM365_EMAC_TX_CLK);
267 davinci_cfg_reg(DM365_EMAC_COL);
268 davinci_cfg_reg(DM365_EMAC_TXD3);
269 davinci_cfg_reg(DM365_EMAC_TXD2);
270 davinci_cfg_reg(DM365_EMAC_TXD1);
271 davinci_cfg_reg(DM365_EMAC_TXD0);
272 davinci_cfg_reg(DM365_EMAC_RXD3);
273 davinci_cfg_reg(DM365_EMAC_RXD2);
274 davinci_cfg_reg(DM365_EMAC_RXD1);
275 davinci_cfg_reg(DM365_EMAC_RXD0);
276 davinci_cfg_reg(DM365_EMAC_RX_CLK);
277 davinci_cfg_reg(DM365_EMAC_RX_DV);
278 davinci_cfg_reg(DM365_EMAC_RX_ER);
279 davinci_cfg_reg(DM365_EMAC_CRS);
280 davinci_cfg_reg(DM365_EMAC_MDIO);
281 davinci_cfg_reg(DM365_EMAC_MDCLK);
282
283 /*
284 * EMAC interrupts are multiplexed with GPIO interrupts
285 * Details are available at the DM365 ARM
286 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
287 */
288 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
289 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
290 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
291 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
292 }
293
294 static void dm365evm_mmc_configure(void)
295 {
296 /*
297 * MMC/SD pins are multiplexed with GPIO and EMIF
298 * Further details are available at the DM365 ARM
299 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
300 */
301 davinci_cfg_reg(DM365_SD1_CLK);
302 davinci_cfg_reg(DM365_SD1_CMD);
303 davinci_cfg_reg(DM365_SD1_DATA3);
304 davinci_cfg_reg(DM365_SD1_DATA2);
305 davinci_cfg_reg(DM365_SD1_DATA1);
306 davinci_cfg_reg(DM365_SD1_DATA0);
307 }
308
309 static struct tvp514x_platform_data tvp5146_pdata = {
310 .clk_polarity = 0,
311 .hs_polarity = 1,
312 .vs_polarity = 1
313 };
314
315 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
316 /* Inputs available at the TVP5146 */
317 static struct v4l2_input tvp5146_inputs[] = {
318 {
319 .index = 0,
320 .name = "Composite",
321 .type = V4L2_INPUT_TYPE_CAMERA,
322 .std = TVP514X_STD_ALL,
323 },
324 {
325 .index = 1,
326 .name = "S-Video",
327 .type = V4L2_INPUT_TYPE_CAMERA,
328 .std = TVP514X_STD_ALL,
329 },
330 };
331
332 /*
333 * this is the route info for connecting each input to decoder
334 * ouput that goes to vpfe. There is a one to one correspondence
335 * with tvp5146_inputs
336 */
337 static struct vpfe_route tvp5146_routes[] = {
338 {
339 .input = INPUT_CVBS_VI2B,
340 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
341 },
342 {
343 .input = INPUT_SVIDEO_VI2C_VI1C,
344 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
345 },
346 };
347
348 static struct vpfe_subdev_info vpfe_sub_devs[] = {
349 {
350 .name = "tvp5146",
351 .grp_id = 0,
352 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
353 .inputs = tvp5146_inputs,
354 .routes = tvp5146_routes,
355 .can_route = 1,
356 .ccdc_if_params = {
357 .if_type = VPFE_BT656,
358 .hdpol = VPFE_PINPOL_POSITIVE,
359 .vdpol = VPFE_PINPOL_POSITIVE,
360 },
361 .board_info = {
362 I2C_BOARD_INFO("tvp5146", 0x5d),
363 .platform_data = &tvp5146_pdata,
364 },
365 },
366 };
367
368 static struct vpfe_config vpfe_cfg = {
369 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
370 .sub_devs = vpfe_sub_devs,
371 .i2c_adapter_id = 1,
372 .card_name = "DM365 EVM",
373 .ccdc = "ISIF",
374 };
375
376 static void __init evm_init_i2c(void)
377 {
378 davinci_init_i2c(&i2c_pdata);
379 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
380 }
381
382 static struct platform_device *dm365_evm_nand_devices[] __initdata = {
383 &davinci_nand_device,
384 };
385
386 static inline int have_leds(void)
387 {
388 #ifdef CONFIG_LEDS_CLASS
389 return 1;
390 #else
391 return 0;
392 #endif
393 }
394
395 struct cpld_led {
396 struct led_classdev cdev;
397 u8 mask;
398 };
399
400 static const struct {
401 const char *name;
402 const char *trigger;
403 } cpld_leds[] = {
404 { "dm365evm::ds2", },
405 { "dm365evm::ds3", },
406 { "dm365evm::ds4", },
407 { "dm365evm::ds5", },
408 { "dm365evm::ds6", "nand-disk", },
409 { "dm365evm::ds7", "mmc1", },
410 { "dm365evm::ds8", "mmc0", },
411 { "dm365evm::ds9", "heartbeat", },
412 };
413
414 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
415 {
416 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
417 u8 reg = __raw_readb(cpld + CPLD_LEDS);
418
419 if (b != LED_OFF)
420 reg &= ~led->mask;
421 else
422 reg |= led->mask;
423 __raw_writeb(reg, cpld + CPLD_LEDS);
424 }
425
426 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
427 {
428 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
429 u8 reg = __raw_readb(cpld + CPLD_LEDS);
430
431 return (reg & led->mask) ? LED_OFF : LED_FULL;
432 }
433
434 static int __init cpld_leds_init(void)
435 {
436 int i;
437
438 if (!have_leds() || !cpld)
439 return 0;
440
441 /* setup LEDs */
442 __raw_writeb(0xff, cpld + CPLD_LEDS);
443 for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
444 struct cpld_led *led;
445
446 led = kzalloc(sizeof(*led), GFP_KERNEL);
447 if (!led)
448 break;
449
450 led->cdev.name = cpld_leds[i].name;
451 led->cdev.brightness_set = cpld_led_set;
452 led->cdev.brightness_get = cpld_led_get;
453 led->cdev.default_trigger = cpld_leds[i].trigger;
454 led->mask = BIT(i);
455
456 if (led_classdev_register(NULL, &led->cdev) < 0) {
457 kfree(led);
458 break;
459 }
460 }
461
462 return 0;
463 }
464 /* run after subsys_initcall() for LEDs */
465 fs_initcall(cpld_leds_init);
466
467
468 static void __init evm_init_cpld(void)
469 {
470 u8 mux, resets;
471 const char *label;
472 struct clk *aemif_clk;
473
474 /* Make sure we can configure the CPLD through CS1. Then
475 * leave it on for later access to MMC and LED registers.
476 */
477 aemif_clk = clk_get(NULL, "aemif");
478 if (IS_ERR(aemif_clk))
479 return;
480 clk_enable(aemif_clk);
481
482 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
483 "cpld") == NULL)
484 goto fail;
485 cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
486 if (!cpld) {
487 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
488 SECTION_SIZE);
489 fail:
490 pr_err("ERROR: can't map CPLD\n");
491 clk_disable(aemif_clk);
492 return;
493 }
494
495 /* External muxing for some signals */
496 mux = 0;
497
498 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
499 * NOTE: SW4 bus width setting must match!
500 */
501 if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
502 /* external keypad mux */
503 mux |= BIT(7);
504
505 platform_add_devices(dm365_evm_nand_devices,
506 ARRAY_SIZE(dm365_evm_nand_devices));
507 } else {
508 /* no OneNAND support yet */
509 }
510
511 /* Leave external chips in reset when unused. */
512 resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
513
514 /* Static video input config with SN74CBT16214 1-of-3 mux:
515 * - port b1 == tvp7002 (mux lowbits == 1 or 6)
516 * - port b2 == imager (mux lowbits == 2 or 7)
517 * - port b3 == tvp5146 (mux lowbits == 5)
518 *
519 * Runtime switching could work too, with limitations.
520 */
521 if (have_imager()) {
522 label = "HD imager";
523 mux |= 2;
524
525 /* externally mux MMC1/ENET/AIC33 to imager */
526 mux |= BIT(6) | BIT(5) | BIT(3);
527 } else {
528 struct davinci_soc_info *soc_info = &davinci_soc_info;
529
530 /* we can use MMC1 ... */
531 dm365evm_mmc_configure();
532 davinci_setup_mmc(1, &dm365evm_mmc_config);
533
534 /* ... and ENET ... */
535 dm365evm_emac_configure();
536 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
537 resets &= ~BIT(3);
538
539 /* ... and AIC33 */
540 resets &= ~BIT(1);
541
542 if (have_tvp7002()) {
543 mux |= 1;
544 resets &= ~BIT(2);
545 label = "tvp7002 HD";
546 } else {
547 /* default to tvp5146 */
548 mux |= 5;
549 resets &= ~BIT(0);
550 label = "tvp5146 SD";
551 }
552 }
553 __raw_writeb(mux, cpld + CPLD_MUX);
554 __raw_writeb(resets, cpld + CPLD_RESETS);
555 pr_info("EVM: %s video input\n", label);
556
557 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
558 }
559
560 static struct davinci_uart_config uart_config __initdata = {
561 .enabled_uarts = (1 << 0),
562 };
563
564 static void __init dm365_evm_map_io(void)
565 {
566 /* setup input configuration for VPFE input devices */
567 dm365_set_vpfe_config(&vpfe_cfg);
568 dm365_init();
569 }
570
571 static struct spi_eeprom at25640 = {
572 .byte_len = SZ_64K / 8,
573 .name = "at25640",
574 .page_size = 32,
575 .flags = EE_ADDR2,
576 };
577
578 static struct spi_board_info dm365_evm_spi_info[] __initconst = {
579 {
580 .modalias = "at25",
581 .platform_data = &at25640,
582 .max_speed_hz = 10 * 1000 * 1000,
583 .bus_num = 0,
584 .chip_select = 0,
585 .mode = SPI_MODE_0,
586 },
587 };
588
589 static __init void dm365_evm_init(void)
590 {
591 evm_init_i2c();
592 davinci_serial_init(&uart_config);
593
594 dm365evm_emac_configure();
595 dm365evm_mmc_configure();
596
597 davinci_setup_mmc(0, &dm365evm_mmc_config);
598
599 /* maybe setup mmc1/etc ... _after_ mmc0 */
600 evm_init_cpld();
601
602 #ifdef CONFIG_SND_DM365_AIC3X_CODEC
603 dm365_init_asp(&dm365_evm_snd_data);
604 #elif defined(CONFIG_SND_DM365_VOICE_CODEC)
605 dm365_init_vc(&dm365_evm_snd_data);
606 #endif
607 dm365_init_rtc();
608 dm365_init_ks(&dm365evm_ks_data);
609
610 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
611 ARRAY_SIZE(dm365_evm_spi_info));
612 }
613
614 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
615 .atag_offset = 0x100,
616 .map_io = dm365_evm_map_io,
617 .init_irq = davinci_irq_init,
618 .timer = &davinci_timer,
619 .init_machine = dm365_evm_init,
620 .dma_zone_size = SZ_128M,
621 MACHINE_END
622
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