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[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-davinci / da850.c
1 /*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14 #include <linux/clkdev.h>
15 #include <linux/gpio.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/platform_device.h>
19 #include <linux/cpufreq.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/platform_data/gpio-davinci.h>
22
23 #include <asm/mach/map.h>
24
25 #include "psc.h"
26 #include <mach/irqs.h>
27 #include <mach/cputype.h>
28 #include <mach/common.h>
29 #include <mach/time.h>
30 #include <mach/da8xx.h>
31 #include <mach/cpufreq.h>
32 #include <mach/pm.h>
33
34 #include "clock.h"
35 #include "mux.h"
36
37 #define DA850_PLL1_BASE 0x01e1a000
38 #define DA850_TIMER64P2_BASE 0x01f0c000
39 #define DA850_TIMER64P3_BASE 0x01f0d000
40
41 #define DA850_REF_FREQ 24000000
42
43 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
44 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
45 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
46
47 static int da850_set_armrate(struct clk *clk, unsigned long rate);
48 static int da850_round_armrate(struct clk *clk, unsigned long rate);
49 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
50
51 static struct pll_data pll0_data = {
52 .num = 1,
53 .phys_base = DA8XX_PLL0_BASE,
54 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
55 };
56
57 static struct clk ref_clk = {
58 .name = "ref_clk",
59 .rate = DA850_REF_FREQ,
60 .set_rate = davinci_simple_set_rate,
61 };
62
63 static struct clk pll0_clk = {
64 .name = "pll0",
65 .parent = &ref_clk,
66 .pll_data = &pll0_data,
67 .flags = CLK_PLL,
68 .set_rate = da850_set_pll0rate,
69 };
70
71 static struct clk pll0_aux_clk = {
72 .name = "pll0_aux_clk",
73 .parent = &pll0_clk,
74 .flags = CLK_PLL | PRE_PLL,
75 };
76
77 static struct clk pll0_sysclk1 = {
78 .name = "pll0_sysclk1",
79 .parent = &pll0_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV1,
82 };
83
84 static struct clk pll0_sysclk2 = {
85 .name = "pll0_sysclk2",
86 .parent = &pll0_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV2,
89 };
90
91 static struct clk pll0_sysclk3 = {
92 .name = "pll0_sysclk3",
93 .parent = &pll0_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV3,
96 .set_rate = davinci_set_sysclk_rate,
97 .maxrate = 100000000,
98 };
99
100 static struct clk pll0_sysclk4 = {
101 .name = "pll0_sysclk4",
102 .parent = &pll0_clk,
103 .flags = CLK_PLL,
104 .div_reg = PLLDIV4,
105 };
106
107 static struct clk pll0_sysclk5 = {
108 .name = "pll0_sysclk5",
109 .parent = &pll0_clk,
110 .flags = CLK_PLL,
111 .div_reg = PLLDIV5,
112 };
113
114 static struct clk pll0_sysclk6 = {
115 .name = "pll0_sysclk6",
116 .parent = &pll0_clk,
117 .flags = CLK_PLL,
118 .div_reg = PLLDIV6,
119 };
120
121 static struct clk pll0_sysclk7 = {
122 .name = "pll0_sysclk7",
123 .parent = &pll0_clk,
124 .flags = CLK_PLL,
125 .div_reg = PLLDIV7,
126 };
127
128 static struct pll_data pll1_data = {
129 .num = 2,
130 .phys_base = DA850_PLL1_BASE,
131 .flags = PLL_HAS_POSTDIV,
132 };
133
134 static struct clk pll1_clk = {
135 .name = "pll1",
136 .parent = &ref_clk,
137 .pll_data = &pll1_data,
138 .flags = CLK_PLL,
139 };
140
141 static struct clk pll1_aux_clk = {
142 .name = "pll1_aux_clk",
143 .parent = &pll1_clk,
144 .flags = CLK_PLL | PRE_PLL,
145 };
146
147 static struct clk pll1_sysclk2 = {
148 .name = "pll1_sysclk2",
149 .parent = &pll1_clk,
150 .flags = CLK_PLL,
151 .div_reg = PLLDIV2,
152 };
153
154 static struct clk pll1_sysclk3 = {
155 .name = "pll1_sysclk3",
156 .parent = &pll1_clk,
157 .flags = CLK_PLL,
158 .div_reg = PLLDIV3,
159 };
160
161 static int da850_async3_set_parent(struct clk *clk, struct clk *parent)
162 {
163 u32 val;
164
165 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
166
167 if (parent == &pll0_sysclk2) {
168 val &= ~CFGCHIP3_ASYNC3_CLKSRC;
169 } else if (parent == &pll1_sysclk2) {
170 val |= CFGCHIP3_ASYNC3_CLKSRC;
171 } else {
172 pr_err("Bad parent on async3 clock mux\n");
173 return -EINVAL;
174 }
175
176 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
177
178 return 0;
179 }
180
181 static struct clk async3_clk = {
182 .name = "async3",
183 .parent = &pll1_sysclk2,
184 .set_parent = da850_async3_set_parent,
185 };
186
187 static struct clk i2c0_clk = {
188 .name = "i2c0",
189 .parent = &pll0_aux_clk,
190 };
191
192 static struct clk timerp64_0_clk = {
193 .name = "timer0",
194 .parent = &pll0_aux_clk,
195 };
196
197 static struct clk timerp64_1_clk = {
198 .name = "timer1",
199 .parent = &pll0_aux_clk,
200 };
201
202 static struct clk arm_rom_clk = {
203 .name = "arm_rom",
204 .parent = &pll0_sysclk2,
205 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
206 .flags = ALWAYS_ENABLED,
207 };
208
209 static struct clk tpcc0_clk = {
210 .name = "tpcc0",
211 .parent = &pll0_sysclk2,
212 .lpsc = DA8XX_LPSC0_TPCC,
213 .flags = ALWAYS_ENABLED | CLK_PSC,
214 };
215
216 static struct clk tptc0_clk = {
217 .name = "tptc0",
218 .parent = &pll0_sysclk2,
219 .lpsc = DA8XX_LPSC0_TPTC0,
220 .flags = ALWAYS_ENABLED,
221 };
222
223 static struct clk tptc1_clk = {
224 .name = "tptc1",
225 .parent = &pll0_sysclk2,
226 .lpsc = DA8XX_LPSC0_TPTC1,
227 .flags = ALWAYS_ENABLED,
228 };
229
230 static struct clk tpcc1_clk = {
231 .name = "tpcc1",
232 .parent = &pll0_sysclk2,
233 .lpsc = DA850_LPSC1_TPCC1,
234 .gpsc = 1,
235 .flags = CLK_PSC | ALWAYS_ENABLED,
236 };
237
238 static struct clk tptc2_clk = {
239 .name = "tptc2",
240 .parent = &pll0_sysclk2,
241 .lpsc = DA850_LPSC1_TPTC2,
242 .gpsc = 1,
243 .flags = ALWAYS_ENABLED,
244 };
245
246 static struct clk pruss_clk = {
247 .name = "pruss",
248 .parent = &pll0_sysclk2,
249 .lpsc = DA8XX_LPSC0_PRUSS,
250 };
251
252 static struct clk uart0_clk = {
253 .name = "uart0",
254 .parent = &pll0_sysclk2,
255 .lpsc = DA8XX_LPSC0_UART0,
256 };
257
258 static struct clk uart1_clk = {
259 .name = "uart1",
260 .parent = &async3_clk,
261 .lpsc = DA8XX_LPSC1_UART1,
262 .gpsc = 1,
263 };
264
265 static struct clk uart2_clk = {
266 .name = "uart2",
267 .parent = &async3_clk,
268 .lpsc = DA8XX_LPSC1_UART2,
269 .gpsc = 1,
270 };
271
272 static struct clk aintc_clk = {
273 .name = "aintc",
274 .parent = &pll0_sysclk4,
275 .lpsc = DA8XX_LPSC0_AINTC,
276 .flags = ALWAYS_ENABLED,
277 };
278
279 static struct clk gpio_clk = {
280 .name = "gpio",
281 .parent = &pll0_sysclk4,
282 .lpsc = DA8XX_LPSC1_GPIO,
283 .gpsc = 1,
284 };
285
286 static struct clk i2c1_clk = {
287 .name = "i2c1",
288 .parent = &pll0_sysclk4,
289 .lpsc = DA8XX_LPSC1_I2C,
290 .gpsc = 1,
291 };
292
293 static struct clk emif3_clk = {
294 .name = "emif3",
295 .parent = &pll0_sysclk5,
296 .lpsc = DA8XX_LPSC1_EMIF3C,
297 .gpsc = 1,
298 .flags = ALWAYS_ENABLED,
299 };
300
301 static struct clk arm_clk = {
302 .name = "arm",
303 .parent = &pll0_sysclk6,
304 .lpsc = DA8XX_LPSC0_ARM,
305 .flags = ALWAYS_ENABLED,
306 .set_rate = da850_set_armrate,
307 .round_rate = da850_round_armrate,
308 };
309
310 static struct clk rmii_clk = {
311 .name = "rmii",
312 .parent = &pll0_sysclk7,
313 };
314
315 static struct clk emac_clk = {
316 .name = "emac",
317 .parent = &pll0_sysclk4,
318 .lpsc = DA8XX_LPSC1_CPGMAC,
319 .gpsc = 1,
320 };
321
322 static struct clk mcasp_clk = {
323 .name = "mcasp",
324 .parent = &async3_clk,
325 .lpsc = DA8XX_LPSC1_McASP0,
326 .gpsc = 1,
327 };
328
329 static struct clk mcbsp0_clk = {
330 .name = "mcbsp0",
331 .parent = &async3_clk,
332 .lpsc = DA850_LPSC1_McBSP0,
333 .gpsc = 1,
334 };
335
336 static struct clk mcbsp1_clk = {
337 .name = "mcbsp1",
338 .parent = &async3_clk,
339 .lpsc = DA850_LPSC1_McBSP1,
340 .gpsc = 1,
341 };
342
343 static struct clk lcdc_clk = {
344 .name = "lcdc",
345 .parent = &pll0_sysclk2,
346 .lpsc = DA8XX_LPSC1_LCDC,
347 .gpsc = 1,
348 };
349
350 static struct clk mmcsd0_clk = {
351 .name = "mmcsd0",
352 .parent = &pll0_sysclk2,
353 .lpsc = DA8XX_LPSC0_MMC_SD,
354 };
355
356 static struct clk mmcsd1_clk = {
357 .name = "mmcsd1",
358 .parent = &pll0_sysclk2,
359 .lpsc = DA850_LPSC1_MMC_SD1,
360 .gpsc = 1,
361 };
362
363 static struct clk aemif_clk = {
364 .name = "aemif",
365 .parent = &pll0_sysclk3,
366 .lpsc = DA8XX_LPSC0_EMIF25,
367 .flags = ALWAYS_ENABLED,
368 };
369
370 static struct clk usb11_clk = {
371 .name = "usb11",
372 .parent = &pll0_sysclk4,
373 .lpsc = DA8XX_LPSC1_USB11,
374 .gpsc = 1,
375 };
376
377 static struct clk usb20_clk = {
378 .name = "usb20",
379 .parent = &pll0_sysclk2,
380 .lpsc = DA8XX_LPSC1_USB20,
381 .gpsc = 1,
382 };
383
384 static struct clk spi0_clk = {
385 .name = "spi0",
386 .parent = &pll0_sysclk2,
387 .lpsc = DA8XX_LPSC0_SPI0,
388 };
389
390 static struct clk spi1_clk = {
391 .name = "spi1",
392 .parent = &async3_clk,
393 .lpsc = DA8XX_LPSC1_SPI1,
394 .gpsc = 1,
395 };
396
397 static struct clk vpif_clk = {
398 .name = "vpif",
399 .parent = &pll0_sysclk2,
400 .lpsc = DA850_LPSC1_VPIF,
401 .gpsc = 1,
402 };
403
404 static struct clk sata_clk = {
405 .name = "sata",
406 .parent = &pll0_sysclk2,
407 .lpsc = DA850_LPSC1_SATA,
408 .gpsc = 1,
409 .flags = PSC_FORCE,
410 };
411
412 static struct clk dsp_clk = {
413 .name = "dsp",
414 .parent = &pll0_sysclk1,
415 .domain = DAVINCI_GPSC_DSPDOMAIN,
416 .lpsc = DA8XX_LPSC0_GEM,
417 .flags = PSC_LRST | PSC_FORCE,
418 };
419
420 static struct clk ehrpwm_clk = {
421 .name = "ehrpwm",
422 .parent = &async3_clk,
423 .lpsc = DA8XX_LPSC1_PWM,
424 .gpsc = 1,
425 };
426
427 static struct clk ehrpwm0_clk = {
428 .name = "ehrpwm0",
429 .parent = &ehrpwm_clk,
430 };
431
432 static struct clk ehrpwm1_clk = {
433 .name = "ehrpwm1",
434 .parent = &ehrpwm_clk,
435 };
436
437 #define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
438
439 static void ehrpwm_tblck_enable(struct clk *clk)
440 {
441 u32 val;
442
443 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
444 val |= DA8XX_EHRPWM_TBCLKSYNC;
445 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
446 }
447
448 static void ehrpwm_tblck_disable(struct clk *clk)
449 {
450 u32 val;
451
452 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
453 val &= ~DA8XX_EHRPWM_TBCLKSYNC;
454 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
455 }
456
457 static struct clk ehrpwm_tbclk = {
458 .name = "ehrpwm_tbclk",
459 .parent = &ehrpwm_clk,
460 .clk_enable = ehrpwm_tblck_enable,
461 .clk_disable = ehrpwm_tblck_disable,
462 };
463
464 static struct clk ehrpwm0_tbclk = {
465 .name = "ehrpwm0_tbclk",
466 .parent = &ehrpwm_tbclk,
467 };
468
469 static struct clk ehrpwm1_tbclk = {
470 .name = "ehrpwm1_tbclk",
471 .parent = &ehrpwm_tbclk,
472 };
473
474 static struct clk ecap_clk = {
475 .name = "ecap",
476 .parent = &async3_clk,
477 .lpsc = DA8XX_LPSC1_ECAP,
478 .gpsc = 1,
479 };
480
481 static struct clk ecap0_clk = {
482 .name = "ecap0_clk",
483 .parent = &ecap_clk,
484 };
485
486 static struct clk ecap1_clk = {
487 .name = "ecap1_clk",
488 .parent = &ecap_clk,
489 };
490
491 static struct clk ecap2_clk = {
492 .name = "ecap2_clk",
493 .parent = &ecap_clk,
494 };
495
496 static struct clk_lookup da850_clks[] = {
497 CLK(NULL, "ref", &ref_clk),
498 CLK(NULL, "pll0", &pll0_clk),
499 CLK(NULL, "pll0_aux", &pll0_aux_clk),
500 CLK(NULL, "pll0_sysclk1", &pll0_sysclk1),
501 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
502 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
503 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
504 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
505 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
506 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
507 CLK(NULL, "pll1", &pll1_clk),
508 CLK(NULL, "pll1_aux", &pll1_aux_clk),
509 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
510 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
511 CLK(NULL, "async3", &async3_clk),
512 CLK("i2c_davinci.1", NULL, &i2c0_clk),
513 CLK(NULL, "timer0", &timerp64_0_clk),
514 CLK("davinci-wdt", NULL, &timerp64_1_clk),
515 CLK(NULL, "arm_rom", &arm_rom_clk),
516 CLK(NULL, "tpcc0", &tpcc0_clk),
517 CLK(NULL, "tptc0", &tptc0_clk),
518 CLK(NULL, "tptc1", &tptc1_clk),
519 CLK(NULL, "tpcc1", &tpcc1_clk),
520 CLK(NULL, "tptc2", &tptc2_clk),
521 CLK("pruss_uio", "pruss", &pruss_clk),
522 CLK("serial8250.0", NULL, &uart0_clk),
523 CLK("serial8250.1", NULL, &uart1_clk),
524 CLK("serial8250.2", NULL, &uart2_clk),
525 CLK(NULL, "aintc", &aintc_clk),
526 CLK(NULL, "gpio", &gpio_clk),
527 CLK("i2c_davinci.2", NULL, &i2c1_clk),
528 CLK(NULL, "emif3", &emif3_clk),
529 CLK(NULL, "arm", &arm_clk),
530 CLK(NULL, "rmii", &rmii_clk),
531 CLK("davinci_emac.1", NULL, &emac_clk),
532 CLK("davinci_mdio.0", "fck", &emac_clk),
533 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
534 CLK("davinci-mcbsp.0", NULL, &mcbsp0_clk),
535 CLK("davinci-mcbsp.1", NULL, &mcbsp1_clk),
536 CLK("da8xx_lcdc.0", "fck", &lcdc_clk),
537 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
538 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
539 CLK("ti-aemif", NULL, &aemif_clk),
540 CLK(NULL, "aemif", &aemif_clk),
541 CLK("ohci-da8xx", "usb11", &usb11_clk),
542 CLK("musb-da8xx", "usb20", &usb20_clk),
543 CLK("spi_davinci.0", NULL, &spi0_clk),
544 CLK("spi_davinci.1", NULL, &spi1_clk),
545 CLK("vpif", NULL, &vpif_clk),
546 CLK("ahci_da850", NULL, &sata_clk),
547 CLK("davinci-rproc.0", NULL, &dsp_clk),
548 CLK(NULL, NULL, &ehrpwm_clk),
549 CLK("ehrpwm.0", "fck", &ehrpwm0_clk),
550 CLK("ehrpwm.1", "fck", &ehrpwm1_clk),
551 CLK(NULL, NULL, &ehrpwm_tbclk),
552 CLK("ehrpwm.0", "tbclk", &ehrpwm0_tbclk),
553 CLK("ehrpwm.1", "tbclk", &ehrpwm1_tbclk),
554 CLK(NULL, NULL, &ecap_clk),
555 CLK("ecap.0", "fck", &ecap0_clk),
556 CLK("ecap.1", "fck", &ecap1_clk),
557 CLK("ecap.2", "fck", &ecap2_clk),
558 CLK(NULL, NULL, NULL),
559 };
560
561 /*
562 * Device specific mux setup
563 *
564 * soc description mux mode mode mux dbg
565 * reg offset mask mode
566 */
567 static const struct mux_config da850_pins[] = {
568 #ifdef CONFIG_DAVINCI_MUX
569 /* UART0 function */
570 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
571 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
572 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
573 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
574 /* UART1 function */
575 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
576 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
577 /* UART2 function */
578 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
579 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
580 /* I2C1 function */
581 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
582 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
583 /* I2C0 function */
584 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
585 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
586 /* EMAC function */
587 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
588 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
589 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
590 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
591 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
592 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
593 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
594 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
595 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
596 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
597 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
598 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
599 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
600 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
601 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
602 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
603 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
604 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
605 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
606 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
607 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
608 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
609 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
610 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
611 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
612 /* McASP function */
613 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
614 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
615 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
616 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
617 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
618 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
619 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
620 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
621 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
622 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
623 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
624 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
625 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
626 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
627 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
628 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
629 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
630 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
631 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
632 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
633 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
634 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
635 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
636 /* LCD function */
637 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
638 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
639 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
640 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
641 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
642 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
643 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
644 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
645 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
646 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
647 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
648 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
649 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
650 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
651 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
652 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
653 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
654 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
655 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
656 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
657 /* MMC/SD0 function */
658 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
659 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
660 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
661 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
662 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
663 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
664 /* MMC/SD1 function */
665 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
666 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
667 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
668 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
669 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
670 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
671 /* EMIF2.5/EMIFA function */
672 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
673 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
674 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
675 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
676 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
677 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
678 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
679 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
680 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
681 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
682 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
683 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
684 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
685 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
686 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
687 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
688 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
689 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
690 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
691 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
692 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
693 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
694 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
695 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
696 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
697 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
698 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
699 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
700 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
701 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
702 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
703 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
704 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
705 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
706 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
707 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
708 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
709 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
710 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
711 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
712 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
713 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
714 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
715 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
716 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
717 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
718 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
719 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
720 /* GPIO function */
721 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
722 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
723 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
724 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
725 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
726 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
727 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
728 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
729 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
730 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
731 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
732 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
733 /* VPIF Capture */
734 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
735 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
736 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
737 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
738 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
739 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
740 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
741 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
742 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
743 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
744 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
745 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
746 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
747 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
748 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
749 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
750 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
751 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
752 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
753 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
754 /* VPIF Display */
755 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
756 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
757 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
758 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
759 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
760 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
761 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
762 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
763 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
764 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
765 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
766 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
767 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
768 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
769 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
770 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
771 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
772 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
773 #endif
774 };
775
776 const short da850_i2c0_pins[] __initconst = {
777 DA850_I2C0_SDA, DA850_I2C0_SCL,
778 -1
779 };
780
781 const short da850_i2c1_pins[] __initconst = {
782 DA850_I2C1_SCL, DA850_I2C1_SDA,
783 -1
784 };
785
786 const short da850_lcdcntl_pins[] __initconst = {
787 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
788 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
789 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
790 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
791 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
792 -1
793 };
794
795 const short da850_vpif_capture_pins[] __initconst = {
796 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
797 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
798 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
799 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
800 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
801 DA850_VPIF_CLKIN3,
802 -1
803 };
804
805 const short da850_vpif_display_pins[] __initconst = {
806 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
807 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
808 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
809 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
810 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
811 DA850_VPIF_CLKO3,
812 -1
813 };
814
815 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
816 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
817 [IRQ_DA8XX_COMMTX] = 7,
818 [IRQ_DA8XX_COMMRX] = 7,
819 [IRQ_DA8XX_NINT] = 7,
820 [IRQ_DA8XX_EVTOUT0] = 7,
821 [IRQ_DA8XX_EVTOUT1] = 7,
822 [IRQ_DA8XX_EVTOUT2] = 7,
823 [IRQ_DA8XX_EVTOUT3] = 7,
824 [IRQ_DA8XX_EVTOUT4] = 7,
825 [IRQ_DA8XX_EVTOUT5] = 7,
826 [IRQ_DA8XX_EVTOUT6] = 7,
827 [IRQ_DA8XX_EVTOUT7] = 7,
828 [IRQ_DA8XX_CCINT0] = 7,
829 [IRQ_DA8XX_CCERRINT] = 7,
830 [IRQ_DA8XX_TCERRINT0] = 7,
831 [IRQ_DA8XX_AEMIFINT] = 7,
832 [IRQ_DA8XX_I2CINT0] = 7,
833 [IRQ_DA8XX_MMCSDINT0] = 7,
834 [IRQ_DA8XX_MMCSDINT1] = 7,
835 [IRQ_DA8XX_ALLINT0] = 7,
836 [IRQ_DA8XX_RTC] = 7,
837 [IRQ_DA8XX_SPINT0] = 7,
838 [IRQ_DA8XX_TINT12_0] = 7,
839 [IRQ_DA8XX_TINT34_0] = 7,
840 [IRQ_DA8XX_TINT12_1] = 7,
841 [IRQ_DA8XX_TINT34_1] = 7,
842 [IRQ_DA8XX_UARTINT0] = 7,
843 [IRQ_DA8XX_KEYMGRINT] = 7,
844 [IRQ_DA850_MPUADDRERR0] = 7,
845 [IRQ_DA8XX_CHIPINT0] = 7,
846 [IRQ_DA8XX_CHIPINT1] = 7,
847 [IRQ_DA8XX_CHIPINT2] = 7,
848 [IRQ_DA8XX_CHIPINT3] = 7,
849 [IRQ_DA8XX_TCERRINT1] = 7,
850 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
851 [IRQ_DA8XX_C0_RX_PULSE] = 7,
852 [IRQ_DA8XX_C0_TX_PULSE] = 7,
853 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
854 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
855 [IRQ_DA8XX_C1_RX_PULSE] = 7,
856 [IRQ_DA8XX_C1_TX_PULSE] = 7,
857 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
858 [IRQ_DA8XX_MEMERR] = 7,
859 [IRQ_DA8XX_GPIO0] = 7,
860 [IRQ_DA8XX_GPIO1] = 7,
861 [IRQ_DA8XX_GPIO2] = 7,
862 [IRQ_DA8XX_GPIO3] = 7,
863 [IRQ_DA8XX_GPIO4] = 7,
864 [IRQ_DA8XX_GPIO5] = 7,
865 [IRQ_DA8XX_GPIO6] = 7,
866 [IRQ_DA8XX_GPIO7] = 7,
867 [IRQ_DA8XX_GPIO8] = 7,
868 [IRQ_DA8XX_I2CINT1] = 7,
869 [IRQ_DA8XX_LCDINT] = 7,
870 [IRQ_DA8XX_UARTINT1] = 7,
871 [IRQ_DA8XX_MCASPINT] = 7,
872 [IRQ_DA8XX_ALLINT1] = 7,
873 [IRQ_DA8XX_SPINT1] = 7,
874 [IRQ_DA8XX_UHPI_INT1] = 7,
875 [IRQ_DA8XX_USB_INT] = 7,
876 [IRQ_DA8XX_IRQN] = 7,
877 [IRQ_DA8XX_RWAKEUP] = 7,
878 [IRQ_DA8XX_UARTINT2] = 7,
879 [IRQ_DA8XX_DFTSSINT] = 7,
880 [IRQ_DA8XX_EHRPWM0] = 7,
881 [IRQ_DA8XX_EHRPWM0TZ] = 7,
882 [IRQ_DA8XX_EHRPWM1] = 7,
883 [IRQ_DA8XX_EHRPWM1TZ] = 7,
884 [IRQ_DA850_SATAINT] = 7,
885 [IRQ_DA850_TINTALL_2] = 7,
886 [IRQ_DA8XX_ECAP0] = 7,
887 [IRQ_DA8XX_ECAP1] = 7,
888 [IRQ_DA8XX_ECAP2] = 7,
889 [IRQ_DA850_MMCSDINT0_1] = 7,
890 [IRQ_DA850_MMCSDINT1_1] = 7,
891 [IRQ_DA850_T12CMPINT0_2] = 7,
892 [IRQ_DA850_T12CMPINT1_2] = 7,
893 [IRQ_DA850_T12CMPINT2_2] = 7,
894 [IRQ_DA850_T12CMPINT3_2] = 7,
895 [IRQ_DA850_T12CMPINT4_2] = 7,
896 [IRQ_DA850_T12CMPINT5_2] = 7,
897 [IRQ_DA850_T12CMPINT6_2] = 7,
898 [IRQ_DA850_T12CMPINT7_2] = 7,
899 [IRQ_DA850_T12CMPINT0_3] = 7,
900 [IRQ_DA850_T12CMPINT1_3] = 7,
901 [IRQ_DA850_T12CMPINT2_3] = 7,
902 [IRQ_DA850_T12CMPINT3_3] = 7,
903 [IRQ_DA850_T12CMPINT4_3] = 7,
904 [IRQ_DA850_T12CMPINT5_3] = 7,
905 [IRQ_DA850_T12CMPINT6_3] = 7,
906 [IRQ_DA850_T12CMPINT7_3] = 7,
907 [IRQ_DA850_RPIINT] = 7,
908 [IRQ_DA850_VPIFINT] = 7,
909 [IRQ_DA850_CCINT1] = 7,
910 [IRQ_DA850_CCERRINT1] = 7,
911 [IRQ_DA850_TCERRINT2] = 7,
912 [IRQ_DA850_TINTALL_3] = 7,
913 [IRQ_DA850_MCBSP0RINT] = 7,
914 [IRQ_DA850_MCBSP0XINT] = 7,
915 [IRQ_DA850_MCBSP1RINT] = 7,
916 [IRQ_DA850_MCBSP1XINT] = 7,
917 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
918 };
919
920 static struct map_desc da850_io_desc[] = {
921 {
922 .virtual = IO_VIRT,
923 .pfn = __phys_to_pfn(IO_PHYS),
924 .length = IO_SIZE,
925 .type = MT_DEVICE
926 },
927 {
928 .virtual = DA8XX_CP_INTC_VIRT,
929 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
930 .length = DA8XX_CP_INTC_SIZE,
931 .type = MT_DEVICE
932 },
933 };
934
935 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
936
937 /* Contents of JTAG ID register used to identify exact cpu type */
938 static struct davinci_id da850_ids[] = {
939 {
940 .variant = 0x0,
941 .part_no = 0xb7d1,
942 .manufacturer = 0x017, /* 0x02f >> 1 */
943 .cpu_id = DAVINCI_CPU_ID_DA850,
944 .name = "da850/omap-l138",
945 },
946 {
947 .variant = 0x1,
948 .part_no = 0xb7d1,
949 .manufacturer = 0x017, /* 0x02f >> 1 */
950 .cpu_id = DAVINCI_CPU_ID_DA850,
951 .name = "da850/omap-l138/am18x",
952 },
953 };
954
955 static struct davinci_timer_instance da850_timer_instance[4] = {
956 {
957 .base = DA8XX_TIMER64P0_BASE,
958 .bottom_irq = IRQ_DA8XX_TINT12_0,
959 .top_irq = IRQ_DA8XX_TINT34_0,
960 },
961 {
962 .base = DA8XX_TIMER64P1_BASE,
963 .bottom_irq = IRQ_DA8XX_TINT12_1,
964 .top_irq = IRQ_DA8XX_TINT34_1,
965 },
966 {
967 .base = DA850_TIMER64P2_BASE,
968 .bottom_irq = IRQ_DA850_TINT12_2,
969 .top_irq = IRQ_DA850_TINT34_2,
970 },
971 {
972 .base = DA850_TIMER64P3_BASE,
973 .bottom_irq = IRQ_DA850_TINT12_3,
974 .top_irq = IRQ_DA850_TINT34_3,
975 },
976 };
977
978 /*
979 * T0_BOT: Timer 0, bottom : Used for clock_event
980 * T0_TOP: Timer 0, top : Used for clocksource
981 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
982 */
983 static struct davinci_timer_info da850_timer_info = {
984 .timers = da850_timer_instance,
985 .clockevent_id = T0_BOT,
986 .clocksource_id = T0_TOP,
987 };
988
989 #ifdef CONFIG_CPU_FREQ
990 /*
991 * Notes:
992 * According to the TRM, minimum PLLM results in maximum power savings.
993 * The OPP definitions below should keep the PLLM as low as possible.
994 *
995 * The output of the PLLM must be between 300 to 600 MHz.
996 */
997 struct da850_opp {
998 unsigned int freq; /* in KHz */
999 unsigned int prediv;
1000 unsigned int mult;
1001 unsigned int postdiv;
1002 unsigned int cvdd_min; /* in uV */
1003 unsigned int cvdd_max; /* in uV */
1004 };
1005
1006 static const struct da850_opp da850_opp_456 = {
1007 .freq = 456000,
1008 .prediv = 1,
1009 .mult = 19,
1010 .postdiv = 1,
1011 .cvdd_min = 1300000,
1012 .cvdd_max = 1350000,
1013 };
1014
1015 static const struct da850_opp da850_opp_408 = {
1016 .freq = 408000,
1017 .prediv = 1,
1018 .mult = 17,
1019 .postdiv = 1,
1020 .cvdd_min = 1300000,
1021 .cvdd_max = 1350000,
1022 };
1023
1024 static const struct da850_opp da850_opp_372 = {
1025 .freq = 372000,
1026 .prediv = 2,
1027 .mult = 31,
1028 .postdiv = 1,
1029 .cvdd_min = 1200000,
1030 .cvdd_max = 1320000,
1031 };
1032
1033 static const struct da850_opp da850_opp_300 = {
1034 .freq = 300000,
1035 .prediv = 1,
1036 .mult = 25,
1037 .postdiv = 2,
1038 .cvdd_min = 1200000,
1039 .cvdd_max = 1320000,
1040 };
1041
1042 static const struct da850_opp da850_opp_200 = {
1043 .freq = 200000,
1044 .prediv = 1,
1045 .mult = 25,
1046 .postdiv = 3,
1047 .cvdd_min = 1100000,
1048 .cvdd_max = 1160000,
1049 };
1050
1051 static const struct da850_opp da850_opp_96 = {
1052 .freq = 96000,
1053 .prediv = 1,
1054 .mult = 20,
1055 .postdiv = 5,
1056 .cvdd_min = 1000000,
1057 .cvdd_max = 1050000,
1058 };
1059
1060 #define OPP(freq) \
1061 { \
1062 .driver_data = (unsigned int) &da850_opp_##freq, \
1063 .frequency = freq * 1000, \
1064 }
1065
1066 static struct cpufreq_frequency_table da850_freq_table[] = {
1067 OPP(456),
1068 OPP(408),
1069 OPP(372),
1070 OPP(300),
1071 OPP(200),
1072 OPP(96),
1073 {
1074 .driver_data = 0,
1075 .frequency = CPUFREQ_TABLE_END,
1076 },
1077 };
1078
1079 #ifdef CONFIG_REGULATOR
1080 static int da850_set_voltage(unsigned int index);
1081 static int da850_regulator_init(void);
1082 #endif
1083
1084 static struct davinci_cpufreq_config cpufreq_info = {
1085 .freq_table = da850_freq_table,
1086 #ifdef CONFIG_REGULATOR
1087 .init = da850_regulator_init,
1088 .set_voltage = da850_set_voltage,
1089 #endif
1090 };
1091
1092 #ifdef CONFIG_REGULATOR
1093 static struct regulator *cvdd;
1094
1095 static int da850_set_voltage(unsigned int index)
1096 {
1097 struct da850_opp *opp;
1098
1099 if (!cvdd)
1100 return -ENODEV;
1101
1102 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1103
1104 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
1105 }
1106
1107 static int da850_regulator_init(void)
1108 {
1109 cvdd = regulator_get(NULL, "cvdd");
1110 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
1111 " voltage scaling unsupported\n")) {
1112 return PTR_ERR(cvdd);
1113 }
1114
1115 return 0;
1116 }
1117 #endif
1118
1119 static struct platform_device da850_cpufreq_device = {
1120 .name = "cpufreq-davinci",
1121 .dev = {
1122 .platform_data = &cpufreq_info,
1123 },
1124 .id = -1,
1125 };
1126
1127 unsigned int da850_max_speed = 300000;
1128
1129 int da850_register_cpufreq(char *async_clk)
1130 {
1131 int i;
1132
1133 /* cpufreq driver can help keep an "async" clock constant */
1134 if (async_clk)
1135 clk_add_alias("async", da850_cpufreq_device.name,
1136 async_clk, NULL);
1137 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
1138 if (da850_freq_table[i].frequency <= da850_max_speed) {
1139 cpufreq_info.freq_table = &da850_freq_table[i];
1140 break;
1141 }
1142 }
1143
1144 return platform_device_register(&da850_cpufreq_device);
1145 }
1146
1147 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1148 {
1149 int ret = 0, diff;
1150 unsigned int best = (unsigned int) -1;
1151 struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
1152 struct cpufreq_frequency_table *pos;
1153
1154 rate /= 1000; /* convert to kHz */
1155
1156 cpufreq_for_each_entry(pos, table) {
1157 diff = pos->frequency - rate;
1158 if (diff < 0)
1159 diff = -diff;
1160
1161 if (diff < best) {
1162 best = diff;
1163 ret = pos->frequency;
1164 }
1165 }
1166
1167 return ret * 1000;
1168 }
1169
1170 static int da850_set_armrate(struct clk *clk, unsigned long index)
1171 {
1172 struct clk *pllclk = &pll0_clk;
1173
1174 return clk_set_rate(pllclk, index);
1175 }
1176
1177 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1178 {
1179 unsigned int prediv, mult, postdiv;
1180 struct da850_opp *opp;
1181 struct pll_data *pll = clk->pll_data;
1182 int ret;
1183
1184 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1185 prediv = opp->prediv;
1186 mult = opp->mult;
1187 postdiv = opp->postdiv;
1188
1189 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1190 if (WARN_ON(ret))
1191 return ret;
1192
1193 return 0;
1194 }
1195 #else
1196 int __init da850_register_cpufreq(char *async_clk)
1197 {
1198 return 0;
1199 }
1200
1201 static int da850_set_armrate(struct clk *clk, unsigned long rate)
1202 {
1203 return -EINVAL;
1204 }
1205
1206 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1207 {
1208 return -EINVAL;
1209 }
1210
1211 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1212 {
1213 return clk->rate;
1214 }
1215 #endif
1216
1217 /* VPIF resource, platform data */
1218 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
1219
1220 static struct resource da850_vpif_resource[] = {
1221 {
1222 .start = DA8XX_VPIF_BASE,
1223 .end = DA8XX_VPIF_BASE + 0xfff,
1224 .flags = IORESOURCE_MEM,
1225 }
1226 };
1227
1228 static struct platform_device da850_vpif_dev = {
1229 .name = "vpif",
1230 .id = -1,
1231 .dev = {
1232 .dma_mask = &da850_vpif_dma_mask,
1233 .coherent_dma_mask = DMA_BIT_MASK(32),
1234 },
1235 .resource = da850_vpif_resource,
1236 .num_resources = ARRAY_SIZE(da850_vpif_resource),
1237 };
1238
1239 static struct resource da850_vpif_display_resource[] = {
1240 {
1241 .start = IRQ_DA850_VPIFINT,
1242 .end = IRQ_DA850_VPIFINT,
1243 .flags = IORESOURCE_IRQ,
1244 },
1245 };
1246
1247 static struct platform_device da850_vpif_display_dev = {
1248 .name = "vpif_display",
1249 .id = -1,
1250 .dev = {
1251 .dma_mask = &da850_vpif_dma_mask,
1252 .coherent_dma_mask = DMA_BIT_MASK(32),
1253 },
1254 .resource = da850_vpif_display_resource,
1255 .num_resources = ARRAY_SIZE(da850_vpif_display_resource),
1256 };
1257
1258 static struct resource da850_vpif_capture_resource[] = {
1259 {
1260 .start = IRQ_DA850_VPIFINT,
1261 .end = IRQ_DA850_VPIFINT,
1262 .flags = IORESOURCE_IRQ,
1263 },
1264 {
1265 .start = IRQ_DA850_VPIFINT,
1266 .end = IRQ_DA850_VPIFINT,
1267 .flags = IORESOURCE_IRQ,
1268 },
1269 };
1270
1271 static struct platform_device da850_vpif_capture_dev = {
1272 .name = "vpif_capture",
1273 .id = -1,
1274 .dev = {
1275 .dma_mask = &da850_vpif_dma_mask,
1276 .coherent_dma_mask = DMA_BIT_MASK(32),
1277 },
1278 .resource = da850_vpif_capture_resource,
1279 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
1280 };
1281
1282 int __init da850_register_vpif(void)
1283 {
1284 return platform_device_register(&da850_vpif_dev);
1285 }
1286
1287 int __init da850_register_vpif_display(struct vpif_display_config
1288 *display_config)
1289 {
1290 da850_vpif_display_dev.dev.platform_data = display_config;
1291 return platform_device_register(&da850_vpif_display_dev);
1292 }
1293
1294 int __init da850_register_vpif_capture(struct vpif_capture_config
1295 *capture_config)
1296 {
1297 da850_vpif_capture_dev.dev.platform_data = capture_config;
1298 return platform_device_register(&da850_vpif_capture_dev);
1299 }
1300
1301 static struct davinci_gpio_platform_data da850_gpio_platform_data = {
1302 .ngpio = 144,
1303 };
1304
1305 int __init da850_register_gpio(void)
1306 {
1307 return da8xx_register_gpio(&da850_gpio_platform_data);
1308 }
1309
1310 static struct davinci_soc_info davinci_soc_info_da850 = {
1311 .io_desc = da850_io_desc,
1312 .io_desc_num = ARRAY_SIZE(da850_io_desc),
1313 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1314 .ids = da850_ids,
1315 .ids_num = ARRAY_SIZE(da850_ids),
1316 .cpu_clks = da850_clks,
1317 .psc_bases = da850_psc_bases,
1318 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
1319 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
1320 .pinmux_pins = da850_pins,
1321 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1322 .intc_base = DA8XX_CP_INTC_BASE,
1323 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1324 .intc_irq_prios = da850_default_priorities,
1325 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1326 .timer_info = &da850_timer_info,
1327 .emac_pdata = &da8xx_emac_pdata,
1328 .sram_dma = DA8XX_SHARED_RAM_BASE,
1329 .sram_len = SZ_128K,
1330 };
1331
1332 void __init da850_init(void)
1333 {
1334 unsigned int v;
1335
1336 davinci_common_init(&davinci_soc_info_da850);
1337
1338 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1339 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1340 return;
1341
1342 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1343 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1344 return;
1345
1346 /* Unlock writing to PLL0 registers */
1347 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1348 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1349 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1350
1351 /* Unlock writing to PLL1 registers */
1352 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1353 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1354 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1355
1356 davinci_clk_init(davinci_soc_info_da850.cpu_clks);
1357 }
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