2 * DA8XX/OMAP L1XX platform device data
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/serial_8250.h>
17 #include <linux/ahci_platform.h>
18 #include <linux/clk.h>
20 #include <mach/cputype.h>
21 #include <mach/common.h>
22 #include <mach/time.h>
23 #include <mach/da8xx.h>
24 #include <mach/cpuidle.h>
29 #define DA8XX_TPCC_BASE 0x01c00000
30 #define DA8XX_TPTC0_BASE 0x01c08000
31 #define DA8XX_TPTC1_BASE 0x01c08400
32 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
33 #define DA8XX_I2C0_BASE 0x01c22000
34 #define DA8XX_RTC_BASE 0x01c23000
35 #define DA8XX_MMCSD0_BASE 0x01c40000
36 #define DA8XX_SPI0_BASE 0x01c41000
37 #define DA830_SPI1_BASE 0x01e12000
38 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
39 #define DA850_SATA_BASE 0x01e18000
40 #define DA850_MMCSD1_BASE 0x01e1b000
41 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
42 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
43 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
44 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
45 #define DA8XX_I2C1_BASE 0x01e28000
46 #define DA850_TPCC1_BASE 0x01e30000
47 #define DA850_TPTC2_BASE 0x01e38000
48 #define DA850_SPI1_BASE 0x01f0e000
49 #define DA8XX_DDR2_CTL_BASE 0xb0000000
51 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
52 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
53 #define DA8XX_EMAC_RAM_OFFSET 0x0000
54 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
56 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
57 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
58 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
59 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
60 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
61 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
62 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
63 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
65 void __iomem
*da8xx_syscfg0_base
;
66 void __iomem
*da8xx_syscfg1_base
;
68 static struct plat_serial8250_port da8xx_serial_pdata
[] = {
70 .mapbase
= DA8XX_UART0_BASE
,
71 .irq
= IRQ_DA8XX_UARTINT0
,
72 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
78 .mapbase
= DA8XX_UART1_BASE
,
79 .irq
= IRQ_DA8XX_UARTINT1
,
80 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
86 .mapbase
= DA8XX_UART2_BASE
,
87 .irq
= IRQ_DA8XX_UARTINT2
,
88 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
98 struct platform_device da8xx_serial_device
= {
100 .id
= PLAT8250_DEV_PLATFORM
,
102 .platform_data
= da8xx_serial_pdata
,
106 static const s8 da8xx_queue_tc_mapping
[][2] = {
107 /* {event queue no, TC no} */
113 static const s8 da8xx_queue_priority_mapping
[][2] = {
114 /* {event queue no, Priority} */
120 static const s8 da850_queue_tc_mapping
[][2] = {
121 /* {event queue no, TC no} */
126 static const s8 da850_queue_priority_mapping
[][2] = {
127 /* {event queue no, Priority} */
132 static struct edma_soc_info da830_edma_cc0_info
= {
138 .queue_tc_mapping
= da8xx_queue_tc_mapping
,
139 .queue_priority_mapping
= da8xx_queue_priority_mapping
,
140 .default_queue
= EVENTQ_1
,
143 static struct edma_soc_info
*da830_edma_info
[EDMA_MAX_CC
] = {
144 &da830_edma_cc0_info
,
147 static struct edma_soc_info da850_edma_cc_info
[] = {
154 .queue_tc_mapping
= da8xx_queue_tc_mapping
,
155 .queue_priority_mapping
= da8xx_queue_priority_mapping
,
156 .default_queue
= EVENTQ_1
,
164 .queue_tc_mapping
= da850_queue_tc_mapping
,
165 .queue_priority_mapping
= da850_queue_priority_mapping
,
166 .default_queue
= EVENTQ_0
,
170 static struct edma_soc_info
*da850_edma_info
[EDMA_MAX_CC
] = {
171 &da850_edma_cc_info
[0],
172 &da850_edma_cc_info
[1],
175 static struct resource da830_edma_resources
[] = {
178 .start
= DA8XX_TPCC_BASE
,
179 .end
= DA8XX_TPCC_BASE
+ SZ_32K
- 1,
180 .flags
= IORESOURCE_MEM
,
184 .start
= DA8XX_TPTC0_BASE
,
185 .end
= DA8XX_TPTC0_BASE
+ SZ_1K
- 1,
186 .flags
= IORESOURCE_MEM
,
190 .start
= DA8XX_TPTC1_BASE
,
191 .end
= DA8XX_TPTC1_BASE
+ SZ_1K
- 1,
192 .flags
= IORESOURCE_MEM
,
196 .start
= IRQ_DA8XX_CCINT0
,
197 .flags
= IORESOURCE_IRQ
,
201 .start
= IRQ_DA8XX_CCERRINT
,
202 .flags
= IORESOURCE_IRQ
,
206 static struct resource da850_edma_resources
[] = {
209 .start
= DA8XX_TPCC_BASE
,
210 .end
= DA8XX_TPCC_BASE
+ SZ_32K
- 1,
211 .flags
= IORESOURCE_MEM
,
215 .start
= DA8XX_TPTC0_BASE
,
216 .end
= DA8XX_TPTC0_BASE
+ SZ_1K
- 1,
217 .flags
= IORESOURCE_MEM
,
221 .start
= DA8XX_TPTC1_BASE
,
222 .end
= DA8XX_TPTC1_BASE
+ SZ_1K
- 1,
223 .flags
= IORESOURCE_MEM
,
227 .start
= DA850_TPCC1_BASE
,
228 .end
= DA850_TPCC1_BASE
+ SZ_32K
- 1,
229 .flags
= IORESOURCE_MEM
,
233 .start
= DA850_TPTC2_BASE
,
234 .end
= DA850_TPTC2_BASE
+ SZ_1K
- 1,
235 .flags
= IORESOURCE_MEM
,
239 .start
= IRQ_DA8XX_CCINT0
,
240 .flags
= IORESOURCE_IRQ
,
244 .start
= IRQ_DA8XX_CCERRINT
,
245 .flags
= IORESOURCE_IRQ
,
249 .start
= IRQ_DA850_CCINT1
,
250 .flags
= IORESOURCE_IRQ
,
254 .start
= IRQ_DA850_CCERRINT1
,
255 .flags
= IORESOURCE_IRQ
,
259 static struct platform_device da830_edma_device
= {
263 .platform_data
= da830_edma_info
,
265 .num_resources
= ARRAY_SIZE(da830_edma_resources
),
266 .resource
= da830_edma_resources
,
269 static struct platform_device da850_edma_device
= {
273 .platform_data
= da850_edma_info
,
275 .num_resources
= ARRAY_SIZE(da850_edma_resources
),
276 .resource
= da850_edma_resources
,
279 int __init
da830_register_edma(struct edma_rsv_info
*rsv
)
281 da830_edma_cc0_info
.rsv
= rsv
;
283 return platform_device_register(&da830_edma_device
);
286 int __init
da850_register_edma(struct edma_rsv_info
*rsv
[2])
289 da850_edma_cc_info
[0].rsv
= rsv
[0];
290 da850_edma_cc_info
[1].rsv
= rsv
[1];
293 return platform_device_register(&da850_edma_device
);
296 static struct resource da8xx_i2c_resources0
[] = {
298 .start
= DA8XX_I2C0_BASE
,
299 .end
= DA8XX_I2C0_BASE
+ SZ_4K
- 1,
300 .flags
= IORESOURCE_MEM
,
303 .start
= IRQ_DA8XX_I2CINT0
,
304 .end
= IRQ_DA8XX_I2CINT0
,
305 .flags
= IORESOURCE_IRQ
,
309 static struct platform_device da8xx_i2c_device0
= {
310 .name
= "i2c_davinci",
312 .num_resources
= ARRAY_SIZE(da8xx_i2c_resources0
),
313 .resource
= da8xx_i2c_resources0
,
316 static struct resource da8xx_i2c_resources1
[] = {
318 .start
= DA8XX_I2C1_BASE
,
319 .end
= DA8XX_I2C1_BASE
+ SZ_4K
- 1,
320 .flags
= IORESOURCE_MEM
,
323 .start
= IRQ_DA8XX_I2CINT1
,
324 .end
= IRQ_DA8XX_I2CINT1
,
325 .flags
= IORESOURCE_IRQ
,
329 static struct platform_device da8xx_i2c_device1
= {
330 .name
= "i2c_davinci",
332 .num_resources
= ARRAY_SIZE(da8xx_i2c_resources1
),
333 .resource
= da8xx_i2c_resources1
,
336 int __init
da8xx_register_i2c(int instance
,
337 struct davinci_i2c_platform_data
*pdata
)
339 struct platform_device
*pdev
;
342 pdev
= &da8xx_i2c_device0
;
343 else if (instance
== 1)
344 pdev
= &da8xx_i2c_device1
;
348 pdev
->dev
.platform_data
= pdata
;
349 return platform_device_register(pdev
);
352 static struct resource da8xx_watchdog_resources
[] = {
354 .start
= DA8XX_WDOG_BASE
,
355 .end
= DA8XX_WDOG_BASE
+ SZ_4K
- 1,
356 .flags
= IORESOURCE_MEM
,
360 struct platform_device da8xx_wdt_device
= {
363 .num_resources
= ARRAY_SIZE(da8xx_watchdog_resources
),
364 .resource
= da8xx_watchdog_resources
,
367 void da8xx_restart(char mode
, const char *cmd
)
369 davinci_watchdog_reset(&da8xx_wdt_device
);
372 int __init
da8xx_register_watchdog(void)
374 return platform_device_register(&da8xx_wdt_device
);
377 static struct resource da8xx_emac_resources
[] = {
379 .start
= DA8XX_EMAC_CPPI_PORT_BASE
,
380 .end
= DA8XX_EMAC_CPPI_PORT_BASE
+ SZ_16K
- 1,
381 .flags
= IORESOURCE_MEM
,
384 .start
= IRQ_DA8XX_C0_RX_THRESH_PULSE
,
385 .end
= IRQ_DA8XX_C0_RX_THRESH_PULSE
,
386 .flags
= IORESOURCE_IRQ
,
389 .start
= IRQ_DA8XX_C0_RX_PULSE
,
390 .end
= IRQ_DA8XX_C0_RX_PULSE
,
391 .flags
= IORESOURCE_IRQ
,
394 .start
= IRQ_DA8XX_C0_TX_PULSE
,
395 .end
= IRQ_DA8XX_C0_TX_PULSE
,
396 .flags
= IORESOURCE_IRQ
,
399 .start
= IRQ_DA8XX_C0_MISC_PULSE
,
400 .end
= IRQ_DA8XX_C0_MISC_PULSE
,
401 .flags
= IORESOURCE_IRQ
,
405 struct emac_platform_data da8xx_emac_pdata
= {
406 .ctrl_reg_offset
= DA8XX_EMAC_CTRL_REG_OFFSET
,
407 .ctrl_mod_reg_offset
= DA8XX_EMAC_MOD_REG_OFFSET
,
408 .ctrl_ram_offset
= DA8XX_EMAC_RAM_OFFSET
,
409 .ctrl_ram_size
= DA8XX_EMAC_CTRL_RAM_SIZE
,
410 .version
= EMAC_VERSION_2
,
413 static struct platform_device da8xx_emac_device
= {
414 .name
= "davinci_emac",
417 .platform_data
= &da8xx_emac_pdata
,
419 .num_resources
= ARRAY_SIZE(da8xx_emac_resources
),
420 .resource
= da8xx_emac_resources
,
423 static struct resource da8xx_mdio_resources
[] = {
425 .start
= DA8XX_EMAC_MDIO_BASE
,
426 .end
= DA8XX_EMAC_MDIO_BASE
+ SZ_4K
- 1,
427 .flags
= IORESOURCE_MEM
,
431 static struct platform_device da8xx_mdio_device
= {
432 .name
= "davinci_mdio",
434 .num_resources
= ARRAY_SIZE(da8xx_mdio_resources
),
435 .resource
= da8xx_mdio_resources
,
438 int __init
da8xx_register_emac(void)
442 ret
= platform_device_register(&da8xx_mdio_device
);
445 ret
= platform_device_register(&da8xx_emac_device
);
448 ret
= clk_add_alias(NULL
, dev_name(&da8xx_mdio_device
.dev
),
449 NULL
, &da8xx_emac_device
.dev
);
453 static struct resource da830_mcasp1_resources
[] = {
456 .start
= DAVINCI_DA830_MCASP1_REG_BASE
,
457 .end
= DAVINCI_DA830_MCASP1_REG_BASE
+ (SZ_1K
* 12) - 1,
458 .flags
= IORESOURCE_MEM
,
462 .start
= DAVINCI_DA830_DMA_MCASP1_AXEVT
,
463 .end
= DAVINCI_DA830_DMA_MCASP1_AXEVT
,
464 .flags
= IORESOURCE_DMA
,
468 .start
= DAVINCI_DA830_DMA_MCASP1_AREVT
,
469 .end
= DAVINCI_DA830_DMA_MCASP1_AREVT
,
470 .flags
= IORESOURCE_DMA
,
474 static struct platform_device da830_mcasp1_device
= {
475 .name
= "davinci-mcasp",
477 .num_resources
= ARRAY_SIZE(da830_mcasp1_resources
),
478 .resource
= da830_mcasp1_resources
,
481 static struct resource da850_mcasp_resources
[] = {
484 .start
= DAVINCI_DA8XX_MCASP0_REG_BASE
,
485 .end
= DAVINCI_DA8XX_MCASP0_REG_BASE
+ (SZ_1K
* 12) - 1,
486 .flags
= IORESOURCE_MEM
,
490 .start
= DAVINCI_DA8XX_DMA_MCASP0_AXEVT
,
491 .end
= DAVINCI_DA8XX_DMA_MCASP0_AXEVT
,
492 .flags
= IORESOURCE_DMA
,
496 .start
= DAVINCI_DA8XX_DMA_MCASP0_AREVT
,
497 .end
= DAVINCI_DA8XX_DMA_MCASP0_AREVT
,
498 .flags
= IORESOURCE_DMA
,
502 static struct platform_device da850_mcasp_device
= {
503 .name
= "davinci-mcasp",
505 .num_resources
= ARRAY_SIZE(da850_mcasp_resources
),
506 .resource
= da850_mcasp_resources
,
509 void __init
da8xx_register_mcasp(int id
, struct snd_platform_data
*pdata
)
511 /* DA830/OMAP-L137 has 3 instances of McASP */
512 if (cpu_is_davinci_da830() && id
== 1) {
513 da830_mcasp1_device
.dev
.platform_data
= pdata
;
514 platform_device_register(&da830_mcasp1_device
);
515 } else if (cpu_is_davinci_da850()) {
516 da850_mcasp_device
.dev
.platform_data
= pdata
;
517 platform_device_register(&da850_mcasp_device
);
521 static const struct display_panel disp_panel
= {
528 static struct lcd_ctrl_config lcd_cfg
= {
538 .invert_line_clock
= 1,
539 .invert_frm_clock
= 1,
546 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata
= {
547 .manu_name
= "sharp",
548 .controller_data
= &lcd_cfg
,
549 .type
= "Sharp_LCD035Q3DG01",
552 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata
= {
553 .manu_name
= "sharp",
554 .controller_data
= &lcd_cfg
,
555 .type
= "Sharp_LK043T1DG01",
558 static struct resource da8xx_lcdc_resources
[] = {
559 [0] = { /* registers */
560 .start
= DA8XX_LCD_CNTRL_BASE
,
561 .end
= DA8XX_LCD_CNTRL_BASE
+ SZ_4K
- 1,
562 .flags
= IORESOURCE_MEM
,
564 [1] = { /* interrupt */
565 .start
= IRQ_DA8XX_LCDINT
,
566 .end
= IRQ_DA8XX_LCDINT
,
567 .flags
= IORESOURCE_IRQ
,
571 static struct platform_device da8xx_lcdc_device
= {
572 .name
= "da8xx_lcdc",
574 .num_resources
= ARRAY_SIZE(da8xx_lcdc_resources
),
575 .resource
= da8xx_lcdc_resources
,
578 int __init
da8xx_register_lcdc(struct da8xx_lcdc_platform_data
*pdata
)
580 da8xx_lcdc_device
.dev
.platform_data
= pdata
;
581 return platform_device_register(&da8xx_lcdc_device
);
584 static struct resource da8xx_mmcsd0_resources
[] = {
586 .start
= DA8XX_MMCSD0_BASE
,
587 .end
= DA8XX_MMCSD0_BASE
+ SZ_4K
- 1,
588 .flags
= IORESOURCE_MEM
,
591 .start
= IRQ_DA8XX_MMCSDINT0
,
592 .end
= IRQ_DA8XX_MMCSDINT0
,
593 .flags
= IORESOURCE_IRQ
,
596 .start
= DA8XX_DMA_MMCSD0_RX
,
597 .end
= DA8XX_DMA_MMCSD0_RX
,
598 .flags
= IORESOURCE_DMA
,
601 .start
= DA8XX_DMA_MMCSD0_TX
,
602 .end
= DA8XX_DMA_MMCSD0_TX
,
603 .flags
= IORESOURCE_DMA
,
607 static struct platform_device da8xx_mmcsd0_device
= {
608 .name
= "davinci_mmc",
610 .num_resources
= ARRAY_SIZE(da8xx_mmcsd0_resources
),
611 .resource
= da8xx_mmcsd0_resources
,
614 int __init
da8xx_register_mmcsd0(struct davinci_mmc_config
*config
)
616 da8xx_mmcsd0_device
.dev
.platform_data
= config
;
617 return platform_device_register(&da8xx_mmcsd0_device
);
620 #ifdef CONFIG_ARCH_DAVINCI_DA850
621 static struct resource da850_mmcsd1_resources
[] = {
623 .start
= DA850_MMCSD1_BASE
,
624 .end
= DA850_MMCSD1_BASE
+ SZ_4K
- 1,
625 .flags
= IORESOURCE_MEM
,
628 .start
= IRQ_DA850_MMCSDINT0_1
,
629 .end
= IRQ_DA850_MMCSDINT0_1
,
630 .flags
= IORESOURCE_IRQ
,
633 .start
= DA850_DMA_MMCSD1_RX
,
634 .end
= DA850_DMA_MMCSD1_RX
,
635 .flags
= IORESOURCE_DMA
,
638 .start
= DA850_DMA_MMCSD1_TX
,
639 .end
= DA850_DMA_MMCSD1_TX
,
640 .flags
= IORESOURCE_DMA
,
644 static struct platform_device da850_mmcsd1_device
= {
645 .name
= "davinci_mmc",
647 .num_resources
= ARRAY_SIZE(da850_mmcsd1_resources
),
648 .resource
= da850_mmcsd1_resources
,
651 int __init
da850_register_mmcsd1(struct davinci_mmc_config
*config
)
653 da850_mmcsd1_device
.dev
.platform_data
= config
;
654 return platform_device_register(&da850_mmcsd1_device
);
658 static struct resource da8xx_rtc_resources
[] = {
660 .start
= DA8XX_RTC_BASE
,
661 .end
= DA8XX_RTC_BASE
+ SZ_4K
- 1,
662 .flags
= IORESOURCE_MEM
,
665 .start
= IRQ_DA8XX_RTC
,
666 .end
= IRQ_DA8XX_RTC
,
667 .flags
= IORESOURCE_IRQ
,
670 .start
= IRQ_DA8XX_RTC
,
671 .end
= IRQ_DA8XX_RTC
,
672 .flags
= IORESOURCE_IRQ
,
676 static struct platform_device da8xx_rtc_device
= {
679 .num_resources
= ARRAY_SIZE(da8xx_rtc_resources
),
680 .resource
= da8xx_rtc_resources
,
683 int da8xx_register_rtc(void)
688 base
= ioremap(DA8XX_RTC_BASE
, SZ_4K
);
692 /* Unlock the rtc's registers */
693 __raw_writel(0x83e70b13, base
+ 0x6c);
694 __raw_writel(0x95a4f1e0, base
+ 0x70);
698 ret
= platform_device_register(&da8xx_rtc_device
);
700 /* Atleast on DA850, RTC is a wakeup source */
701 device_init_wakeup(&da8xx_rtc_device
.dev
, true);
706 static void __iomem
*da8xx_ddr2_ctlr_base
;
707 void __iomem
* __init
da8xx_get_mem_ctlr(void)
709 if (da8xx_ddr2_ctlr_base
)
710 return da8xx_ddr2_ctlr_base
;
712 da8xx_ddr2_ctlr_base
= ioremap(DA8XX_DDR2_CTL_BASE
, SZ_32K
);
713 if (!da8xx_ddr2_ctlr_base
)
714 pr_warning("%s: Unable to map DDR2 controller", __func__
);
716 return da8xx_ddr2_ctlr_base
;
719 static struct resource da8xx_cpuidle_resources
[] = {
721 .start
= DA8XX_DDR2_CTL_BASE
,
722 .end
= DA8XX_DDR2_CTL_BASE
+ SZ_32K
- 1,
723 .flags
= IORESOURCE_MEM
,
727 /* DA8XX devices support DDR2 power down */
728 static struct davinci_cpuidle_config da8xx_cpuidle_pdata
= {
733 static struct platform_device da8xx_cpuidle_device
= {
734 .name
= "cpuidle-davinci",
735 .num_resources
= ARRAY_SIZE(da8xx_cpuidle_resources
),
736 .resource
= da8xx_cpuidle_resources
,
738 .platform_data
= &da8xx_cpuidle_pdata
,
742 int __init
da8xx_register_cpuidle(void)
744 da8xx_cpuidle_pdata
.ddr2_ctlr_base
= da8xx_get_mem_ctlr();
746 return platform_device_register(&da8xx_cpuidle_device
);
749 static struct resource da8xx_spi0_resources
[] = {
751 .start
= DA8XX_SPI0_BASE
,
752 .end
= DA8XX_SPI0_BASE
+ SZ_4K
- 1,
753 .flags
= IORESOURCE_MEM
,
756 .start
= IRQ_DA8XX_SPINT0
,
757 .end
= IRQ_DA8XX_SPINT0
,
758 .flags
= IORESOURCE_IRQ
,
761 .start
= DA8XX_DMA_SPI0_RX
,
762 .end
= DA8XX_DMA_SPI0_RX
,
763 .flags
= IORESOURCE_DMA
,
766 .start
= DA8XX_DMA_SPI0_TX
,
767 .end
= DA8XX_DMA_SPI0_TX
,
768 .flags
= IORESOURCE_DMA
,
772 static struct resource da8xx_spi1_resources
[] = {
774 .start
= DA830_SPI1_BASE
,
775 .end
= DA830_SPI1_BASE
+ SZ_4K
- 1,
776 .flags
= IORESOURCE_MEM
,
779 .start
= IRQ_DA8XX_SPINT1
,
780 .end
= IRQ_DA8XX_SPINT1
,
781 .flags
= IORESOURCE_IRQ
,
784 .start
= DA8XX_DMA_SPI1_RX
,
785 .end
= DA8XX_DMA_SPI1_RX
,
786 .flags
= IORESOURCE_DMA
,
789 .start
= DA8XX_DMA_SPI1_TX
,
790 .end
= DA8XX_DMA_SPI1_TX
,
791 .flags
= IORESOURCE_DMA
,
795 struct davinci_spi_platform_data da8xx_spi_pdata
[] = {
797 .version
= SPI_VERSION_2
,
799 .dma_event_q
= EVENTQ_0
,
802 .version
= SPI_VERSION_2
,
804 .dma_event_q
= EVENTQ_0
,
808 static struct platform_device da8xx_spi_device
[] = {
810 .name
= "spi_davinci",
812 .num_resources
= ARRAY_SIZE(da8xx_spi0_resources
),
813 .resource
= da8xx_spi0_resources
,
815 .platform_data
= &da8xx_spi_pdata
[0],
819 .name
= "spi_davinci",
821 .num_resources
= ARRAY_SIZE(da8xx_spi1_resources
),
822 .resource
= da8xx_spi1_resources
,
824 .platform_data
= &da8xx_spi_pdata
[1],
829 int __init
da8xx_register_spi(int instance
, const struct spi_board_info
*info
,
834 if (instance
< 0 || instance
> 1)
837 ret
= spi_register_board_info(info
, len
);
839 pr_warning("%s: failed to register board info for spi %d :"
840 " %d\n", __func__
, instance
, ret
);
842 da8xx_spi_pdata
[instance
].num_chipselect
= len
;
844 if (instance
== 1 && cpu_is_davinci_da850()) {
845 da8xx_spi1_resources
[0].start
= DA850_SPI1_BASE
;
846 da8xx_spi1_resources
[0].end
= DA850_SPI1_BASE
+ SZ_4K
- 1;
849 return platform_device_register(&da8xx_spi_device
[instance
]);
852 #ifdef CONFIG_ARCH_DAVINCI_DA850
854 static struct resource da850_sata_resources
[] = {
856 .start
= DA850_SATA_BASE
,
857 .end
= DA850_SATA_BASE
+ 0x1fff,
858 .flags
= IORESOURCE_MEM
,
861 .start
= IRQ_DA850_SATAINT
,
862 .flags
= IORESOURCE_IRQ
,
866 /* SATA PHY Control Register offset from AHCI base */
867 #define SATA_P0PHYCR_REG 0x178
869 #define SATA_PHY_MPY(x) ((x) << 0)
870 #define SATA_PHY_LOS(x) ((x) << 6)
871 #define SATA_PHY_RXCDR(x) ((x) << 10)
872 #define SATA_PHY_RXEQ(x) ((x) << 13)
873 #define SATA_PHY_TXSWING(x) ((x) << 19)
874 #define SATA_PHY_ENPLL(x) ((x) << 31)
876 static struct clk
*da850_sata_clk
;
877 static unsigned long da850_sata_refclkpn
;
879 /* Supported DA850 SATA crystal frequencies */
880 #define KHZ_TO_HZ(freq) ((freq) * 1000)
881 static unsigned long da850_sata_xtal
[] = {
894 static int da850_sata_init(struct device
*dev
, void __iomem
*addr
)
899 da850_sata_clk
= clk_get(dev
, NULL
);
900 if (IS_ERR(da850_sata_clk
))
901 return PTR_ERR(da850_sata_clk
);
903 ret
= clk_prepare_enable(da850_sata_clk
);
907 /* Enable SATA clock receiver */
908 val
= __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG
));
910 __raw_writel(val
, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG
));
912 /* Get the multiplier needed for 1.5GHz PLL output */
913 for (i
= 0; i
< ARRAY_SIZE(da850_sata_xtal
); i
++)
914 if (da850_sata_xtal
[i
] == da850_sata_refclkpn
)
917 if (i
== ARRAY_SIZE(da850_sata_xtal
)) {
922 val
= SATA_PHY_MPY(i
+ 1) |
926 SATA_PHY_TXSWING(3) |
929 __raw_writel(val
, addr
+ SATA_P0PHYCR_REG
);
934 clk_disable_unprepare(da850_sata_clk
);
936 clk_put(da850_sata_clk
);
940 static void da850_sata_exit(struct device
*dev
)
942 clk_disable_unprepare(da850_sata_clk
);
943 clk_put(da850_sata_clk
);
946 static struct ahci_platform_data da850_sata_pdata
= {
947 .init
= da850_sata_init
,
948 .exit
= da850_sata_exit
,
951 static u64 da850_sata_dmamask
= DMA_BIT_MASK(32);
953 static struct platform_device da850_sata_device
= {
957 .platform_data
= &da850_sata_pdata
,
958 .dma_mask
= &da850_sata_dmamask
,
959 .coherent_dma_mask
= DMA_BIT_MASK(32),
961 .num_resources
= ARRAY_SIZE(da850_sata_resources
),
962 .resource
= da850_sata_resources
,
965 int __init
da850_register_sata(unsigned long refclkpn
)
967 da850_sata_refclkpn
= refclkpn
;
968 if (!da850_sata_refclkpn
)
971 return platform_device_register(&da850_sata_device
);