arch/arm/mach-davinci/dm355.c

   1 /*
   2  * TI DaVinci DM355 chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/clk.h>
  13 #include <linux/serial_8250.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17
  18 #include <linux/spi/spi.h>
  19
  20 #include <asm/mach/map.h>
  21
  22 #include <mach/dm355.h>
  23 #include <mach/cputype.h>
  24 #include <mach/edma.h>
  25 #include <mach/psc.h>
  26 #include <mach/mux.h>
  27 #include <mach/irqs.h>
  28 #include <mach/time.h>
  29 #include <mach/serial.h>
  30 #include <mach/common.h>
  31 #include <mach/asp.h>
  32 #include <mach/spi.h>
  33
  34 #include "clock.h"
  35 #include "mux.h"
  36
  37 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
  38
  39 /*
  40  * Device specific clocks
  41  */
  42 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  43
  44 static struct pll_data pll1_data = {
  45         .num       = 1,
  46         .phys_base = DAVINCI_PLL1_BASE,
  47         .flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  48 };
  49
  50 static struct pll_data pll2_data = {
  51         .num       = 2,
  52         .phys_base = DAVINCI_PLL2_BASE,
  53         .flags     = PLL_HAS_PREDIV,
  54 };
  55
  56 static struct clk ref_clk = {
  57         .name = "ref_clk",
  58         /* FIXME -- crystal rate is board-specific */
  59         .rate = DM355_REF_FREQ,
  60 };
  61
  62 static struct clk pll1_clk = {
  63         .name = "pll1",
  64         .parent = &ref_clk,
  65         .flags = CLK_PLL,
  66         .pll_data = &pll1_data,
  67 };
  68
  69 static struct clk pll1_aux_clk = {
  70         .name = "pll1_aux_clk",
  71         .parent = &pll1_clk,
  72         .flags = CLK_PLL | PRE_PLL,
  73 };
  74
  75 static struct clk pll1_sysclk1 = {
  76         .name = "pll1_sysclk1",
  77         .parent = &pll1_clk,
  78         .flags = CLK_PLL,
  79         .div_reg = PLLDIV1,
  80 };
  81
  82 static struct clk pll1_sysclk2 = {
  83         .name = "pll1_sysclk2",
  84         .parent = &pll1_clk,
  85         .flags = CLK_PLL,
  86         .div_reg = PLLDIV2,
  87 };
  88
  89 static struct clk pll1_sysclk3 = {
  90         .name = "pll1_sysclk3",
  91         .parent = &pll1_clk,
  92         .flags = CLK_PLL,
  93         .div_reg = PLLDIV3,
  94 };
  95
  96 static struct clk pll1_sysclk4 = {
  97         .name = "pll1_sysclk4",
  98         .parent = &pll1_clk,
  99         .flags = CLK_PLL,
 100         .div_reg = PLLDIV4,
 101 };
 102
 103 static struct clk pll1_sysclkbp = {
 104         .name = "pll1_sysclkbp",
 105         .parent = &pll1_clk,
 106         .flags = CLK_PLL | PRE_PLL,
 107         .div_reg = BPDIV
 108 };
 109
 110 static struct clk vpss_dac_clk = {
 111         .name = "vpss_dac",
 112         .parent = &pll1_sysclk3,
 113         .lpsc = DM355_LPSC_VPSS_DAC,
 114 };
 115
 116 static struct clk vpss_master_clk = {
 117         .name = "vpss_master",
 118         .parent = &pll1_sysclk4,
 119         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 120         .flags = CLK_PSC,
 121 };
 122
 123 static struct clk vpss_slave_clk = {
 124         .name = "vpss_slave",
 125         .parent = &pll1_sysclk4,
 126         .lpsc = DAVINCI_LPSC_VPSSSLV,
 127 };
 128
 129
 130 static struct clk clkout1_clk = {
 131         .name = "clkout1",
 132         .parent = &pll1_aux_clk,
 133         /* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
 134 };
 135
 136 static struct clk clkout2_clk = {
 137         .name = "clkout2",
 138         .parent = &pll1_sysclkbp,
 139 };
 140
 141 static struct clk pll2_clk = {
 142         .name = "pll2",
 143         .parent = &ref_clk,
 144         .flags = CLK_PLL,
 145         .pll_data = &pll2_data,
 146 };
 147
 148 static struct clk pll2_sysclk1 = {
 149         .name = "pll2_sysclk1",
 150         .parent = &pll2_clk,
 151         .flags = CLK_PLL,
 152         .div_reg = PLLDIV1,
 153 };
 154
 155 static struct clk pll2_sysclkbp = {
 156         .name = "pll2_sysclkbp",
 157         .parent = &pll2_clk,
 158         .flags = CLK_PLL | PRE_PLL,
 159         .div_reg = BPDIV
 160 };
 161
 162 static struct clk clkout3_clk = {
 163         .name = "clkout3",
 164         .parent = &pll2_sysclkbp,
 165         /* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
 166 };
 167
 168 static struct clk arm_clk = {
 169         .name = "arm_clk",
 170         .parent = &pll1_sysclk1,
 171         .lpsc = DAVINCI_LPSC_ARM,
 172         .flags = ALWAYS_ENABLED,
 173 };
 174
 175 /*
 176  * NOT LISTED below, and not touched by Linux
 177  *   - in SyncReset state by default
 178  *      .lpsc = DAVINCI_LPSC_TPCC,
 179  *      .lpsc = DAVINCI_LPSC_TPTC0,
 180  *      .lpsc = DAVINCI_LPSC_TPTC1,
 181  *      .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 182  *      .lpsc = DAVINCI_LPSC_MEMSTICK,
 183  *   - in Enabled state by default
 184  *      .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 185  *      .lpsc = DAVINCI_LPSC_SCR2,      // "bus"
 186  *      .lpsc = DAVINCI_LPSC_SCR3,      // "bus"
 187  *      .lpsc = DAVINCI_LPSC_SCR4,      // "bus"
 188  *      .lpsc = DAVINCI_LPSC_CROSSBAR,  // "emulation"
 189  *      .lpsc = DAVINCI_LPSC_CFG27,     // "test"
 190  *      .lpsc = DAVINCI_LPSC_CFG3,      // "test"
 191  *      .lpsc = DAVINCI_LPSC_CFG5,      // "test"
 192  */
 193
 194 static struct clk mjcp_clk = {
 195         .name = "mjcp",
 196         .parent = &pll1_sysclk1,
 197         .lpsc = DAVINCI_LPSC_IMCOP,
 198 };
 199
 200 static struct clk uart0_clk = {
 201         .name = "uart0",
 202         .parent = &pll1_aux_clk,
 203         .lpsc = DAVINCI_LPSC_UART0,
 204 };
 205
 206 static struct clk uart1_clk = {
 207         .name = "uart1",
 208         .parent = &pll1_aux_clk,
 209         .lpsc = DAVINCI_LPSC_UART1,
 210 };
 211
 212 static struct clk uart2_clk = {
 213         .name = "uart2",
 214         .parent = &pll1_sysclk2,
 215         .lpsc = DAVINCI_LPSC_UART2,
 216 };
 217
 218 static struct clk i2c_clk = {
 219         .name = "i2c",
 220         .parent = &pll1_aux_clk,
 221         .lpsc = DAVINCI_LPSC_I2C,
 222 };
 223
 224 static struct clk asp0_clk = {
 225         .name = "asp0",
 226         .parent = &pll1_sysclk2,
 227         .lpsc = DAVINCI_LPSC_McBSP,
 228 };
 229
 230 static struct clk asp1_clk = {
 231         .name = "asp1",
 232         .parent = &pll1_sysclk2,
 233         .lpsc = DM355_LPSC_McBSP1,
 234 };
 235
 236 static struct clk mmcsd0_clk = {
 237         .name = "mmcsd0",
 238         .parent = &pll1_sysclk2,
 239         .lpsc = DAVINCI_LPSC_MMC_SD,
 240 };
 241
 242 static struct clk mmcsd1_clk = {
 243         .name = "mmcsd1",
 244         .parent = &pll1_sysclk2,
 245         .lpsc = DM355_LPSC_MMC_SD1,
 246 };
 247
 248 static struct clk spi0_clk = {
 249         .name = "spi0",
 250         .parent = &pll1_sysclk2,
 251         .lpsc = DAVINCI_LPSC_SPI,
 252 };
 253
 254 static struct clk spi1_clk = {
 255         .name = "spi1",
 256         .parent = &pll1_sysclk2,
 257         .lpsc = DM355_LPSC_SPI1,
 258 };
 259
 260 static struct clk spi2_clk = {
 261         .name = "spi2",
 262         .parent = &pll1_sysclk2,
 263         .lpsc = DM355_LPSC_SPI2,
 264 };
 265
 266 static struct clk gpio_clk = {
 267         .name = "gpio",
 268         .parent = &pll1_sysclk2,
 269         .lpsc = DAVINCI_LPSC_GPIO,
 270 };
 271
 272 static struct clk aemif_clk = {
 273         .name = "aemif",
 274         .parent = &pll1_sysclk2,
 275         .lpsc = DAVINCI_LPSC_AEMIF,
 276 };
 277
 278 static struct clk pwm0_clk = {
 279         .name = "pwm0",
 280         .parent = &pll1_aux_clk,
 281         .lpsc = DAVINCI_LPSC_PWM0,
 282 };
 283
 284 static struct clk pwm1_clk = {
 285         .name = "pwm1",
 286         .parent = &pll1_aux_clk,
 287         .lpsc = DAVINCI_LPSC_PWM1,
 288 };
 289
 290 static struct clk pwm2_clk = {
 291         .name = "pwm2",
 292         .parent = &pll1_aux_clk,
 293         .lpsc = DAVINCI_LPSC_PWM2,
 294 };
 295
 296 static struct clk pwm3_clk = {
 297         .name = "pwm3",
 298         .parent = &pll1_aux_clk,
 299         .lpsc = DM355_LPSC_PWM3,
 300 };
 301
 302 static struct clk timer0_clk = {
 303         .name = "timer0",
 304         .parent = &pll1_aux_clk,
 305         .lpsc = DAVINCI_LPSC_TIMER0,
 306 };
 307
 308 static struct clk timer1_clk = {
 309         .name = "timer1",
 310         .parent = &pll1_aux_clk,
 311         .lpsc = DAVINCI_LPSC_TIMER1,
 312 };
 313
 314 static struct clk timer2_clk = {
 315         .name = "timer2",
 316         .parent = &pll1_aux_clk,
 317         .lpsc = DAVINCI_LPSC_TIMER2,
 318         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 319 };
 320
 321 static struct clk timer3_clk = {
 322         .name = "timer3",
 323         .parent = &pll1_aux_clk,
 324         .lpsc = DM355_LPSC_TIMER3,
 325 };
 326
 327 static struct clk rto_clk = {
 328         .name = "rto",
 329         .parent = &pll1_aux_clk,
 330         .lpsc = DM355_LPSC_RTO,
 331 };
 332
 333 static struct clk usb_clk = {
 334         .name = "usb",
 335         .parent = &pll1_sysclk2,
 336         .lpsc = DAVINCI_LPSC_USB,
 337 };
 338
 339 static struct clk_lookup dm355_clks[] = {
 340         CLK(NULL, "ref", &ref_clk),
 341         CLK(NULL, "pll1", &pll1_clk),
 342         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 343         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 344         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 345         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 346         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 347         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 348         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 349         CLK(NULL, "vpss_master", &vpss_master_clk),
 350         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 351         CLK(NULL, "clkout1", &clkout1_clk),
 352         CLK(NULL, "clkout2", &clkout2_clk),
 353         CLK(NULL, "pll2", &pll2_clk),
 354         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 355         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 356         CLK(NULL, "clkout3", &clkout3_clk),
 357         CLK(NULL, "arm", &arm_clk),
 358         CLK(NULL, "mjcp", &mjcp_clk),
 359         CLK(NULL, "uart0", &uart0_clk),
 360         CLK(NULL, "uart1", &uart1_clk),
 361         CLK(NULL, "uart2", &uart2_clk),
 362         CLK("i2c_davinci.1", NULL, &i2c_clk),
 363         CLK("davinci-asp.0", NULL, &asp0_clk),
 364         CLK("davinci-asp.1", NULL, &asp1_clk),
 365         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
 366         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
 367         CLK("spi_davinci.0", NULL, &spi0_clk),
 368         CLK("spi_davinci.1", NULL, &spi1_clk),
 369         CLK("spi_davinci.2", NULL, &spi2_clk),
 370         CLK(NULL, "gpio", &gpio_clk),
 371         CLK(NULL, "aemif", &aemif_clk),
 372         CLK(NULL, "pwm0", &pwm0_clk),
 373         CLK(NULL, "pwm1", &pwm1_clk),
 374         CLK(NULL, "pwm2", &pwm2_clk),
 375         CLK(NULL, "pwm3", &pwm3_clk),
 376         CLK(NULL, "timer0", &timer0_clk),
 377         CLK(NULL, "timer1", &timer1_clk),
 378         CLK("watchdog", NULL, &timer2_clk),
 379         CLK(NULL, "timer3", &timer3_clk),
 380         CLK(NULL, "rto", &rto_clk),
 381         CLK(NULL, "usb", &usb_clk),
 382         CLK(NULL, NULL, NULL),
 383 };
 384
 385 /*----------------------------------------------------------------------*/
 386
 387 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
 388
 389 static struct resource dm355_spi0_resources[] = {
 390         {
 391                 .start = 0x01c66000,
 392                 .end   = 0x01c667ff,
 393                 .flags = IORESOURCE_MEM,
 394         },
 395         {
 396                 .start = IRQ_DM355_SPINT0_0,
 397                 .flags = IORESOURCE_IRQ,
 398         },
 399         {
 400                 .start = 17,
 401                 .flags = IORESOURCE_DMA,
 402         },
 403         {
 404                 .start = 16,
 405                 .flags = IORESOURCE_DMA,
 406         },
 407         {
 408                 .start = EVENTQ_1,
 409                 .flags = IORESOURCE_DMA,
 410         },
 411 };
 412
 413 static struct davinci_spi_platform_data dm355_spi0_pdata = {
 414         .version        = SPI_VERSION_1,
 415         .num_chipselect = 2,
 416         .clk_internal   = 1,
 417         .cs_hold        = 1,
 418         .intr_level     = 0,
 419         .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
 420         .c2tdelay       = 0,
 421         .t2cdelay       = 0,
 422 };
 423 static struct platform_device dm355_spi0_device = {
 424         .name = "spi_davinci",
 425         .id = 0,
 426         .dev = {
 427                 .dma_mask = &dm355_spi0_dma_mask,
 428                 .coherent_dma_mask = DMA_BIT_MASK(32),
 429                 .platform_data = &dm355_spi0_pdata,
 430         },
 431         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
 432         .resource = dm355_spi0_resources,
 433 };
 434
 435 void __init dm355_init_spi0(unsigned chipselect_mask,
 436                 struct spi_board_info *info, unsigned len)
 437 {
 438         /* for now, assume we need MISO */
 439         davinci_cfg_reg(DM355_SPI0_SDI);
 440
 441         /* not all slaves will be wired up */
 442         if (chipselect_mask & BIT(0))
 443                 davinci_cfg_reg(DM355_SPI0_SDENA0);
 444         if (chipselect_mask & BIT(1))
 445                 davinci_cfg_reg(DM355_SPI0_SDENA1);
 446
 447         spi_register_board_info(info, len);
 448
 449         platform_device_register(&dm355_spi0_device);
 450 }
 451
 452 /*----------------------------------------------------------------------*/
 453
 454 #define PINMUX0         0x00
 455 #define PINMUX1         0x04
 456 #define PINMUX2         0x08
 457 #define PINMUX3         0x0c
 458 #define PINMUX4         0x10
 459 #define INTMUX          0x18
 460 #define EVTMUX          0x1c
 461
 462 /*
 463  * Device specific mux setup
 464  *
 465  *      soc     description     mux  mode   mode  mux    dbg
 466  *                              reg  offset mask  mode
 467  */
 468 static const struct mux_config dm355_pins[] = {
 469 #ifdef CONFIG_DAVINCI_MUX
 470 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 471
 472 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 473 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 474 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 475 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 476 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 477 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 478
 479 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 480 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 481
 482 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 483 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 484 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 485 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 486 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 487 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 488
 489 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 490 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 491 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 492
 493 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 494 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 495 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 496
 497 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 498 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 499 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 500
 501 MUX_CFG(DM355,  VOUT_FIELD,     1,   18,    3,    1,     false)
 502 MUX_CFG(DM355,  VOUT_FIELD_G70, 1,   18,    3,    0,     false)
 503 MUX_CFG(DM355,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 504 MUX_CFG(DM355,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 505 MUX_CFG(DM355,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 506
 507 MUX_CFG(DM355,  VIN_PCLK,       0,   14,    1,    1,     false)
 508 MUX_CFG(DM355,  VIN_CAM_WEN,    0,   13,    1,    1,     false)
 509 MUX_CFG(DM355,  VIN_CAM_VD,     0,   12,    1,    1,     false)
 510 MUX_CFG(DM355,  VIN_CAM_HD,     0,   11,    1,    1,     false)
 511 MUX_CFG(DM355,  VIN_YIN_EN,     0,   10,    1,    1,     false)
 512 MUX_CFG(DM355,  VIN_CINL_EN,    0,   0,   0xff, 0x55,    false)
 513 MUX_CFG(DM355,  VIN_CINH_EN,    0,   8,     3,    3,     false)
 514 #endif
 515 };
 516
 517 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 518         [IRQ_DM355_CCDC_VDINT0]         = 2,
 519         [IRQ_DM355_CCDC_VDINT1]         = 6,
 520         [IRQ_DM355_CCDC_VDINT2]         = 6,
 521         [IRQ_DM355_IPIPE_HST]           = 6,
 522         [IRQ_DM355_H3AINT]              = 6,
 523         [IRQ_DM355_IPIPE_SDR]           = 6,
 524         [IRQ_DM355_IPIPEIFINT]          = 6,
 525         [IRQ_DM355_OSDINT]              = 7,
 526         [IRQ_DM355_VENCINT]             = 6,
 527         [IRQ_ASQINT]                    = 6,
 528         [IRQ_IMXINT]                    = 6,
 529         [IRQ_USBINT]                    = 4,
 530         [IRQ_DM355_RTOINT]              = 4,
 531         [IRQ_DM355_UARTINT2]            = 7,
 532         [IRQ_DM355_TINT6]               = 7,
 533         [IRQ_CCINT0]                    = 5,    /* dma */
 534         [IRQ_CCERRINT]                  = 5,    /* dma */
 535         [IRQ_TCERRINT0]                 = 5,    /* dma */
 536         [IRQ_TCERRINT]                  = 5,    /* dma */
 537         [IRQ_DM355_SPINT2_1]            = 7,
 538         [IRQ_DM355_TINT7]               = 4,
 539         [IRQ_DM355_SDIOINT0]            = 7,
 540         [IRQ_MBXINT]                    = 7,
 541         [IRQ_MBRINT]                    = 7,
 542         [IRQ_MMCINT]                    = 7,
 543         [IRQ_DM355_MMCINT1]             = 7,
 544         [IRQ_DM355_PWMINT3]             = 7,
 545         [IRQ_DDRINT]                    = 7,
 546         [IRQ_AEMIFINT]                  = 7,
 547         [IRQ_DM355_SDIOINT1]            = 4,
 548         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 549         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 550         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 551         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 552         [IRQ_PWMINT0]                   = 7,
 553         [IRQ_PWMINT1]                   = 7,
 554         [IRQ_PWMINT2]                   = 7,
 555         [IRQ_I2C]                       = 3,
 556         [IRQ_UARTINT0]                  = 3,
 557         [IRQ_UARTINT1]                  = 3,
 558         [IRQ_DM355_SPINT0_0]            = 3,
 559         [IRQ_DM355_SPINT0_1]            = 3,
 560         [IRQ_DM355_GPIO0]               = 3,
 561         [IRQ_DM355_GPIO1]               = 7,
 562         [IRQ_DM355_GPIO2]               = 4,
 563         [IRQ_DM355_GPIO3]               = 4,
 564         [IRQ_DM355_GPIO4]               = 7,
 565         [IRQ_DM355_GPIO5]               = 7,
 566         [IRQ_DM355_GPIO6]               = 7,
 567         [IRQ_DM355_GPIO7]               = 7,
 568         [IRQ_DM355_GPIO8]               = 7,
 569         [IRQ_DM355_GPIO9]               = 7,
 570         [IRQ_DM355_GPIOBNK0]            = 7,
 571         [IRQ_DM355_GPIOBNK1]            = 7,
 572         [IRQ_DM355_GPIOBNK2]            = 7,
 573         [IRQ_DM355_GPIOBNK3]            = 7,
 574         [IRQ_DM355_GPIOBNK4]            = 7,
 575         [IRQ_DM355_GPIOBNK5]            = 7,
 576         [IRQ_DM355_GPIOBNK6]            = 7,
 577         [IRQ_COMMTX]                    = 7,
 578         [IRQ_COMMRX]                    = 7,
 579         [IRQ_EMUINT]                    = 7,
 580 };
 581
 582 /*----------------------------------------------------------------------*/
 583
 584 static const s8
 585 queue_tc_mapping[][2] = {
 586         /* {event queue no, TC no} */
 587         {0, 0},
 588         {1, 1},
 589         {-1, -1},
 590 };
 591
 592 static const s8
 593 queue_priority_mapping[][2] = {
 594         /* {event queue no, Priority} */
 595         {0, 3},
 596         {1, 7},
 597         {-1, -1},
 598 };
 599
 600 static struct edma_soc_info dm355_edma_info[] = {
 601         {
 602                 .n_channel              = 64,
 603                 .n_region               = 4,
 604                 .n_slot                 = 128,
 605                 .n_tc                   = 2,
 606                 .n_cc                   = 1,
 607                 .queue_tc_mapping       = queue_tc_mapping,
 608                 .queue_priority_mapping = queue_priority_mapping,
 609         },
 610 };
 611
 612 static struct resource edma_resources[] = {
 613         {
 614                 .name   = "edma_cc0",
 615                 .start  = 0x01c00000,
 616                 .end    = 0x01c00000 + SZ_64K - 1,
 617                 .flags  = IORESOURCE_MEM,
 618         },
 619         {
 620                 .name   = "edma_tc0",
 621                 .start  = 0x01c10000,
 622                 .end    = 0x01c10000 + SZ_1K - 1,
 623                 .flags  = IORESOURCE_MEM,
 624         },
 625         {
 626                 .name   = "edma_tc1",
 627                 .start  = 0x01c10400,
 628                 .end    = 0x01c10400 + SZ_1K - 1,
 629                 .flags  = IORESOURCE_MEM,
 630         },
 631         {
 632                 .name   = "edma0",
 633                 .start  = IRQ_CCINT0,
 634                 .flags  = IORESOURCE_IRQ,
 635         },
 636         {
 637                 .name   = "edma0_err",
 638                 .start  = IRQ_CCERRINT,
 639                 .flags  = IORESOURCE_IRQ,
 640         },
 641         /* not using (or muxing) TC*_ERR */
 642 };
 643
 644 static struct platform_device dm355_edma_device = {
 645         .name                   = "edma",
 646         .id                     = 0,
 647         .dev.platform_data      = dm355_edma_info,
 648         .num_resources          = ARRAY_SIZE(edma_resources),
 649         .resource               = edma_resources,
 650 };
 651
 652 static struct resource dm355_asp1_resources[] = {
 653         {
 654                 .start  = DAVINCI_ASP1_BASE,
 655                 .end    = DAVINCI_ASP1_BASE + SZ_8K - 1,
 656                 .flags  = IORESOURCE_MEM,
 657         },
 658         {
 659                 .start  = DAVINCI_DMA_ASP1_TX,
 660                 .end    = DAVINCI_DMA_ASP1_TX,
 661                 .flags  = IORESOURCE_DMA,
 662         },
 663         {
 664                 .start  = DAVINCI_DMA_ASP1_RX,
 665                 .end    = DAVINCI_DMA_ASP1_RX,
 666                 .flags  = IORESOURCE_DMA,
 667         },
 668 };
 669
 670 static struct platform_device dm355_asp1_device = {
 671         .name           = "davinci-asp",
 672         .id             = 1,
 673         .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
 674         .resource       = dm355_asp1_resources,
 675 };
 676
 677 static struct resource dm355_vpss_resources[] = {
 678         {
 679                 /* VPSS BL Base address */
 680                 .name           = "vpss",
 681                 .start          = 0x01c70800,
 682                 .end            = 0x01c70800 + 0xff,
 683                 .flags          = IORESOURCE_MEM,
 684         },
 685         {
 686                 /* VPSS CLK Base address */
 687                 .name           = "vpss",
 688                 .start          = 0x01c70000,
 689                 .end            = 0x01c70000 + 0xf,
 690                 .flags          = IORESOURCE_MEM,
 691         },
 692 };
 693
 694 static struct platform_device dm355_vpss_device = {
 695         .name                   = "vpss",
 696         .id                     = -1,
 697         .dev.platform_data      = "dm355_vpss",
 698         .num_resources          = ARRAY_SIZE(dm355_vpss_resources),
 699         .resource               = dm355_vpss_resources,
 700 };
 701
 702 static struct resource vpfe_resources[] = {
 703         {
 704                 .start          = IRQ_VDINT0,
 705                 .end            = IRQ_VDINT0,
 706                 .flags          = IORESOURCE_IRQ,
 707         },
 708         {
 709                 .start          = IRQ_VDINT1,
 710                 .end            = IRQ_VDINT1,
 711                 .flags          = IORESOURCE_IRQ,
 712         },
 713         /* CCDC Base address */
 714         {
 715                 .flags          = IORESOURCE_MEM,
 716                 .start          = 0x01c70600,
 717                 .end            = 0x01c70600 + 0x1ff,
 718         },
 719 };
 720
 721 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 722 static struct platform_device vpfe_capture_dev = {
 723         .name           = CAPTURE_DRV_NAME,
 724         .id             = -1,
 725         .num_resources  = ARRAY_SIZE(vpfe_resources),
 726         .resource       = vpfe_resources,
 727         .dev = {
 728                 .dma_mask               = &vpfe_capture_dma_mask,
 729                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 730         },
 731 };
 732
 733 void dm355_set_vpfe_config(struct vpfe_config *cfg)
 734 {
 735         vpfe_capture_dev.dev.platform_data = cfg;
 736 }
 737
 738 /*----------------------------------------------------------------------*/
 739
 740 static struct map_desc dm355_io_desc[] = {
 741         {
 742                 .virtual        = IO_VIRT,
 743                 .pfn            = __phys_to_pfn(IO_PHYS),
 744                 .length         = IO_SIZE,
 745                 .type           = MT_DEVICE
 746         },
 747         {
 748                 .virtual        = SRAM_VIRT,
 749                 .pfn            = __phys_to_pfn(0x00010000),
 750                 .length         = SZ_32K,
 751                 /* MT_MEMORY_NONCACHED requires supersection alignment */
 752                 .type           = MT_DEVICE,
 753         },
 754 };
 755
 756 /* Contents of JTAG ID register used to identify exact cpu type */
 757 static struct davinci_id dm355_ids[] = {
 758         {
 759                 .variant        = 0x0,
 760                 .part_no        = 0xb73b,
 761                 .manufacturer   = 0x00f,
 762                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 763                 .name           = "dm355",
 764         },
 765 };
 766
 767 static void __iomem *dm355_psc_bases[] = {
 768         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 769 };
 770
 771 /*
 772  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 773  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 774  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 775  * T1_TOP: Timer 1, top   :  <unused>
 776  */
 777 struct davinci_timer_info dm355_timer_info = {
 778         .timers         = davinci_timer_instance,
 779         .clockevent_id  = T0_BOT,
 780         .clocksource_id = T0_TOP,
 781 };
 782
 783 static struct plat_serial8250_port dm355_serial_platform_data[] = {
 784         {
 785                 .mapbase        = DAVINCI_UART0_BASE,
 786                 .irq            = IRQ_UARTINT0,
 787                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 788                                   UPF_IOREMAP,
 789                 .iotype         = UPIO_MEM,
 790                 .regshift       = 2,
 791         },
 792         {
 793                 .mapbase        = DAVINCI_UART1_BASE,
 794                 .irq            = IRQ_UARTINT1,
 795                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 796                                   UPF_IOREMAP,
 797                 .iotype         = UPIO_MEM,
 798                 .regshift       = 2,
 799         },
 800         {
 801                 .mapbase        = DM355_UART2_BASE,
 802                 .irq            = IRQ_DM355_UARTINT2,
 803                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 804                                   UPF_IOREMAP,
 805                 .iotype         = UPIO_MEM,
 806                 .regshift       = 2,
 807         },
 808         {
 809                 .flags          = 0
 810         },
 811 };
 812
 813 static struct platform_device dm355_serial_device = {
 814         .name                   = "serial8250",
 815         .id                     = PLAT8250_DEV_PLATFORM,
 816         .dev                    = {
 817                 .platform_data  = dm355_serial_platform_data,
 818         },
 819 };
 820
 821 static struct davinci_soc_info davinci_soc_info_dm355 = {
 822         .io_desc                = dm355_io_desc,
 823         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
 824         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 825         .ids                    = dm355_ids,
 826         .ids_num                = ARRAY_SIZE(dm355_ids),
 827         .cpu_clks               = dm355_clks,
 828         .psc_bases              = dm355_psc_bases,
 829         .psc_bases_num          = ARRAY_SIZE(dm355_psc_bases),
 830         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 831         .pinmux_pins            = dm355_pins,
 832         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
 833         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 834         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 835         .intc_irq_prios         = dm355_default_priorities,
 836         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 837         .timer_info             = &dm355_timer_info,
 838         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
 839         .gpio_num               = 104,
 840         .gpio_irq               = IRQ_DM355_GPIOBNK0,
 841         .serial_dev             = &dm355_serial_device,
 842         .sram_dma               = 0x00010000,
 843         .sram_len               = SZ_32K,
 844 };
 845
 846 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
 847 {
 848         /* we don't use ASP1 IRQs, or we'd need to mux them ... */
 849         if (evt_enable & ASP1_TX_EVT_EN)
 850                 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
 851
 852         if (evt_enable & ASP1_RX_EVT_EN)
 853                 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
 854
 855         dm355_asp1_device.dev.platform_data = pdata;
 856         platform_device_register(&dm355_asp1_device);
 857 }
 858
 859 void __init dm355_init(void)
 860 {
 861         davinci_common_init(&davinci_soc_info_dm355);
 862 }
 863
 864 static int __init dm355_init_devices(void)
 865 {
 866         if (!cpu_is_davinci_dm355())
 867                 return 0;
 868
 869         davinci_cfg_reg(DM355_INT_EDMA_CC);
 870         platform_device_register(&dm355_edma_device);
 871         platform_device_register(&dm355_vpss_device);
 872         /*
 873          * setup Mux configuration for vpfe input and register
 874          * vpfe capture platform device
 875          */
 876         davinci_cfg_reg(DM355_VIN_PCLK);
 877         davinci_cfg_reg(DM355_VIN_CAM_WEN);
 878         davinci_cfg_reg(DM355_VIN_CAM_VD);
 879         davinci_cfg_reg(DM355_VIN_CAM_HD);
 880         davinci_cfg_reg(DM355_VIN_YIN_EN);
 881         davinci_cfg_reg(DM355_VIN_CINL_EN);
 882         davinci_cfg_reg(DM355_VIN_CINH_EN);
 883         platform_device_register(&vpfe_capture_dev);
 884
 885         return 0;
 886 }
 887 postcore_initcall(dm355_init_devices);