2 * TI DaVinci DM365 chip specific setup
4 * Copyright (C) 2009 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/serial_8250.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
22 #include <asm/mach/map.h>
24 #include <mach/cputype.h>
25 #include <mach/edma.h>
28 #include <mach/irqs.h>
29 #include <mach/time.h>
30 #include <mach/serial.h>
31 #include <mach/common.h>
32 #include <linux/platform_data/keyscan-davinci.h>
33 #include <linux/platform_data/spi-davinci.h>
34 #include <mach/gpio-davinci.h>
41 #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
43 /* Base of key scan register bank */
44 #define DM365_KEYSCAN_BASE 0x01c69400
46 #define DM365_RTC_BASE 0x01c69000
48 #define DAVINCI_DM365_VC_BASE 0x01d0c000
49 #define DAVINCI_DMA_VC_TX 2
50 #define DAVINCI_DMA_VC_RX 3
52 #define DM365_EMAC_BASE 0x01d07000
53 #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
54 #define DM365_EMAC_CNTRL_OFFSET 0x0000
55 #define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
56 #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
57 #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
59 static struct pll_data pll1_data
= {
61 .phys_base
= DAVINCI_PLL1_BASE
,
62 .flags
= PLL_HAS_POSTDIV
| PLL_HAS_PREDIV
,
65 static struct pll_data pll2_data
= {
67 .phys_base
= DAVINCI_PLL2_BASE
,
68 .flags
= PLL_HAS_POSTDIV
| PLL_HAS_PREDIV
,
71 static struct clk ref_clk
= {
73 .rate
= DM365_REF_FREQ
,
76 static struct clk pll1_clk
= {
80 .pll_data
= &pll1_data
,
83 static struct clk pll1_aux_clk
= {
84 .name
= "pll1_aux_clk",
86 .flags
= CLK_PLL
| PRE_PLL
,
89 static struct clk pll1_sysclkbp
= {
90 .name
= "pll1_sysclkbp",
92 .flags
= CLK_PLL
| PRE_PLL
,
96 static struct clk clkout0_clk
= {
99 .flags
= CLK_PLL
| PRE_PLL
,
102 static struct clk pll1_sysclk1
= {
103 .name
= "pll1_sysclk1",
109 static struct clk pll1_sysclk2
= {
110 .name
= "pll1_sysclk2",
116 static struct clk pll1_sysclk3
= {
117 .name
= "pll1_sysclk3",
123 static struct clk pll1_sysclk4
= {
124 .name
= "pll1_sysclk4",
130 static struct clk pll1_sysclk5
= {
131 .name
= "pll1_sysclk5",
137 static struct clk pll1_sysclk6
= {
138 .name
= "pll1_sysclk6",
144 static struct clk pll1_sysclk7
= {
145 .name
= "pll1_sysclk7",
151 static struct clk pll1_sysclk8
= {
152 .name
= "pll1_sysclk8",
158 static struct clk pll1_sysclk9
= {
159 .name
= "pll1_sysclk9",
165 static struct clk pll2_clk
= {
169 .pll_data
= &pll2_data
,
172 static struct clk pll2_aux_clk
= {
173 .name
= "pll2_aux_clk",
175 .flags
= CLK_PLL
| PRE_PLL
,
178 static struct clk clkout1_clk
= {
181 .flags
= CLK_PLL
| PRE_PLL
,
184 static struct clk pll2_sysclk1
= {
185 .name
= "pll2_sysclk1",
191 static struct clk pll2_sysclk2
= {
192 .name
= "pll2_sysclk2",
198 static struct clk pll2_sysclk3
= {
199 .name
= "pll2_sysclk3",
205 static struct clk pll2_sysclk4
= {
206 .name
= "pll2_sysclk4",
212 static struct clk pll2_sysclk5
= {
213 .name
= "pll2_sysclk5",
219 static struct clk pll2_sysclk6
= {
220 .name
= "pll2_sysclk6",
226 static struct clk pll2_sysclk7
= {
227 .name
= "pll2_sysclk7",
233 static struct clk pll2_sysclk8
= {
234 .name
= "pll2_sysclk8",
240 static struct clk pll2_sysclk9
= {
241 .name
= "pll2_sysclk9",
247 static struct clk vpss_dac_clk
= {
249 .parent
= &pll1_sysclk3
,
250 .lpsc
= DM365_LPSC_DAC_CLK
,
253 static struct clk vpss_master_clk
= {
254 .name
= "vpss_master",
255 .parent
= &pll1_sysclk5
,
256 .lpsc
= DM365_LPSC_VPSSMSTR
,
260 static struct clk arm_clk
= {
262 .parent
= &pll2_sysclk2
,
263 .lpsc
= DAVINCI_LPSC_ARM
,
264 .flags
= ALWAYS_ENABLED
,
267 static struct clk uart0_clk
= {
269 .parent
= &pll1_aux_clk
,
270 .lpsc
= DAVINCI_LPSC_UART0
,
273 static struct clk uart1_clk
= {
275 .parent
= &pll1_sysclk4
,
276 .lpsc
= DAVINCI_LPSC_UART1
,
279 static struct clk i2c_clk
= {
281 .parent
= &pll1_aux_clk
,
282 .lpsc
= DAVINCI_LPSC_I2C
,
285 static struct clk mmcsd0_clk
= {
287 .parent
= &pll1_sysclk8
,
288 .lpsc
= DAVINCI_LPSC_MMC_SD
,
291 static struct clk mmcsd1_clk
= {
293 .parent
= &pll1_sysclk4
,
294 .lpsc
= DM365_LPSC_MMC_SD1
,
297 static struct clk spi0_clk
= {
299 .parent
= &pll1_sysclk4
,
300 .lpsc
= DAVINCI_LPSC_SPI
,
303 static struct clk spi1_clk
= {
305 .parent
= &pll1_sysclk4
,
306 .lpsc
= DM365_LPSC_SPI1
,
309 static struct clk spi2_clk
= {
311 .parent
= &pll1_sysclk4
,
312 .lpsc
= DM365_LPSC_SPI2
,
315 static struct clk spi3_clk
= {
317 .parent
= &pll1_sysclk4
,
318 .lpsc
= DM365_LPSC_SPI3
,
321 static struct clk spi4_clk
= {
323 .parent
= &pll1_aux_clk
,
324 .lpsc
= DM365_LPSC_SPI4
,
327 static struct clk gpio_clk
= {
329 .parent
= &pll1_sysclk4
,
330 .lpsc
= DAVINCI_LPSC_GPIO
,
333 static struct clk aemif_clk
= {
335 .parent
= &pll1_sysclk4
,
336 .lpsc
= DAVINCI_LPSC_AEMIF
,
339 static struct clk pwm0_clk
= {
341 .parent
= &pll1_aux_clk
,
342 .lpsc
= DAVINCI_LPSC_PWM0
,
345 static struct clk pwm1_clk
= {
347 .parent
= &pll1_aux_clk
,
348 .lpsc
= DAVINCI_LPSC_PWM1
,
351 static struct clk pwm2_clk
= {
353 .parent
= &pll1_aux_clk
,
354 .lpsc
= DAVINCI_LPSC_PWM2
,
357 static struct clk pwm3_clk
= {
360 .lpsc
= DM365_LPSC_PWM3
,
363 static struct clk timer0_clk
= {
365 .parent
= &pll1_aux_clk
,
366 .lpsc
= DAVINCI_LPSC_TIMER0
,
369 static struct clk timer1_clk
= {
371 .parent
= &pll1_aux_clk
,
372 .lpsc
= DAVINCI_LPSC_TIMER1
,
375 static struct clk timer2_clk
= {
377 .parent
= &pll1_aux_clk
,
378 .lpsc
= DAVINCI_LPSC_TIMER2
,
382 static struct clk timer3_clk
= {
384 .parent
= &pll1_aux_clk
,
385 .lpsc
= DM365_LPSC_TIMER3
,
388 static struct clk usb_clk
= {
390 .parent
= &pll1_aux_clk
,
391 .lpsc
= DAVINCI_LPSC_USB
,
394 static struct clk emac_clk
= {
396 .parent
= &pll1_sysclk4
,
397 .lpsc
= DM365_LPSC_EMAC
,
400 static struct clk voicecodec_clk
= {
401 .name
= "voice_codec",
402 .parent
= &pll2_sysclk4
,
403 .lpsc
= DM365_LPSC_VOICE_CODEC
,
406 static struct clk asp0_clk
= {
408 .parent
= &pll1_sysclk4
,
409 .lpsc
= DM365_LPSC_McBSP1
,
412 static struct clk rto_clk
= {
414 .parent
= &pll1_sysclk4
,
415 .lpsc
= DM365_LPSC_RTO
,
418 static struct clk mjcp_clk
= {
420 .parent
= &pll1_sysclk3
,
421 .lpsc
= DM365_LPSC_MJCP
,
424 static struct clk_lookup dm365_clks
[] = {
425 CLK(NULL
, "ref", &ref_clk
),
426 CLK(NULL
, "pll1", &pll1_clk
),
427 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
428 CLK(NULL
, "pll1_sysclkbp", &pll1_sysclkbp
),
429 CLK(NULL
, "clkout0", &clkout0_clk
),
430 CLK(NULL
, "pll1_sysclk1", &pll1_sysclk1
),
431 CLK(NULL
, "pll1_sysclk2", &pll1_sysclk2
),
432 CLK(NULL
, "pll1_sysclk3", &pll1_sysclk3
),
433 CLK(NULL
, "pll1_sysclk4", &pll1_sysclk4
),
434 CLK(NULL
, "pll1_sysclk5", &pll1_sysclk5
),
435 CLK(NULL
, "pll1_sysclk6", &pll1_sysclk6
),
436 CLK(NULL
, "pll1_sysclk7", &pll1_sysclk7
),
437 CLK(NULL
, "pll1_sysclk8", &pll1_sysclk8
),
438 CLK(NULL
, "pll1_sysclk9", &pll1_sysclk9
),
439 CLK(NULL
, "pll2", &pll2_clk
),
440 CLK(NULL
, "pll2_aux", &pll2_aux_clk
),
441 CLK(NULL
, "clkout1", &clkout1_clk
),
442 CLK(NULL
, "pll2_sysclk1", &pll2_sysclk1
),
443 CLK(NULL
, "pll2_sysclk2", &pll2_sysclk2
),
444 CLK(NULL
, "pll2_sysclk3", &pll2_sysclk3
),
445 CLK(NULL
, "pll2_sysclk4", &pll2_sysclk4
),
446 CLK(NULL
, "pll2_sysclk5", &pll2_sysclk5
),
447 CLK(NULL
, "pll2_sysclk6", &pll2_sysclk6
),
448 CLK(NULL
, "pll2_sysclk7", &pll2_sysclk7
),
449 CLK(NULL
, "pll2_sysclk8", &pll2_sysclk8
),
450 CLK(NULL
, "pll2_sysclk9", &pll2_sysclk9
),
451 CLK(NULL
, "vpss_dac", &vpss_dac_clk
),
452 CLK(NULL
, "vpss_master", &vpss_master_clk
),
453 CLK(NULL
, "arm", &arm_clk
),
454 CLK(NULL
, "uart0", &uart0_clk
),
455 CLK(NULL
, "uart1", &uart1_clk
),
456 CLK("i2c_davinci.1", NULL
, &i2c_clk
),
457 CLK("davinci_mmc.0", NULL
, &mmcsd0_clk
),
458 CLK("davinci_mmc.1", NULL
, &mmcsd1_clk
),
459 CLK("spi_davinci.0", NULL
, &spi0_clk
),
460 CLK("spi_davinci.1", NULL
, &spi1_clk
),
461 CLK("spi_davinci.2", NULL
, &spi2_clk
),
462 CLK("spi_davinci.3", NULL
, &spi3_clk
),
463 CLK("spi_davinci.4", NULL
, &spi4_clk
),
464 CLK(NULL
, "gpio", &gpio_clk
),
465 CLK(NULL
, "aemif", &aemif_clk
),
466 CLK(NULL
, "pwm0", &pwm0_clk
),
467 CLK(NULL
, "pwm1", &pwm1_clk
),
468 CLK(NULL
, "pwm2", &pwm2_clk
),
469 CLK(NULL
, "pwm3", &pwm3_clk
),
470 CLK(NULL
, "timer0", &timer0_clk
),
471 CLK(NULL
, "timer1", &timer1_clk
),
472 CLK("watchdog", NULL
, &timer2_clk
),
473 CLK(NULL
, "timer3", &timer3_clk
),
474 CLK(NULL
, "usb", &usb_clk
),
475 CLK("davinci_emac.1", NULL
, &emac_clk
),
476 CLK("davinci_voicecodec", NULL
, &voicecodec_clk
),
477 CLK("davinci-mcbsp", NULL
, &asp0_clk
),
478 CLK(NULL
, "rto", &rto_clk
),
479 CLK(NULL
, "mjcp", &mjcp_clk
),
480 CLK(NULL
, NULL
, NULL
),
483 /*----------------------------------------------------------------------*/
489 static const struct mux_config dm365_pins
[] = {
490 #ifdef CONFIG_DAVINCI_MUX
491 MUX_CFG(DM365
, MMCSD0
, 0, 24, 1, 0, false)
493 MUX_CFG(DM365
, SD1_CLK
, 0, 16, 3, 1, false)
494 MUX_CFG(DM365
, SD1_CMD
, 4, 30, 3, 1, false)
495 MUX_CFG(DM365
, SD1_DATA3
, 4, 28, 3, 1, false)
496 MUX_CFG(DM365
, SD1_DATA2
, 4, 26, 3, 1, false)
497 MUX_CFG(DM365
, SD1_DATA1
, 4, 24, 3, 1, false)
498 MUX_CFG(DM365
, SD1_DATA0
, 4, 22, 3, 1, false)
500 MUX_CFG(DM365
, I2C_SDA
, 3, 23, 3, 2, false)
501 MUX_CFG(DM365
, I2C_SCL
, 3, 21, 3, 2, false)
503 MUX_CFG(DM365
, AEMIF_AR_A14
, 2, 0, 3, 1, false)
504 MUX_CFG(DM365
, AEMIF_AR_BA0
, 2, 0, 3, 2, false)
505 MUX_CFG(DM365
, AEMIF_A3
, 2, 2, 3, 1, false)
506 MUX_CFG(DM365
, AEMIF_A7
, 2, 4, 3, 1, false)
507 MUX_CFG(DM365
, AEMIF_D15_8
, 2, 6, 1, 1, false)
508 MUX_CFG(DM365
, AEMIF_CE0
, 2, 7, 1, 0, false)
509 MUX_CFG(DM365
, AEMIF_CE1
, 2, 8, 1, 0, false)
510 MUX_CFG(DM365
, AEMIF_WE_OE
, 2, 9, 1, 0, false)
512 MUX_CFG(DM365
, MCBSP0_BDX
, 0, 23, 1, 1, false)
513 MUX_CFG(DM365
, MCBSP0_X
, 0, 22, 1, 1, false)
514 MUX_CFG(DM365
, MCBSP0_BFSX
, 0, 21, 1, 1, false)
515 MUX_CFG(DM365
, MCBSP0_BDR
, 0, 20, 1, 1, false)
516 MUX_CFG(DM365
, MCBSP0_R
, 0, 19, 1, 1, false)
517 MUX_CFG(DM365
, MCBSP0_BFSR
, 0, 18, 1, 1, false)
519 MUX_CFG(DM365
, SPI0_SCLK
, 3, 28, 1, 1, false)
520 MUX_CFG(DM365
, SPI0_SDI
, 3, 26, 3, 1, false)
521 MUX_CFG(DM365
, SPI0_SDO
, 3, 25, 1, 1, false)
522 MUX_CFG(DM365
, SPI0_SDENA0
, 3, 29, 3, 1, false)
523 MUX_CFG(DM365
, SPI0_SDENA1
, 3, 26, 3, 2, false)
525 MUX_CFG(DM365
, UART0_RXD
, 3, 20, 1, 1, false)
526 MUX_CFG(DM365
, UART0_TXD
, 3, 19, 1, 1, false)
527 MUX_CFG(DM365
, UART1_RXD
, 3, 17, 3, 2, false)
528 MUX_CFG(DM365
, UART1_TXD
, 3, 15, 3, 2, false)
529 MUX_CFG(DM365
, UART1_RTS
, 3, 23, 3, 1, false)
530 MUX_CFG(DM365
, UART1_CTS
, 3, 21, 3, 1, false)
532 MUX_CFG(DM365
, EMAC_TX_EN
, 3, 17, 3, 1, false)
533 MUX_CFG(DM365
, EMAC_TX_CLK
, 3, 15, 3, 1, false)
534 MUX_CFG(DM365
, EMAC_COL
, 3, 14, 1, 1, false)
535 MUX_CFG(DM365
, EMAC_TXD3
, 3, 13, 1, 1, false)
536 MUX_CFG(DM365
, EMAC_TXD2
, 3, 12, 1, 1, false)
537 MUX_CFG(DM365
, EMAC_TXD1
, 3, 11, 1, 1, false)
538 MUX_CFG(DM365
, EMAC_TXD0
, 3, 10, 1, 1, false)
539 MUX_CFG(DM365
, EMAC_RXD3
, 3, 9, 1, 1, false)
540 MUX_CFG(DM365
, EMAC_RXD2
, 3, 8, 1, 1, false)
541 MUX_CFG(DM365
, EMAC_RXD1
, 3, 7, 1, 1, false)
542 MUX_CFG(DM365
, EMAC_RXD0
, 3, 6, 1, 1, false)
543 MUX_CFG(DM365
, EMAC_RX_CLK
, 3, 5, 1, 1, false)
544 MUX_CFG(DM365
, EMAC_RX_DV
, 3, 4, 1, 1, false)
545 MUX_CFG(DM365
, EMAC_RX_ER
, 3, 3, 1, 1, false)
546 MUX_CFG(DM365
, EMAC_CRS
, 3, 2, 1, 1, false)
547 MUX_CFG(DM365
, EMAC_MDIO
, 3, 1, 1, 1, false)
548 MUX_CFG(DM365
, EMAC_MDCLK
, 3, 0, 1, 1, false)
550 MUX_CFG(DM365
, KEYSCAN
, 2, 0, 0x3f, 0x3f, false)
552 MUX_CFG(DM365
, PWM0
, 1, 0, 3, 2, false)
553 MUX_CFG(DM365
, PWM0_G23
, 3, 26, 3, 3, false)
554 MUX_CFG(DM365
, PWM1
, 1, 2, 3, 2, false)
555 MUX_CFG(DM365
, PWM1_G25
, 3, 29, 3, 2, false)
556 MUX_CFG(DM365
, PWM2_G87
, 1, 10, 3, 2, false)
557 MUX_CFG(DM365
, PWM2_G88
, 1, 8, 3, 2, false)
558 MUX_CFG(DM365
, PWM2_G89
, 1, 6, 3, 2, false)
559 MUX_CFG(DM365
, PWM2_G90
, 1, 4, 3, 2, false)
560 MUX_CFG(DM365
, PWM3_G80
, 1, 20, 3, 3, false)
561 MUX_CFG(DM365
, PWM3_G81
, 1, 18, 3, 3, false)
562 MUX_CFG(DM365
, PWM3_G85
, 1, 14, 3, 2, false)
563 MUX_CFG(DM365
, PWM3_G86
, 1, 12, 3, 2, false)
565 MUX_CFG(DM365
, SPI1_SCLK
, 4, 2, 3, 1, false)
566 MUX_CFG(DM365
, SPI1_SDI
, 3, 31, 1, 1, false)
567 MUX_CFG(DM365
, SPI1_SDO
, 4, 0, 3, 1, false)
568 MUX_CFG(DM365
, SPI1_SDENA0
, 4, 4, 3, 1, false)
569 MUX_CFG(DM365
, SPI1_SDENA1
, 4, 0, 3, 2, false)
571 MUX_CFG(DM365
, SPI2_SCLK
, 4, 10, 3, 1, false)
572 MUX_CFG(DM365
, SPI2_SDI
, 4, 6, 3, 1, false)
573 MUX_CFG(DM365
, SPI2_SDO
, 4, 8, 3, 1, false)
574 MUX_CFG(DM365
, SPI2_SDENA0
, 4, 12, 3, 1, false)
575 MUX_CFG(DM365
, SPI2_SDENA1
, 4, 8, 3, 2, false)
577 MUX_CFG(DM365
, SPI3_SCLK
, 0, 0, 3, 2, false)
578 MUX_CFG(DM365
, SPI3_SDI
, 0, 2, 3, 2, false)
579 MUX_CFG(DM365
, SPI3_SDO
, 0, 6, 3, 2, false)
580 MUX_CFG(DM365
, SPI3_SDENA0
, 0, 4, 3, 2, false)
581 MUX_CFG(DM365
, SPI3_SDENA1
, 0, 6, 3, 3, false)
583 MUX_CFG(DM365
, SPI4_SCLK
, 4, 18, 3, 1, false)
584 MUX_CFG(DM365
, SPI4_SDI
, 4, 14, 3, 1, false)
585 MUX_CFG(DM365
, SPI4_SDO
, 4, 16, 3, 1, false)
586 MUX_CFG(DM365
, SPI4_SDENA0
, 4, 20, 3, 1, false)
587 MUX_CFG(DM365
, SPI4_SDENA1
, 4, 16, 3, 2, false)
589 MUX_CFG(DM365
, CLKOUT0
, 4, 20, 3, 3, false)
590 MUX_CFG(DM365
, CLKOUT1
, 4, 16, 3, 3, false)
591 MUX_CFG(DM365
, CLKOUT2
, 4, 8, 3, 3, false)
593 MUX_CFG(DM365
, GPIO20
, 3, 21, 3, 0, false)
594 MUX_CFG(DM365
, GPIO30
, 4, 6, 3, 0, false)
595 MUX_CFG(DM365
, GPIO31
, 4, 8, 3, 0, false)
596 MUX_CFG(DM365
, GPIO32
, 4, 10, 3, 0, false)
597 MUX_CFG(DM365
, GPIO33
, 4, 12, 3, 0, false)
598 MUX_CFG(DM365
, GPIO40
, 4, 26, 3, 0, false)
599 MUX_CFG(DM365
, GPIO64_57
, 2, 6, 1, 0, false)
601 MUX_CFG(DM365
, VOUT_FIELD
, 1, 18, 3, 1, false)
602 MUX_CFG(DM365
, VOUT_FIELD_G81
, 1, 18, 3, 0, false)
603 MUX_CFG(DM365
, VOUT_HVSYNC
, 1, 16, 1, 0, false)
604 MUX_CFG(DM365
, VOUT_COUTL_EN
, 1, 0, 0xff, 0x55, false)
605 MUX_CFG(DM365
, VOUT_COUTH_EN
, 1, 8, 0xff, 0x55, false)
606 MUX_CFG(DM365
, VIN_CAM_WEN
, 0, 14, 3, 0, false)
607 MUX_CFG(DM365
, VIN_CAM_VD
, 0, 13, 1, 0, false)
608 MUX_CFG(DM365
, VIN_CAM_HD
, 0, 12, 1, 0, false)
609 MUX_CFG(DM365
, VIN_YIN4_7_EN
, 0, 0, 0xff, 0, false)
610 MUX_CFG(DM365
, VIN_YIN0_3_EN
, 0, 8, 0xf, 0, false)
612 INT_CFG(DM365
, INT_EDMA_CC
, 2, 1, 1, false)
613 INT_CFG(DM365
, INT_EDMA_TC0_ERR
, 3, 1, 1, false)
614 INT_CFG(DM365
, INT_EDMA_TC1_ERR
, 4, 1, 1, false)
615 INT_CFG(DM365
, INT_EDMA_TC2_ERR
, 22, 1, 1, false)
616 INT_CFG(DM365
, INT_EDMA_TC3_ERR
, 23, 1, 1, false)
617 INT_CFG(DM365
, INT_PRTCSS
, 10, 1, 1, false)
618 INT_CFG(DM365
, INT_EMAC_RXTHRESH
, 14, 1, 1, false)
619 INT_CFG(DM365
, INT_EMAC_RXPULSE
, 15, 1, 1, false)
620 INT_CFG(DM365
, INT_EMAC_TXPULSE
, 16, 1, 1, false)
621 INT_CFG(DM365
, INT_EMAC_MISCPULSE
, 17, 1, 1, false)
622 INT_CFG(DM365
, INT_IMX0_ENABLE
, 0, 1, 0, false)
623 INT_CFG(DM365
, INT_IMX0_DISABLE
, 0, 1, 1, false)
624 INT_CFG(DM365
, INT_HDVICP_ENABLE
, 0, 1, 1, false)
625 INT_CFG(DM365
, INT_HDVICP_DISABLE
, 0, 1, 0, false)
626 INT_CFG(DM365
, INT_IMX1_ENABLE
, 24, 1, 1, false)
627 INT_CFG(DM365
, INT_IMX1_DISABLE
, 24, 1, 0, false)
628 INT_CFG(DM365
, INT_NSF_ENABLE
, 25, 1, 1, false)
629 INT_CFG(DM365
, INT_NSF_DISABLE
, 25, 1, 0, false)
631 EVT_CFG(DM365
, EVT2_ASP_TX
, 0, 1, 0, false)
632 EVT_CFG(DM365
, EVT3_ASP_RX
, 1, 1, 0, false)
633 EVT_CFG(DM365
, EVT2_VC_TX
, 0, 1, 1, false)
634 EVT_CFG(DM365
, EVT3_VC_RX
, 1, 1, 1, false)
638 static u64 dm365_spi0_dma_mask
= DMA_BIT_MASK(32);
640 static struct davinci_spi_platform_data dm365_spi0_pdata
= {
641 .version
= SPI_VERSION_1
,
643 .dma_event_q
= EVENTQ_3
,
646 static struct resource dm365_spi0_resources
[] = {
650 .flags
= IORESOURCE_MEM
,
653 .start
= IRQ_DM365_SPIINT0_0
,
654 .flags
= IORESOURCE_IRQ
,
658 .flags
= IORESOURCE_DMA
,
662 .flags
= IORESOURCE_DMA
,
666 static struct platform_device dm365_spi0_device
= {
667 .name
= "spi_davinci",
670 .dma_mask
= &dm365_spi0_dma_mask
,
671 .coherent_dma_mask
= DMA_BIT_MASK(32),
672 .platform_data
= &dm365_spi0_pdata
,
674 .num_resources
= ARRAY_SIZE(dm365_spi0_resources
),
675 .resource
= dm365_spi0_resources
,
678 void __init
dm365_init_spi0(unsigned chipselect_mask
,
679 const struct spi_board_info
*info
, unsigned len
)
681 davinci_cfg_reg(DM365_SPI0_SCLK
);
682 davinci_cfg_reg(DM365_SPI0_SDI
);
683 davinci_cfg_reg(DM365_SPI0_SDO
);
685 /* not all slaves will be wired up */
686 if (chipselect_mask
& BIT(0))
687 davinci_cfg_reg(DM365_SPI0_SDENA0
);
688 if (chipselect_mask
& BIT(1))
689 davinci_cfg_reg(DM365_SPI0_SDENA1
);
691 spi_register_board_info(info
, len
);
693 platform_device_register(&dm365_spi0_device
);
696 static struct emac_platform_data dm365_emac_pdata
= {
697 .ctrl_reg_offset
= DM365_EMAC_CNTRL_OFFSET
,
698 .ctrl_mod_reg_offset
= DM365_EMAC_CNTRL_MOD_OFFSET
,
699 .ctrl_ram_offset
= DM365_EMAC_CNTRL_RAM_OFFSET
,
700 .ctrl_ram_size
= DM365_EMAC_CNTRL_RAM_SIZE
,
701 .version
= EMAC_VERSION_2
,
704 static struct resource dm365_emac_resources
[] = {
706 .start
= DM365_EMAC_BASE
,
707 .end
= DM365_EMAC_BASE
+ SZ_16K
- 1,
708 .flags
= IORESOURCE_MEM
,
711 .start
= IRQ_DM365_EMAC_RXTHRESH
,
712 .end
= IRQ_DM365_EMAC_RXTHRESH
,
713 .flags
= IORESOURCE_IRQ
,
716 .start
= IRQ_DM365_EMAC_RXPULSE
,
717 .end
= IRQ_DM365_EMAC_RXPULSE
,
718 .flags
= IORESOURCE_IRQ
,
721 .start
= IRQ_DM365_EMAC_TXPULSE
,
722 .end
= IRQ_DM365_EMAC_TXPULSE
,
723 .flags
= IORESOURCE_IRQ
,
726 .start
= IRQ_DM365_EMAC_MISCPULSE
,
727 .end
= IRQ_DM365_EMAC_MISCPULSE
,
728 .flags
= IORESOURCE_IRQ
,
732 static struct platform_device dm365_emac_device
= {
733 .name
= "davinci_emac",
736 .platform_data
= &dm365_emac_pdata
,
738 .num_resources
= ARRAY_SIZE(dm365_emac_resources
),
739 .resource
= dm365_emac_resources
,
742 static struct resource dm365_mdio_resources
[] = {
744 .start
= DM365_EMAC_MDIO_BASE
,
745 .end
= DM365_EMAC_MDIO_BASE
+ SZ_4K
- 1,
746 .flags
= IORESOURCE_MEM
,
750 static struct platform_device dm365_mdio_device
= {
751 .name
= "davinci_mdio",
753 .num_resources
= ARRAY_SIZE(dm365_mdio_resources
),
754 .resource
= dm365_mdio_resources
,
757 static u8 dm365_default_priorities
[DAVINCI_N_AINTC_IRQ
] = {
765 [IRQ_DM365_INSFINT
] = 7,
769 [IRQ_DM365_IMCOPINT
] = 4,
771 [IRQ_DM365_RTOINT
] = 7,
772 [IRQ_DM365_TINT5
] = 7,
773 [IRQ_DM365_TINT6
] = 5,
779 [IRQ_DM365_SPINT2_1
] = 7,
780 [IRQ_DM365_TINT7
] = 7,
781 [IRQ_DM365_SDIOINT0
] = 7,
785 [IRQ_DM365_MMCINT1
] = 7,
786 [IRQ_DM365_PWMINT3
] = 7,
788 [IRQ_DM365_SDIOINT1
] = 2,
789 [IRQ_TINT0_TINT12
] = 7,
790 [IRQ_TINT0_TINT34
] = 7,
791 [IRQ_TINT1_TINT12
] = 7,
792 [IRQ_TINT1_TINT34
] = 7,
799 [IRQ_DM365_RTCINT
] = 3,
800 [IRQ_DM365_SPIINT0_0
] = 3,
801 [IRQ_DM365_SPIINT3_0
] = 3,
802 [IRQ_DM365_GPIO0
] = 3,
803 [IRQ_DM365_GPIO1
] = 7,
804 [IRQ_DM365_GPIO2
] = 4,
805 [IRQ_DM365_GPIO3
] = 4,
806 [IRQ_DM365_GPIO4
] = 7,
807 [IRQ_DM365_GPIO5
] = 7,
808 [IRQ_DM365_GPIO6
] = 7,
809 [IRQ_DM365_GPIO7
] = 7,
810 [IRQ_DM365_EMAC_RXTHRESH
] = 7,
811 [IRQ_DM365_EMAC_RXPULSE
] = 7,
812 [IRQ_DM365_EMAC_TXPULSE
] = 7,
813 [IRQ_DM365_EMAC_MISCPULSE
] = 7,
814 [IRQ_DM365_GPIO12
] = 7,
815 [IRQ_DM365_GPIO13
] = 7,
816 [IRQ_DM365_GPIO14
] = 7,
817 [IRQ_DM365_GPIO15
] = 7,
818 [IRQ_DM365_KEYINT
] = 7,
819 [IRQ_DM365_TCERRINT2
] = 7,
820 [IRQ_DM365_TCERRINT3
] = 7,
821 [IRQ_DM365_EMUINT
] = 7,
824 /* Four Transfer Controllers on DM365 */
826 dm365_queue_tc_mapping
[][2] = {
827 /* {event queue no, TC no} */
836 dm365_queue_priority_mapping
[][2] = {
837 /* {event queue no, Priority} */
845 static struct edma_soc_info edma_cc0_info
= {
851 .queue_tc_mapping
= dm365_queue_tc_mapping
,
852 .queue_priority_mapping
= dm365_queue_priority_mapping
,
853 .default_queue
= EVENTQ_3
,
856 static struct edma_soc_info
*dm365_edma_info
[EDMA_MAX_CC
] = {
860 static struct resource edma_resources
[] = {
864 .end
= 0x01c00000 + SZ_64K
- 1,
865 .flags
= IORESOURCE_MEM
,
870 .end
= 0x01c10000 + SZ_1K
- 1,
871 .flags
= IORESOURCE_MEM
,
876 .end
= 0x01c10400 + SZ_1K
- 1,
877 .flags
= IORESOURCE_MEM
,
882 .end
= 0x01c10800 + SZ_1K
- 1,
883 .flags
= IORESOURCE_MEM
,
888 .end
= 0x01c10c00 + SZ_1K
- 1,
889 .flags
= IORESOURCE_MEM
,
894 .flags
= IORESOURCE_IRQ
,
898 .start
= IRQ_CCERRINT
,
899 .flags
= IORESOURCE_IRQ
,
901 /* not using TC*_ERR */
904 static struct platform_device dm365_edma_device
= {
907 .dev
.platform_data
= dm365_edma_info
,
908 .num_resources
= ARRAY_SIZE(edma_resources
),
909 .resource
= edma_resources
,
912 static struct resource dm365_asp_resources
[] = {
914 .start
= DAVINCI_DM365_ASP0_BASE
,
915 .end
= DAVINCI_DM365_ASP0_BASE
+ SZ_8K
- 1,
916 .flags
= IORESOURCE_MEM
,
919 .start
= DAVINCI_DMA_ASP0_TX
,
920 .end
= DAVINCI_DMA_ASP0_TX
,
921 .flags
= IORESOURCE_DMA
,
924 .start
= DAVINCI_DMA_ASP0_RX
,
925 .end
= DAVINCI_DMA_ASP0_RX
,
926 .flags
= IORESOURCE_DMA
,
930 static struct platform_device dm365_asp_device
= {
931 .name
= "davinci-mcbsp",
933 .num_resources
= ARRAY_SIZE(dm365_asp_resources
),
934 .resource
= dm365_asp_resources
,
937 static struct resource dm365_vc_resources
[] = {
939 .start
= DAVINCI_DM365_VC_BASE
,
940 .end
= DAVINCI_DM365_VC_BASE
+ SZ_1K
- 1,
941 .flags
= IORESOURCE_MEM
,
944 .start
= DAVINCI_DMA_VC_TX
,
945 .end
= DAVINCI_DMA_VC_TX
,
946 .flags
= IORESOURCE_DMA
,
949 .start
= DAVINCI_DMA_VC_RX
,
950 .end
= DAVINCI_DMA_VC_RX
,
951 .flags
= IORESOURCE_DMA
,
955 static struct platform_device dm365_vc_device
= {
956 .name
= "davinci_voicecodec",
958 .num_resources
= ARRAY_SIZE(dm365_vc_resources
),
959 .resource
= dm365_vc_resources
,
962 static struct resource dm365_rtc_resources
[] = {
964 .start
= DM365_RTC_BASE
,
965 .end
= DM365_RTC_BASE
+ SZ_1K
- 1,
966 .flags
= IORESOURCE_MEM
,
969 .start
= IRQ_DM365_RTCINT
,
970 .flags
= IORESOURCE_IRQ
,
974 static struct platform_device dm365_rtc_device
= {
975 .name
= "rtc_davinci",
977 .num_resources
= ARRAY_SIZE(dm365_rtc_resources
),
978 .resource
= dm365_rtc_resources
,
981 static struct map_desc dm365_io_desc
[] = {
984 .pfn
= __phys_to_pfn(IO_PHYS
),
990 static struct resource dm365_ks_resources
[] = {
993 .start
= DM365_KEYSCAN_BASE
,
994 .end
= DM365_KEYSCAN_BASE
+ SZ_1K
- 1,
995 .flags
= IORESOURCE_MEM
,
999 .start
= IRQ_DM365_KEYINT
,
1000 .end
= IRQ_DM365_KEYINT
,
1001 .flags
= IORESOURCE_IRQ
,
1005 static struct platform_device dm365_ks_device
= {
1006 .name
= "davinci_keyscan",
1008 .num_resources
= ARRAY_SIZE(dm365_ks_resources
),
1009 .resource
= dm365_ks_resources
,
1012 /* Contents of JTAG ID register used to identify exact cpu type */
1013 static struct davinci_id dm365_ids
[] = {
1017 .manufacturer
= 0x017,
1018 .cpu_id
= DAVINCI_CPU_ID_DM365
,
1019 .name
= "dm365_rev1.1",
1024 .manufacturer
= 0x017,
1025 .cpu_id
= DAVINCI_CPU_ID_DM365
,
1026 .name
= "dm365_rev1.2",
1030 static u32 dm365_psc_bases
[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE
};
1032 static struct davinci_timer_info dm365_timer_info
= {
1033 .timers
= davinci_timer_instance
,
1034 .clockevent_id
= T0_BOT
,
1035 .clocksource_id
= T0_TOP
,
1038 #define DM365_UART1_BASE (IO_PHYS + 0x106000)
1040 static struct plat_serial8250_port dm365_serial_platform_data
[] = {
1042 .mapbase
= DAVINCI_UART0_BASE
,
1043 .irq
= IRQ_UARTINT0
,
1044 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
1050 .mapbase
= DM365_UART1_BASE
,
1051 .irq
= IRQ_UARTINT1
,
1052 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
1062 static struct platform_device dm365_serial_device
= {
1063 .name
= "serial8250",
1064 .id
= PLAT8250_DEV_PLATFORM
,
1066 .platform_data
= dm365_serial_platform_data
,
1070 static struct davinci_soc_info davinci_soc_info_dm365
= {
1071 .io_desc
= dm365_io_desc
,
1072 .io_desc_num
= ARRAY_SIZE(dm365_io_desc
),
1073 .jtag_id_reg
= 0x01c40028,
1075 .ids_num
= ARRAY_SIZE(dm365_ids
),
1076 .cpu_clks
= dm365_clks
,
1077 .psc_bases
= dm365_psc_bases
,
1078 .psc_bases_num
= ARRAY_SIZE(dm365_psc_bases
),
1079 .pinmux_base
= DAVINCI_SYSTEM_MODULE_BASE
,
1080 .pinmux_pins
= dm365_pins
,
1081 .pinmux_pins_num
= ARRAY_SIZE(dm365_pins
),
1082 .intc_base
= DAVINCI_ARM_INTC_BASE
,
1083 .intc_type
= DAVINCI_INTC_TYPE_AINTC
,
1084 .intc_irq_prios
= dm365_default_priorities
,
1085 .intc_irq_num
= DAVINCI_N_AINTC_IRQ
,
1086 .timer_info
= &dm365_timer_info
,
1087 .gpio_type
= GPIO_TYPE_DAVINCI
,
1088 .gpio_base
= DAVINCI_GPIO_BASE
,
1090 .gpio_irq
= IRQ_DM365_GPIO0
,
1091 .gpio_unbanked
= 8, /* really 16 ... skip muxed GPIOs */
1092 .serial_dev
= &dm365_serial_device
,
1093 .emac_pdata
= &dm365_emac_pdata
,
1094 .sram_dma
= 0x00010000,
1098 void __init
dm365_init_asp(struct snd_platform_data
*pdata
)
1100 davinci_cfg_reg(DM365_MCBSP0_BDX
);
1101 davinci_cfg_reg(DM365_MCBSP0_X
);
1102 davinci_cfg_reg(DM365_MCBSP0_BFSX
);
1103 davinci_cfg_reg(DM365_MCBSP0_BDR
);
1104 davinci_cfg_reg(DM365_MCBSP0_R
);
1105 davinci_cfg_reg(DM365_MCBSP0_BFSR
);
1106 davinci_cfg_reg(DM365_EVT2_ASP_TX
);
1107 davinci_cfg_reg(DM365_EVT3_ASP_RX
);
1108 dm365_asp_device
.dev
.platform_data
= pdata
;
1109 platform_device_register(&dm365_asp_device
);
1112 void __init
dm365_init_vc(struct snd_platform_data
*pdata
)
1114 davinci_cfg_reg(DM365_EVT2_VC_TX
);
1115 davinci_cfg_reg(DM365_EVT3_VC_RX
);
1116 dm365_vc_device
.dev
.platform_data
= pdata
;
1117 platform_device_register(&dm365_vc_device
);
1120 void __init
dm365_init_ks(struct davinci_ks_platform_data
*pdata
)
1122 dm365_ks_device
.dev
.platform_data
= pdata
;
1123 platform_device_register(&dm365_ks_device
);
1126 void __init
dm365_init_rtc(void)
1128 davinci_cfg_reg(DM365_INT_PRTCSS
);
1129 platform_device_register(&dm365_rtc_device
);
1132 void __init
dm365_init(void)
1134 davinci_common_init(&davinci_soc_info_dm365
);
1135 davinci_map_sysmod();
1138 static struct resource dm365_vpss_resources
[] = {
1140 /* VPSS ISP5 Base address */
1142 .start
= 0x01c70000,
1143 .end
= 0x01c70000 + 0xff,
1144 .flags
= IORESOURCE_MEM
,
1147 /* VPSS CLK Base address */
1149 .start
= 0x01c70200,
1150 .end
= 0x01c70200 + 0xff,
1151 .flags
= IORESOURCE_MEM
,
1155 static struct platform_device dm365_vpss_device
= {
1158 .dev
.platform_data
= "dm365_vpss",
1159 .num_resources
= ARRAY_SIZE(dm365_vpss_resources
),
1160 .resource
= dm365_vpss_resources
,
1163 static struct resource vpfe_resources
[] = {
1165 .start
= IRQ_VDINT0
,
1167 .flags
= IORESOURCE_IRQ
,
1170 .start
= IRQ_VDINT1
,
1172 .flags
= IORESOURCE_IRQ
,
1176 static u64 vpfe_capture_dma_mask
= DMA_BIT_MASK(32);
1177 static struct platform_device vpfe_capture_dev
= {
1178 .name
= CAPTURE_DRV_NAME
,
1180 .num_resources
= ARRAY_SIZE(vpfe_resources
),
1181 .resource
= vpfe_resources
,
1183 .dma_mask
= &vpfe_capture_dma_mask
,
1184 .coherent_dma_mask
= DMA_BIT_MASK(32),
1188 static void dm365_isif_setup_pinmux(void)
1190 davinci_cfg_reg(DM365_VIN_CAM_WEN
);
1191 davinci_cfg_reg(DM365_VIN_CAM_VD
);
1192 davinci_cfg_reg(DM365_VIN_CAM_HD
);
1193 davinci_cfg_reg(DM365_VIN_YIN4_7_EN
);
1194 davinci_cfg_reg(DM365_VIN_YIN0_3_EN
);
1197 static struct resource isif_resource
[] = {
1198 /* ISIF Base address */
1200 .start
= 0x01c71000,
1201 .end
= 0x01c71000 + 0x1ff,
1202 .flags
= IORESOURCE_MEM
,
1204 /* ISIF Linearization table 0 */
1207 .end
= 0x1C7C000 + 0x2ff,
1208 .flags
= IORESOURCE_MEM
,
1210 /* ISIF Linearization table 1 */
1213 .end
= 0x1C7C400 + 0x2ff,
1214 .flags
= IORESOURCE_MEM
,
1217 static struct platform_device dm365_isif_dev
= {
1220 .num_resources
= ARRAY_SIZE(isif_resource
),
1221 .resource
= isif_resource
,
1223 .dma_mask
= &vpfe_capture_dma_mask
,
1224 .coherent_dma_mask
= DMA_BIT_MASK(32),
1225 .platform_data
= dm365_isif_setup_pinmux
,
1229 static int __init
dm365_init_devices(void)
1231 if (!cpu_is_davinci_dm365())
1234 davinci_cfg_reg(DM365_INT_EDMA_CC
);
1235 platform_device_register(&dm365_edma_device
);
1237 platform_device_register(&dm365_mdio_device
);
1238 platform_device_register(&dm365_emac_device
);
1239 clk_add_alias(NULL
, dev_name(&dm365_mdio_device
.dev
),
1240 NULL
, &dm365_emac_device
.dev
);
1242 /* Add isif clock alias */
1243 clk_add_alias("master", dm365_isif_dev
.name
, "vpss_master", NULL
);
1244 platform_device_register(&dm365_vpss_device
);
1245 platform_device_register(&dm365_isif_dev
);
1246 platform_device_register(&vpfe_capture_dev
);
1249 postcore_initcall(dm365_init_devices
);
1251 void dm365_set_vpfe_config(struct vpfe_config
*cfg
)
1253 vpfe_capture_dev
.dev
.platform_data
= cfg
;