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[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-davinci / dm365.c
1 /*
2 * TI DaVinci DM365 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/serial_8250.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/spi/spi.h>
22 #include <linux/platform_data/edma.h>
23 #include <linux/platform_data/gpio-davinci.h>
24 #include <linux/platform_data/keyscan-davinci.h>
25 #include <linux/platform_data/spi-davinci.h>
26
27 #include <asm/mach/map.h>
28
29 #include <mach/cputype.h>
30 #include "psc.h"
31 #include <mach/mux.h>
32 #include <mach/irqs.h>
33 #include <mach/time.h>
34 #include <mach/serial.h>
35 #include <mach/common.h>
36
37 #include "davinci.h"
38 #include "clock.h"
39 #include "mux.h"
40 #include "asp.h"
41
42 #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
43 #define DM365_RTC_BASE 0x01c69000
44 #define DM365_KEYSCAN_BASE 0x01c69400
45 #define DM365_OSD_BASE 0x01c71c00
46 #define DM365_VENC_BASE 0x01c71e00
47 #define DAVINCI_DM365_VC_BASE 0x01d0c000
48 #define DAVINCI_DMA_VC_TX 2
49 #define DAVINCI_DMA_VC_RX 3
50 #define DM365_EMAC_BASE 0x01d07000
51 #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
52 #define DM365_EMAC_CNTRL_OFFSET 0x0000
53 #define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
54 #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
55 #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
56
57 static struct pll_data pll1_data = {
58 .num = 1,
59 .phys_base = DAVINCI_PLL1_BASE,
60 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
61 };
62
63 static struct pll_data pll2_data = {
64 .num = 2,
65 .phys_base = DAVINCI_PLL2_BASE,
66 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
67 };
68
69 static struct clk ref_clk = {
70 .name = "ref_clk",
71 .rate = DM365_REF_FREQ,
72 };
73
74 static struct clk pll1_clk = {
75 .name = "pll1",
76 .parent = &ref_clk,
77 .flags = CLK_PLL,
78 .pll_data = &pll1_data,
79 };
80
81 static struct clk pll1_aux_clk = {
82 .name = "pll1_aux_clk",
83 .parent = &pll1_clk,
84 .flags = CLK_PLL | PRE_PLL,
85 };
86
87 static struct clk pll1_sysclkbp = {
88 .name = "pll1_sysclkbp",
89 .parent = &pll1_clk,
90 .flags = CLK_PLL | PRE_PLL,
91 .div_reg = BPDIV
92 };
93
94 static struct clk clkout0_clk = {
95 .name = "clkout0",
96 .parent = &pll1_clk,
97 .flags = CLK_PLL | PRE_PLL,
98 };
99
100 static struct clk pll1_sysclk1 = {
101 .name = "pll1_sysclk1",
102 .parent = &pll1_clk,
103 .flags = CLK_PLL,
104 .div_reg = PLLDIV1,
105 };
106
107 static struct clk pll1_sysclk2 = {
108 .name = "pll1_sysclk2",
109 .parent = &pll1_clk,
110 .flags = CLK_PLL,
111 .div_reg = PLLDIV2,
112 };
113
114 static struct clk pll1_sysclk3 = {
115 .name = "pll1_sysclk3",
116 .parent = &pll1_clk,
117 .flags = CLK_PLL,
118 .div_reg = PLLDIV3,
119 };
120
121 static struct clk pll1_sysclk4 = {
122 .name = "pll1_sysclk4",
123 .parent = &pll1_clk,
124 .flags = CLK_PLL,
125 .div_reg = PLLDIV4,
126 };
127
128 static struct clk pll1_sysclk5 = {
129 .name = "pll1_sysclk5",
130 .parent = &pll1_clk,
131 .flags = CLK_PLL,
132 .div_reg = PLLDIV5,
133 };
134
135 static struct clk pll1_sysclk6 = {
136 .name = "pll1_sysclk6",
137 .parent = &pll1_clk,
138 .flags = CLK_PLL,
139 .div_reg = PLLDIV6,
140 };
141
142 static struct clk pll1_sysclk7 = {
143 .name = "pll1_sysclk7",
144 .parent = &pll1_clk,
145 .flags = CLK_PLL,
146 .div_reg = PLLDIV7,
147 };
148
149 static struct clk pll1_sysclk8 = {
150 .name = "pll1_sysclk8",
151 .parent = &pll1_clk,
152 .flags = CLK_PLL,
153 .div_reg = PLLDIV8,
154 };
155
156 static struct clk pll1_sysclk9 = {
157 .name = "pll1_sysclk9",
158 .parent = &pll1_clk,
159 .flags = CLK_PLL,
160 .div_reg = PLLDIV9,
161 };
162
163 static struct clk pll2_clk = {
164 .name = "pll2",
165 .parent = &ref_clk,
166 .flags = CLK_PLL,
167 .pll_data = &pll2_data,
168 };
169
170 static struct clk pll2_aux_clk = {
171 .name = "pll2_aux_clk",
172 .parent = &pll2_clk,
173 .flags = CLK_PLL | PRE_PLL,
174 };
175
176 static struct clk clkout1_clk = {
177 .name = "clkout1",
178 .parent = &pll2_clk,
179 .flags = CLK_PLL | PRE_PLL,
180 };
181
182 static struct clk pll2_sysclk1 = {
183 .name = "pll2_sysclk1",
184 .parent = &pll2_clk,
185 .flags = CLK_PLL,
186 .div_reg = PLLDIV1,
187 };
188
189 static struct clk pll2_sysclk2 = {
190 .name = "pll2_sysclk2",
191 .parent = &pll2_clk,
192 .flags = CLK_PLL,
193 .div_reg = PLLDIV2,
194 };
195
196 static struct clk pll2_sysclk3 = {
197 .name = "pll2_sysclk3",
198 .parent = &pll2_clk,
199 .flags = CLK_PLL,
200 .div_reg = PLLDIV3,
201 };
202
203 static struct clk pll2_sysclk4 = {
204 .name = "pll2_sysclk4",
205 .parent = &pll2_clk,
206 .flags = CLK_PLL,
207 .div_reg = PLLDIV4,
208 };
209
210 static struct clk pll2_sysclk5 = {
211 .name = "pll2_sysclk5",
212 .parent = &pll2_clk,
213 .flags = CLK_PLL,
214 .div_reg = PLLDIV5,
215 };
216
217 static struct clk pll2_sysclk6 = {
218 .name = "pll2_sysclk6",
219 .parent = &pll2_clk,
220 .flags = CLK_PLL,
221 .div_reg = PLLDIV6,
222 };
223
224 static struct clk pll2_sysclk7 = {
225 .name = "pll2_sysclk7",
226 .parent = &pll2_clk,
227 .flags = CLK_PLL,
228 .div_reg = PLLDIV7,
229 };
230
231 static struct clk pll2_sysclk8 = {
232 .name = "pll2_sysclk8",
233 .parent = &pll2_clk,
234 .flags = CLK_PLL,
235 .div_reg = PLLDIV8,
236 };
237
238 static struct clk pll2_sysclk9 = {
239 .name = "pll2_sysclk9",
240 .parent = &pll2_clk,
241 .flags = CLK_PLL,
242 .div_reg = PLLDIV9,
243 };
244
245 static struct clk vpss_dac_clk = {
246 .name = "vpss_dac",
247 .parent = &pll1_sysclk3,
248 .lpsc = DM365_LPSC_DAC_CLK,
249 };
250
251 static struct clk vpss_master_clk = {
252 .name = "vpss_master",
253 .parent = &pll1_sysclk5,
254 .lpsc = DM365_LPSC_VPSSMSTR,
255 .flags = CLK_PSC,
256 };
257
258 static struct clk vpss_slave_clk = {
259 .name = "vpss_slave",
260 .parent = &pll1_sysclk5,
261 .lpsc = DAVINCI_LPSC_VPSSSLV,
262 };
263
264 static struct clk arm_clk = {
265 .name = "arm_clk",
266 .parent = &pll2_sysclk2,
267 .lpsc = DAVINCI_LPSC_ARM,
268 .flags = ALWAYS_ENABLED,
269 };
270
271 static struct clk uart0_clk = {
272 .name = "uart0",
273 .parent = &pll1_aux_clk,
274 .lpsc = DAVINCI_LPSC_UART0,
275 };
276
277 static struct clk uart1_clk = {
278 .name = "uart1",
279 .parent = &pll1_sysclk4,
280 .lpsc = DAVINCI_LPSC_UART1,
281 };
282
283 static struct clk i2c_clk = {
284 .name = "i2c",
285 .parent = &pll1_aux_clk,
286 .lpsc = DAVINCI_LPSC_I2C,
287 };
288
289 static struct clk mmcsd0_clk = {
290 .name = "mmcsd0",
291 .parent = &pll1_sysclk8,
292 .lpsc = DAVINCI_LPSC_MMC_SD,
293 };
294
295 static struct clk mmcsd1_clk = {
296 .name = "mmcsd1",
297 .parent = &pll1_sysclk4,
298 .lpsc = DM365_LPSC_MMC_SD1,
299 };
300
301 static struct clk spi0_clk = {
302 .name = "spi0",
303 .parent = &pll1_sysclk4,
304 .lpsc = DAVINCI_LPSC_SPI,
305 };
306
307 static struct clk spi1_clk = {
308 .name = "spi1",
309 .parent = &pll1_sysclk4,
310 .lpsc = DM365_LPSC_SPI1,
311 };
312
313 static struct clk spi2_clk = {
314 .name = "spi2",
315 .parent = &pll1_sysclk4,
316 .lpsc = DM365_LPSC_SPI2,
317 };
318
319 static struct clk spi3_clk = {
320 .name = "spi3",
321 .parent = &pll1_sysclk4,
322 .lpsc = DM365_LPSC_SPI3,
323 };
324
325 static struct clk spi4_clk = {
326 .name = "spi4",
327 .parent = &pll1_aux_clk,
328 .lpsc = DM365_LPSC_SPI4,
329 };
330
331 static struct clk gpio_clk = {
332 .name = "gpio",
333 .parent = &pll1_sysclk4,
334 .lpsc = DAVINCI_LPSC_GPIO,
335 };
336
337 static struct clk aemif_clk = {
338 .name = "aemif",
339 .parent = &pll1_sysclk4,
340 .lpsc = DAVINCI_LPSC_AEMIF,
341 };
342
343 static struct clk pwm0_clk = {
344 .name = "pwm0",
345 .parent = &pll1_aux_clk,
346 .lpsc = DAVINCI_LPSC_PWM0,
347 };
348
349 static struct clk pwm1_clk = {
350 .name = "pwm1",
351 .parent = &pll1_aux_clk,
352 .lpsc = DAVINCI_LPSC_PWM1,
353 };
354
355 static struct clk pwm2_clk = {
356 .name = "pwm2",
357 .parent = &pll1_aux_clk,
358 .lpsc = DAVINCI_LPSC_PWM2,
359 };
360
361 static struct clk pwm3_clk = {
362 .name = "pwm3",
363 .parent = &ref_clk,
364 .lpsc = DM365_LPSC_PWM3,
365 };
366
367 static struct clk timer0_clk = {
368 .name = "timer0",
369 .parent = &pll1_aux_clk,
370 .lpsc = DAVINCI_LPSC_TIMER0,
371 };
372
373 static struct clk timer1_clk = {
374 .name = "timer1",
375 .parent = &pll1_aux_clk,
376 .lpsc = DAVINCI_LPSC_TIMER1,
377 };
378
379 static struct clk timer2_clk = {
380 .name = "timer2",
381 .parent = &pll1_aux_clk,
382 .lpsc = DAVINCI_LPSC_TIMER2,
383 .usecount = 1,
384 };
385
386 static struct clk timer3_clk = {
387 .name = "timer3",
388 .parent = &pll1_aux_clk,
389 .lpsc = DM365_LPSC_TIMER3,
390 };
391
392 static struct clk usb_clk = {
393 .name = "usb",
394 .parent = &pll1_aux_clk,
395 .lpsc = DAVINCI_LPSC_USB,
396 };
397
398 static struct clk emac_clk = {
399 .name = "emac",
400 .parent = &pll1_sysclk4,
401 .lpsc = DM365_LPSC_EMAC,
402 };
403
404 static struct clk voicecodec_clk = {
405 .name = "voice_codec",
406 .parent = &pll2_sysclk4,
407 .lpsc = DM365_LPSC_VOICE_CODEC,
408 };
409
410 static struct clk asp0_clk = {
411 .name = "asp0",
412 .parent = &pll1_sysclk4,
413 .lpsc = DM365_LPSC_McBSP1,
414 };
415
416 static struct clk rto_clk = {
417 .name = "rto",
418 .parent = &pll1_sysclk4,
419 .lpsc = DM365_LPSC_RTO,
420 };
421
422 static struct clk mjcp_clk = {
423 .name = "mjcp",
424 .parent = &pll1_sysclk3,
425 .lpsc = DM365_LPSC_MJCP,
426 };
427
428 static struct clk_lookup dm365_clks[] = {
429 CLK(NULL, "ref", &ref_clk),
430 CLK(NULL, "pll1", &pll1_clk),
431 CLK(NULL, "pll1_aux", &pll1_aux_clk),
432 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
433 CLK(NULL, "clkout0", &clkout0_clk),
434 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
435 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
436 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
437 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
438 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
439 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
440 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
441 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
442 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
443 CLK(NULL, "pll2", &pll2_clk),
444 CLK(NULL, "pll2_aux", &pll2_aux_clk),
445 CLK(NULL, "clkout1", &clkout1_clk),
446 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
447 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
448 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
449 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
450 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
451 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
452 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
453 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
454 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
455 CLK(NULL, "vpss_dac", &vpss_dac_clk),
456 CLK("vpss", "master", &vpss_master_clk),
457 CLK("vpss", "slave", &vpss_slave_clk),
458 CLK(NULL, "arm", &arm_clk),
459 CLK("serial8250.0", NULL, &uart0_clk),
460 CLK("serial8250.1", NULL, &uart1_clk),
461 CLK("i2c_davinci.1", NULL, &i2c_clk),
462 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
463 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
464 CLK("spi_davinci.0", NULL, &spi0_clk),
465 CLK("spi_davinci.1", NULL, &spi1_clk),
466 CLK("spi_davinci.2", NULL, &spi2_clk),
467 CLK("spi_davinci.3", NULL, &spi3_clk),
468 CLK("spi_davinci.4", NULL, &spi4_clk),
469 CLK(NULL, "gpio", &gpio_clk),
470 CLK(NULL, "aemif", &aemif_clk),
471 CLK(NULL, "pwm0", &pwm0_clk),
472 CLK(NULL, "pwm1", &pwm1_clk),
473 CLK(NULL, "pwm2", &pwm2_clk),
474 CLK(NULL, "pwm3", &pwm3_clk),
475 CLK(NULL, "timer0", &timer0_clk),
476 CLK(NULL, "timer1", &timer1_clk),
477 CLK("davinci-wdt", NULL, &timer2_clk),
478 CLK(NULL, "timer3", &timer3_clk),
479 CLK(NULL, "usb", &usb_clk),
480 CLK("davinci_emac.1", NULL, &emac_clk),
481 CLK("davinci_mdio.0", "fck", &emac_clk),
482 CLK("davinci_voicecodec", NULL, &voicecodec_clk),
483 CLK("davinci-mcbsp", NULL, &asp0_clk),
484 CLK(NULL, "rto", &rto_clk),
485 CLK(NULL, "mjcp", &mjcp_clk),
486 CLK(NULL, NULL, NULL),
487 };
488
489 /*----------------------------------------------------------------------*/
490
491 #define INTMUX 0x18
492 #define EVTMUX 0x1c
493
494
495 static const struct mux_config dm365_pins[] = {
496 #ifdef CONFIG_DAVINCI_MUX
497 MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
498
499 MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
500 MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
501 MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
502 MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
503 MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
504 MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
505
506 MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
507 MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
508
509 MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
510 MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
511 MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
512 MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
513 MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
514 MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
515 MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
516 MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
517
518 MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
519 MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
520 MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
521 MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
522 MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
523 MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
524
525 MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
526 MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
527 MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
528 MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
529 MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
530
531 MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
532 MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
533 MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
534 MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
535 MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
536 MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
537
538 MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
539 MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
540 MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
541 MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
542 MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
543 MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
544 MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
545 MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
546 MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
547 MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
548 MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
549 MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
550 MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
551 MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
552 MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
553 MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
554 MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
555
556 MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
557
558 MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
559 MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
560 MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
561 MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
562 MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
563 MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
564 MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
565 MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
566 MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
567 MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
568 MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
569 MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
570
571 MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
572 MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
573 MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
574 MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
575 MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
576
577 MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
578 MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
579 MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
580 MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
581 MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
582
583 MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
584 MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
585 MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
586 MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
587 MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
588
589 MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
590 MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
591 MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
592 MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
593 MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
594
595 MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
596 MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
597 MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
598
599 MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
600 MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
601 MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
602 MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
603 MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
604 MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
605 MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
606
607 MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
608 MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
609 MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
610 MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
611 MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
612 MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
613 MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
614 MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
615 MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
616 MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
617
618 INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
619 INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
620 INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
621 INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
622 INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
623 INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
624 INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
625 INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
626 INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
627 INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
628 INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
629 INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
630 INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
631 INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
632 INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
633 INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
634 INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
635 INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
636
637 EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
638 EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
639 EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
640 EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
641 #endif
642 };
643
644 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
645
646 static struct davinci_spi_platform_data dm365_spi0_pdata = {
647 .version = SPI_VERSION_1,
648 .num_chipselect = 2,
649 .dma_event_q = EVENTQ_3,
650 .prescaler_limit = 1,
651 };
652
653 static struct resource dm365_spi0_resources[] = {
654 {
655 .start = 0x01c66000,
656 .end = 0x01c667ff,
657 .flags = IORESOURCE_MEM,
658 },
659 {
660 .start = IRQ_DM365_SPIINT0_0,
661 .flags = IORESOURCE_IRQ,
662 },
663 };
664
665 static struct platform_device dm365_spi0_device = {
666 .name = "spi_davinci",
667 .id = 0,
668 .dev = {
669 .dma_mask = &dm365_spi0_dma_mask,
670 .coherent_dma_mask = DMA_BIT_MASK(32),
671 .platform_data = &dm365_spi0_pdata,
672 },
673 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
674 .resource = dm365_spi0_resources,
675 };
676
677 void __init dm365_init_spi0(unsigned chipselect_mask,
678 const struct spi_board_info *info, unsigned len)
679 {
680 davinci_cfg_reg(DM365_SPI0_SCLK);
681 davinci_cfg_reg(DM365_SPI0_SDI);
682 davinci_cfg_reg(DM365_SPI0_SDO);
683
684 /* not all slaves will be wired up */
685 if (chipselect_mask & BIT(0))
686 davinci_cfg_reg(DM365_SPI0_SDENA0);
687 if (chipselect_mask & BIT(1))
688 davinci_cfg_reg(DM365_SPI0_SDENA1);
689
690 spi_register_board_info(info, len);
691
692 platform_device_register(&dm365_spi0_device);
693 }
694
695 static struct resource dm365_gpio_resources[] = {
696 { /* registers */
697 .start = DAVINCI_GPIO_BASE,
698 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
699 .flags = IORESOURCE_MEM,
700 },
701 { /* interrupt */
702 .start = IRQ_DM365_GPIO0,
703 .end = IRQ_DM365_GPIO0,
704 .flags = IORESOURCE_IRQ,
705 },
706 {
707 .start = IRQ_DM365_GPIO1,
708 .end = IRQ_DM365_GPIO1,
709 .flags = IORESOURCE_IRQ,
710 },
711 {
712 .start = IRQ_DM365_GPIO2,
713 .end = IRQ_DM365_GPIO2,
714 .flags = IORESOURCE_IRQ,
715 },
716 {
717 .start = IRQ_DM365_GPIO3,
718 .end = IRQ_DM365_GPIO3,
719 .flags = IORESOURCE_IRQ,
720 },
721 {
722 .start = IRQ_DM365_GPIO4,
723 .end = IRQ_DM365_GPIO4,
724 .flags = IORESOURCE_IRQ,
725 },
726 {
727 .start = IRQ_DM365_GPIO5,
728 .end = IRQ_DM365_GPIO5,
729 .flags = IORESOURCE_IRQ,
730 },
731 {
732 .start = IRQ_DM365_GPIO6,
733 .end = IRQ_DM365_GPIO6,
734 .flags = IORESOURCE_IRQ,
735 },
736 {
737 .start = IRQ_DM365_GPIO7,
738 .end = IRQ_DM365_GPIO7,
739 .flags = IORESOURCE_IRQ,
740 },
741 };
742
743 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
744 .ngpio = 104,
745 .gpio_unbanked = 8,
746 };
747
748 int __init dm365_gpio_register(void)
749 {
750 return davinci_gpio_register(dm365_gpio_resources,
751 ARRAY_SIZE(dm365_gpio_resources),
752 &dm365_gpio_platform_data);
753 }
754
755 static struct emac_platform_data dm365_emac_pdata = {
756 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
757 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
758 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
759 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
760 .version = EMAC_VERSION_2,
761 };
762
763 static struct resource dm365_emac_resources[] = {
764 {
765 .start = DM365_EMAC_BASE,
766 .end = DM365_EMAC_BASE + SZ_16K - 1,
767 .flags = IORESOURCE_MEM,
768 },
769 {
770 .start = IRQ_DM365_EMAC_RXTHRESH,
771 .end = IRQ_DM365_EMAC_RXTHRESH,
772 .flags = IORESOURCE_IRQ,
773 },
774 {
775 .start = IRQ_DM365_EMAC_RXPULSE,
776 .end = IRQ_DM365_EMAC_RXPULSE,
777 .flags = IORESOURCE_IRQ,
778 },
779 {
780 .start = IRQ_DM365_EMAC_TXPULSE,
781 .end = IRQ_DM365_EMAC_TXPULSE,
782 .flags = IORESOURCE_IRQ,
783 },
784 {
785 .start = IRQ_DM365_EMAC_MISCPULSE,
786 .end = IRQ_DM365_EMAC_MISCPULSE,
787 .flags = IORESOURCE_IRQ,
788 },
789 };
790
791 static struct platform_device dm365_emac_device = {
792 .name = "davinci_emac",
793 .id = 1,
794 .dev = {
795 .platform_data = &dm365_emac_pdata,
796 },
797 .num_resources = ARRAY_SIZE(dm365_emac_resources),
798 .resource = dm365_emac_resources,
799 };
800
801 static struct resource dm365_mdio_resources[] = {
802 {
803 .start = DM365_EMAC_MDIO_BASE,
804 .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
805 .flags = IORESOURCE_MEM,
806 },
807 };
808
809 static struct platform_device dm365_mdio_device = {
810 .name = "davinci_mdio",
811 .id = 0,
812 .num_resources = ARRAY_SIZE(dm365_mdio_resources),
813 .resource = dm365_mdio_resources,
814 };
815
816 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
817 [IRQ_VDINT0] = 2,
818 [IRQ_VDINT1] = 6,
819 [IRQ_VDINT2] = 6,
820 [IRQ_HISTINT] = 6,
821 [IRQ_H3AINT] = 6,
822 [IRQ_PRVUINT] = 6,
823 [IRQ_RSZINT] = 6,
824 [IRQ_DM365_INSFINT] = 7,
825 [IRQ_VENCINT] = 6,
826 [IRQ_ASQINT] = 6,
827 [IRQ_IMXINT] = 6,
828 [IRQ_DM365_IMCOPINT] = 4,
829 [IRQ_USBINT] = 4,
830 [IRQ_DM365_RTOINT] = 7,
831 [IRQ_DM365_TINT5] = 7,
832 [IRQ_DM365_TINT6] = 5,
833 [IRQ_CCINT0] = 5,
834 [IRQ_CCERRINT] = 5,
835 [IRQ_TCERRINT0] = 5,
836 [IRQ_TCERRINT] = 7,
837 [IRQ_PSCIN] = 4,
838 [IRQ_DM365_SPINT2_1] = 7,
839 [IRQ_DM365_TINT7] = 7,
840 [IRQ_DM365_SDIOINT0] = 7,
841 [IRQ_MBXINT] = 7,
842 [IRQ_MBRINT] = 7,
843 [IRQ_MMCINT] = 7,
844 [IRQ_DM365_MMCINT1] = 7,
845 [IRQ_DM365_PWMINT3] = 7,
846 [IRQ_AEMIFINT] = 2,
847 [IRQ_DM365_SDIOINT1] = 2,
848 [IRQ_TINT0_TINT12] = 7,
849 [IRQ_TINT0_TINT34] = 7,
850 [IRQ_TINT1_TINT12] = 7,
851 [IRQ_TINT1_TINT34] = 7,
852 [IRQ_PWMINT0] = 7,
853 [IRQ_PWMINT1] = 3,
854 [IRQ_PWMINT2] = 3,
855 [IRQ_I2C] = 3,
856 [IRQ_UARTINT0] = 3,
857 [IRQ_UARTINT1] = 3,
858 [IRQ_DM365_RTCINT] = 3,
859 [IRQ_DM365_SPIINT0_0] = 3,
860 [IRQ_DM365_SPIINT3_0] = 3,
861 [IRQ_DM365_GPIO0] = 3,
862 [IRQ_DM365_GPIO1] = 7,
863 [IRQ_DM365_GPIO2] = 4,
864 [IRQ_DM365_GPIO3] = 4,
865 [IRQ_DM365_GPIO4] = 7,
866 [IRQ_DM365_GPIO5] = 7,
867 [IRQ_DM365_GPIO6] = 7,
868 [IRQ_DM365_GPIO7] = 7,
869 [IRQ_DM365_EMAC_RXTHRESH] = 7,
870 [IRQ_DM365_EMAC_RXPULSE] = 7,
871 [IRQ_DM365_EMAC_TXPULSE] = 7,
872 [IRQ_DM365_EMAC_MISCPULSE] = 7,
873 [IRQ_DM365_GPIO12] = 7,
874 [IRQ_DM365_GPIO13] = 7,
875 [IRQ_DM365_GPIO14] = 7,
876 [IRQ_DM365_GPIO15] = 7,
877 [IRQ_DM365_KEYINT] = 7,
878 [IRQ_DM365_TCERRINT2] = 7,
879 [IRQ_DM365_TCERRINT3] = 7,
880 [IRQ_DM365_EMUINT] = 7,
881 };
882
883 /* Four Transfer Controllers on DM365 */
884 static s8 dm365_queue_priority_mapping[][2] = {
885 /* {event queue no, Priority} */
886 {0, 7},
887 {1, 7},
888 {2, 7},
889 {3, 0},
890 {-1, -1},
891 };
892
893 static const struct dma_slave_map dm365_edma_map[] = {
894 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
895 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
896 { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
897 { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
898 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
899 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
900 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
901 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
902 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
903 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
904 { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
905 { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
906 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
907 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
908 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
909 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
910 };
911
912 static struct edma_soc_info dm365_edma_pdata = {
913 .queue_priority_mapping = dm365_queue_priority_mapping,
914 .default_queue = EVENTQ_3,
915 .slave_map = dm365_edma_map,
916 .slavecnt = ARRAY_SIZE(dm365_edma_map),
917 };
918
919 static struct resource edma_resources[] = {
920 {
921 .name = "edma3_cc",
922 .start = 0x01c00000,
923 .end = 0x01c00000 + SZ_64K - 1,
924 .flags = IORESOURCE_MEM,
925 },
926 {
927 .name = "edma3_tc0",
928 .start = 0x01c10000,
929 .end = 0x01c10000 + SZ_1K - 1,
930 .flags = IORESOURCE_MEM,
931 },
932 {
933 .name = "edma3_tc1",
934 .start = 0x01c10400,
935 .end = 0x01c10400 + SZ_1K - 1,
936 .flags = IORESOURCE_MEM,
937 },
938 {
939 .name = "edma3_tc2",
940 .start = 0x01c10800,
941 .end = 0x01c10800 + SZ_1K - 1,
942 .flags = IORESOURCE_MEM,
943 },
944 {
945 .name = "edma3_tc3",
946 .start = 0x01c10c00,
947 .end = 0x01c10c00 + SZ_1K - 1,
948 .flags = IORESOURCE_MEM,
949 },
950 {
951 .name = "edma3_ccint",
952 .start = IRQ_CCINT0,
953 .flags = IORESOURCE_IRQ,
954 },
955 {
956 .name = "edma3_ccerrint",
957 .start = IRQ_CCERRINT,
958 .flags = IORESOURCE_IRQ,
959 },
960 /* not using TC*_ERR */
961 };
962
963 static const struct platform_device_info dm365_edma_device __initconst = {
964 .name = "edma",
965 .id = 0,
966 .dma_mask = DMA_BIT_MASK(32),
967 .res = edma_resources,
968 .num_res = ARRAY_SIZE(edma_resources),
969 .data = &dm365_edma_pdata,
970 .size_data = sizeof(dm365_edma_pdata),
971 };
972
973 static struct resource dm365_asp_resources[] = {
974 {
975 .name = "mpu",
976 .start = DAVINCI_DM365_ASP0_BASE,
977 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
978 .flags = IORESOURCE_MEM,
979 },
980 {
981 .start = DAVINCI_DMA_ASP0_TX,
982 .end = DAVINCI_DMA_ASP0_TX,
983 .flags = IORESOURCE_DMA,
984 },
985 {
986 .start = DAVINCI_DMA_ASP0_RX,
987 .end = DAVINCI_DMA_ASP0_RX,
988 .flags = IORESOURCE_DMA,
989 },
990 };
991
992 static struct platform_device dm365_asp_device = {
993 .name = "davinci-mcbsp",
994 .id = -1,
995 .num_resources = ARRAY_SIZE(dm365_asp_resources),
996 .resource = dm365_asp_resources,
997 };
998
999 static struct resource dm365_vc_resources[] = {
1000 {
1001 .start = DAVINCI_DM365_VC_BASE,
1002 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
1003 .flags = IORESOURCE_MEM,
1004 },
1005 {
1006 .start = DAVINCI_DMA_VC_TX,
1007 .end = DAVINCI_DMA_VC_TX,
1008 .flags = IORESOURCE_DMA,
1009 },
1010 {
1011 .start = DAVINCI_DMA_VC_RX,
1012 .end = DAVINCI_DMA_VC_RX,
1013 .flags = IORESOURCE_DMA,
1014 },
1015 };
1016
1017 static struct platform_device dm365_vc_device = {
1018 .name = "davinci_voicecodec",
1019 .id = -1,
1020 .num_resources = ARRAY_SIZE(dm365_vc_resources),
1021 .resource = dm365_vc_resources,
1022 };
1023
1024 static struct resource dm365_rtc_resources[] = {
1025 {
1026 .start = DM365_RTC_BASE,
1027 .end = DM365_RTC_BASE + SZ_1K - 1,
1028 .flags = IORESOURCE_MEM,
1029 },
1030 {
1031 .start = IRQ_DM365_RTCINT,
1032 .flags = IORESOURCE_IRQ,
1033 },
1034 };
1035
1036 static struct platform_device dm365_rtc_device = {
1037 .name = "rtc_davinci",
1038 .id = 0,
1039 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
1040 .resource = dm365_rtc_resources,
1041 };
1042
1043 static struct map_desc dm365_io_desc[] = {
1044 {
1045 .virtual = IO_VIRT,
1046 .pfn = __phys_to_pfn(IO_PHYS),
1047 .length = IO_SIZE,
1048 .type = MT_DEVICE
1049 },
1050 };
1051
1052 static struct resource dm365_ks_resources[] = {
1053 {
1054 /* registers */
1055 .start = DM365_KEYSCAN_BASE,
1056 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
1057 .flags = IORESOURCE_MEM,
1058 },
1059 {
1060 /* interrupt */
1061 .start = IRQ_DM365_KEYINT,
1062 .end = IRQ_DM365_KEYINT,
1063 .flags = IORESOURCE_IRQ,
1064 },
1065 };
1066
1067 static struct platform_device dm365_ks_device = {
1068 .name = "davinci_keyscan",
1069 .id = 0,
1070 .num_resources = ARRAY_SIZE(dm365_ks_resources),
1071 .resource = dm365_ks_resources,
1072 };
1073
1074 /* Contents of JTAG ID register used to identify exact cpu type */
1075 static struct davinci_id dm365_ids[] = {
1076 {
1077 .variant = 0x0,
1078 .part_no = 0xb83e,
1079 .manufacturer = 0x017,
1080 .cpu_id = DAVINCI_CPU_ID_DM365,
1081 .name = "dm365_rev1.1",
1082 },
1083 {
1084 .variant = 0x8,
1085 .part_no = 0xb83e,
1086 .manufacturer = 0x017,
1087 .cpu_id = DAVINCI_CPU_ID_DM365,
1088 .name = "dm365_rev1.2",
1089 },
1090 };
1091
1092 static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1093
1094 static struct davinci_timer_info dm365_timer_info = {
1095 .timers = davinci_timer_instance,
1096 .clockevent_id = T0_BOT,
1097 .clocksource_id = T0_TOP,
1098 };
1099
1100 #define DM365_UART1_BASE (IO_PHYS + 0x106000)
1101
1102 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
1103 {
1104 .mapbase = DAVINCI_UART0_BASE,
1105 .irq = IRQ_UARTINT0,
1106 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1107 UPF_IOREMAP,
1108 .iotype = UPIO_MEM,
1109 .regshift = 2,
1110 },
1111 {
1112 .flags = 0,
1113 }
1114 };
1115 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
1116 {
1117 .mapbase = DM365_UART1_BASE,
1118 .irq = IRQ_UARTINT1,
1119 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1120 UPF_IOREMAP,
1121 .iotype = UPIO_MEM,
1122 .regshift = 2,
1123 },
1124 {
1125 .flags = 0,
1126 }
1127 };
1128
1129 struct platform_device dm365_serial_device[] = {
1130 {
1131 .name = "serial8250",
1132 .id = PLAT8250_DEV_PLATFORM,
1133 .dev = {
1134 .platform_data = dm365_serial0_platform_data,
1135 }
1136 },
1137 {
1138 .name = "serial8250",
1139 .id = PLAT8250_DEV_PLATFORM1,
1140 .dev = {
1141 .platform_data = dm365_serial1_platform_data,
1142 }
1143 },
1144 {
1145 }
1146 };
1147
1148 static struct davinci_soc_info davinci_soc_info_dm365 = {
1149 .io_desc = dm365_io_desc,
1150 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
1151 .jtag_id_reg = 0x01c40028,
1152 .ids = dm365_ids,
1153 .ids_num = ARRAY_SIZE(dm365_ids),
1154 .cpu_clks = dm365_clks,
1155 .psc_bases = dm365_psc_bases,
1156 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
1157 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
1158 .pinmux_pins = dm365_pins,
1159 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
1160 .intc_base = DAVINCI_ARM_INTC_BASE,
1161 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1162 .intc_irq_prios = dm365_default_priorities,
1163 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1164 .timer_info = &dm365_timer_info,
1165 .emac_pdata = &dm365_emac_pdata,
1166 .sram_dma = 0x00010000,
1167 .sram_len = SZ_32K,
1168 };
1169
1170 void __init dm365_init_asp(void)
1171 {
1172 davinci_cfg_reg(DM365_MCBSP0_BDX);
1173 davinci_cfg_reg(DM365_MCBSP0_X);
1174 davinci_cfg_reg(DM365_MCBSP0_BFSX);
1175 davinci_cfg_reg(DM365_MCBSP0_BDR);
1176 davinci_cfg_reg(DM365_MCBSP0_R);
1177 davinci_cfg_reg(DM365_MCBSP0_BFSR);
1178 davinci_cfg_reg(DM365_EVT2_ASP_TX);
1179 davinci_cfg_reg(DM365_EVT3_ASP_RX);
1180 platform_device_register(&dm365_asp_device);
1181 }
1182
1183 void __init dm365_init_vc(void)
1184 {
1185 davinci_cfg_reg(DM365_EVT2_VC_TX);
1186 davinci_cfg_reg(DM365_EVT3_VC_RX);
1187 platform_device_register(&dm365_vc_device);
1188 }
1189
1190 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1191 {
1192 dm365_ks_device.dev.platform_data = pdata;
1193 platform_device_register(&dm365_ks_device);
1194 }
1195
1196 void __init dm365_init_rtc(void)
1197 {
1198 davinci_cfg_reg(DM365_INT_PRTCSS);
1199 platform_device_register(&dm365_rtc_device);
1200 }
1201
1202 void __init dm365_init(void)
1203 {
1204 davinci_common_init(&davinci_soc_info_dm365);
1205 davinci_map_sysmod();
1206 davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
1207 }
1208
1209 static struct resource dm365_vpss_resources[] = {
1210 {
1211 /* VPSS ISP5 Base address */
1212 .name = "isp5",
1213 .start = 0x01c70000,
1214 .end = 0x01c70000 + 0xff,
1215 .flags = IORESOURCE_MEM,
1216 },
1217 {
1218 /* VPSS CLK Base address */
1219 .name = "vpss",
1220 .start = 0x01c70200,
1221 .end = 0x01c70200 + 0xff,
1222 .flags = IORESOURCE_MEM,
1223 },
1224 };
1225
1226 static struct platform_device dm365_vpss_device = {
1227 .name = "vpss",
1228 .id = -1,
1229 .dev.platform_data = "dm365_vpss",
1230 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
1231 .resource = dm365_vpss_resources,
1232 };
1233
1234 static struct resource vpfe_resources[] = {
1235 {
1236 .start = IRQ_VDINT0,
1237 .end = IRQ_VDINT0,
1238 .flags = IORESOURCE_IRQ,
1239 },
1240 {
1241 .start = IRQ_VDINT1,
1242 .end = IRQ_VDINT1,
1243 .flags = IORESOURCE_IRQ,
1244 },
1245 };
1246
1247 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1248 static struct platform_device vpfe_capture_dev = {
1249 .name = CAPTURE_DRV_NAME,
1250 .id = -1,
1251 .num_resources = ARRAY_SIZE(vpfe_resources),
1252 .resource = vpfe_resources,
1253 .dev = {
1254 .dma_mask = &vpfe_capture_dma_mask,
1255 .coherent_dma_mask = DMA_BIT_MASK(32),
1256 },
1257 };
1258
1259 static void dm365_isif_setup_pinmux(void)
1260 {
1261 davinci_cfg_reg(DM365_VIN_CAM_WEN);
1262 davinci_cfg_reg(DM365_VIN_CAM_VD);
1263 davinci_cfg_reg(DM365_VIN_CAM_HD);
1264 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1265 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1266 }
1267
1268 static struct resource isif_resource[] = {
1269 /* ISIF Base address */
1270 {
1271 .start = 0x01c71000,
1272 .end = 0x01c71000 + 0x1ff,
1273 .flags = IORESOURCE_MEM,
1274 },
1275 /* ISIF Linearization table 0 */
1276 {
1277 .start = 0x1C7C000,
1278 .end = 0x1C7C000 + 0x2ff,
1279 .flags = IORESOURCE_MEM,
1280 },
1281 /* ISIF Linearization table 1 */
1282 {
1283 .start = 0x1C7C400,
1284 .end = 0x1C7C400 + 0x2ff,
1285 .flags = IORESOURCE_MEM,
1286 },
1287 };
1288 static struct platform_device dm365_isif_dev = {
1289 .name = "isif",
1290 .id = -1,
1291 .num_resources = ARRAY_SIZE(isif_resource),
1292 .resource = isif_resource,
1293 .dev = {
1294 .dma_mask = &vpfe_capture_dma_mask,
1295 .coherent_dma_mask = DMA_BIT_MASK(32),
1296 .platform_data = dm365_isif_setup_pinmux,
1297 },
1298 };
1299
1300 static struct resource dm365_osd_resources[] = {
1301 {
1302 .start = DM365_OSD_BASE,
1303 .end = DM365_OSD_BASE + 0xff,
1304 .flags = IORESOURCE_MEM,
1305 },
1306 };
1307
1308 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
1309
1310 static struct platform_device dm365_osd_dev = {
1311 .name = DM365_VPBE_OSD_SUBDEV_NAME,
1312 .id = -1,
1313 .num_resources = ARRAY_SIZE(dm365_osd_resources),
1314 .resource = dm365_osd_resources,
1315 .dev = {
1316 .dma_mask = &dm365_video_dma_mask,
1317 .coherent_dma_mask = DMA_BIT_MASK(32),
1318 },
1319 };
1320
1321 static struct resource dm365_venc_resources[] = {
1322 {
1323 .start = IRQ_VENCINT,
1324 .end = IRQ_VENCINT,
1325 .flags = IORESOURCE_IRQ,
1326 },
1327 /* venc registers io space */
1328 {
1329 .start = DM365_VENC_BASE,
1330 .end = DM365_VENC_BASE + 0x177,
1331 .flags = IORESOURCE_MEM,
1332 },
1333 /* vdaccfg registers io space */
1334 {
1335 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
1336 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
1337 .flags = IORESOURCE_MEM,
1338 },
1339 };
1340
1341 static struct resource dm365_v4l2_disp_resources[] = {
1342 {
1343 .start = IRQ_VENCINT,
1344 .end = IRQ_VENCINT,
1345 .flags = IORESOURCE_IRQ,
1346 },
1347 /* venc registers io space */
1348 {
1349 .start = DM365_VENC_BASE,
1350 .end = DM365_VENC_BASE + 0x177,
1351 .flags = IORESOURCE_MEM,
1352 },
1353 };
1354
1355 static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
1356 {
1357 switch (if_type) {
1358 case MEDIA_BUS_FMT_SGRBG8_1X8:
1359 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1360 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1361 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1362 break;
1363 case MEDIA_BUS_FMT_YUYV10_1X20:
1364 if (field)
1365 davinci_cfg_reg(DM365_VOUT_FIELD);
1366 else
1367 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1368 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1369 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1370 break;
1371 default:
1372 return -EINVAL;
1373 }
1374
1375 return 0;
1376 }
1377
1378 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
1379 unsigned int pclock)
1380 {
1381 void __iomem *vpss_clkctl_reg;
1382 u32 val;
1383
1384 vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
1385
1386 switch (type) {
1387 case VPBE_ENC_STD:
1388 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1389 break;
1390 case VPBE_ENC_DV_TIMINGS:
1391 if (pclock <= 27000000) {
1392 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1393 } else {
1394 /* set sysclk4 to output 74.25 MHz from pll1 */
1395 val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
1396 VPSS_VENCCLKEN_ENABLE;
1397 }
1398 break;
1399 default:
1400 return -EINVAL;
1401 }
1402 writel(val, vpss_clkctl_reg);
1403
1404 return 0;
1405 }
1406
1407 static struct platform_device dm365_vpbe_display = {
1408 .name = "vpbe-v4l2",
1409 .id = -1,
1410 .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
1411 .resource = dm365_v4l2_disp_resources,
1412 .dev = {
1413 .dma_mask = &dm365_video_dma_mask,
1414 .coherent_dma_mask = DMA_BIT_MASK(32),
1415 },
1416 };
1417
1418 static struct venc_platform_data dm365_venc_pdata = {
1419 .setup_pinmux = dm365_vpbe_setup_pinmux,
1420 .setup_clock = dm365_venc_setup_clock,
1421 };
1422
1423 static struct platform_device dm365_venc_dev = {
1424 .name = DM365_VPBE_VENC_SUBDEV_NAME,
1425 .id = -1,
1426 .num_resources = ARRAY_SIZE(dm365_venc_resources),
1427 .resource = dm365_venc_resources,
1428 .dev = {
1429 .dma_mask = &dm365_video_dma_mask,
1430 .coherent_dma_mask = DMA_BIT_MASK(32),
1431 .platform_data = (void *)&dm365_venc_pdata,
1432 },
1433 };
1434
1435 static struct platform_device dm365_vpbe_dev = {
1436 .name = "vpbe_controller",
1437 .id = -1,
1438 .dev = {
1439 .dma_mask = &dm365_video_dma_mask,
1440 .coherent_dma_mask = DMA_BIT_MASK(32),
1441 },
1442 };
1443
1444 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1445 struct vpbe_config *vpbe_cfg)
1446 {
1447 if (vpfe_cfg || vpbe_cfg)
1448 platform_device_register(&dm365_vpss_device);
1449
1450 if (vpfe_cfg) {
1451 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1452 platform_device_register(&dm365_isif_dev);
1453 platform_device_register(&vpfe_capture_dev);
1454 }
1455 if (vpbe_cfg) {
1456 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1457 platform_device_register(&dm365_osd_dev);
1458 platform_device_register(&dm365_venc_dev);
1459 platform_device_register(&dm365_vpbe_dev);
1460 platform_device_register(&dm365_vpbe_display);
1461 }
1462
1463 return 0;
1464 }
1465
1466 static int __init dm365_init_devices(void)
1467 {
1468 struct platform_device *edma_pdev;
1469 int ret = 0;
1470
1471 if (!cpu_is_davinci_dm365())
1472 return 0;
1473
1474 davinci_cfg_reg(DM365_INT_EDMA_CC);
1475 edma_pdev = platform_device_register_full(&dm365_edma_device);
1476 if (IS_ERR(edma_pdev)) {
1477 pr_warn("%s: Failed to register eDMA\n", __func__);
1478 return PTR_ERR(edma_pdev);
1479 }
1480
1481 platform_device_register(&dm365_mdio_device);
1482 platform_device_register(&dm365_emac_device);
1483
1484 ret = davinci_init_wdt();
1485 if (ret)
1486 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1487
1488 return ret;
1489 }
1490 postcore_initcall(dm365_init_devices);
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